1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY UCLASS_RAM
17 #include <dm/device_compat.h>
18 #include "stm32mp1_ddr.h"
19 #include "stm32mp1_ddr_regs.h"
21 /* DDR subsystem configuration */
22 struct stm32mp1_ddr_cfg {
23 u8 nb_bytes; /* MEMC_DRAM_DATA_WIDTH */
26 static const char *const clkname[] = {
31 "ddrphyc" /* LAST clock => used for get_rate() */
34 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
36 unsigned long ddrphy_clk;
37 unsigned long ddr_clk;
42 for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
43 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
46 ret = clk_enable(&clk);
49 log_err("error for %s : %d\n", clkname[idx], ret);
55 ddrphy_clk = clk_get_rate(&priv->clk);
57 log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
58 mem_speed, (u32)(ddrphy_clk / 1000));
59 /* max 10% frequency delta */
60 ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
61 if (ddr_clk > (mem_speed * 100)) {
62 log_err("DDR expected freq %d kHz, current is %d kHz\n",
63 mem_speed, (u32)(ddrphy_clk / 1000));
70 __weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
73 return 0; /* Always match */
76 static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
81 dev_for_each_subnode(node, dev) {
82 name = ofnode_get_property(node, "compatible", NULL);
84 if (!board_stm32mp1_ddr_config_name_match(dev, name))
88 return dev_ofnode(dev);
91 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
93 struct ddr_info *priv = dev_get_priv(dev);
97 struct stm32mp1_ddr_config config;
98 ofnode node = stm32mp1_ddr_get_ofnode(dev);
100 #define PARAM(x, y, z) \
102 .offset = offsetof(struct stm32mp1_ddr_config, y), \
103 .size = sizeof(config.y) / sizeof(u32), \
106 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
107 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
110 const char *name; /* name in DT */
111 const u32 offset; /* offset in config struct */
112 const u32 size; /* size of parameters */
122 config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
123 config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
124 config.info.name = ofnode_read_string(node, "st,mem-name");
125 if (!config.info.name) {
126 dev_dbg(dev, "no st,mem-name\n");
129 printf("RAM: %s\n", config.info.name);
131 for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
132 ret = ofnode_read_u32_array(node, param[idx].name,
133 (void *)((u32)&config +
136 dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
137 param[idx].name, param[idx].size, ret);
139 dev_err(dev, "Cannot read %s, error=%d\n",
140 param[idx].name, ret);
145 ret = clk_get_by_name(dev, "axidcg", &axidcg);
147 dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
150 clk_disable(&axidcg); /* disable clock gating during init */
152 stm32mp1_ddr_init(priv, &config);
154 clk_enable(&axidcg); /* enable clock gating */
157 dev_dbg(dev, "get_ram_size(%x, %x)\n",
158 (u32)priv->info.base, (u32)STM32_DDR_SIZE);
160 priv->info.size = get_ram_size((long *)priv->info.base,
163 dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
165 /* check memory access for all memory */
166 if (config.info.size != priv->info.size) {
167 printf("DDR invalid size : 0x%x, expected 0x%x\n",
168 priv->info.size, config.info.size);
174 static u8 get_data_bus_width(struct stm32mp1_ddrctl *ctl)
176 u32 reg = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
177 u8 data_bus_width = reg >> DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
179 return data_bus_width;
182 static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
184 /* Count bank address bits */
188 reg = readl(&ctl->addrmap1);
189 /* addrmap1.addrmap_bank_b1 */
190 val = (reg & GENMASK(5, 0)) >> 0;
193 /* addrmap1.addrmap_bank_b2 */
194 val = (reg & GENMASK(13, 8)) >> 8;
197 /* addrmap1.addrmap_bank_b3 */
198 val = (reg & GENMASK(21, 16)) >> 16;
205 static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
210 /* Count column address bits, start at 2 for b0 and b1 (fixed) */
213 reg = readl(&ctl->addrmap2);
214 /* addrmap2.addrmap_col_b2 */
215 val = (reg & GENMASK(3, 0)) >> 0;
218 /* addrmap2.addrmap_col_b3 */
219 val = (reg & GENMASK(11, 8)) >> 8;
222 /* addrmap2.addrmap_col_b4 */
223 val = (reg & GENMASK(19, 16)) >> 16;
226 /* addrmap2.addrmap_col_b5 */
227 val = (reg & GENMASK(27, 24)) >> 24;
231 reg = readl(&ctl->addrmap3);
232 /* addrmap3.addrmap_col_b6 */
233 val = (reg & GENMASK(3, 0)) >> 0;
236 /* addrmap3.addrmap_col_b7 */
237 val = (reg & GENMASK(11, 8)) >> 8;
240 /* addrmap3.addrmap_col_b8 */
241 val = (reg & GENMASK(19, 16)) >> 16;
244 /* addrmap3.addrmap_col_b9 */
245 val = (reg & GENMASK(27, 24)) >> 24;
249 reg = readl(&ctl->addrmap4);
250 /* addrmap4.addrmap_col_b10 */
251 val = (reg & GENMASK(3, 0)) >> 0;
254 /* addrmap4.addrmap_col_b11 */
255 val = (reg & GENMASK(11, 8)) >> 8;
260 * column bits shift up:
261 * 1 when half the data bus is used (data_bus_width = 1)
262 * 2 when a quarter the data bus is used (data_bus_width = 2)
263 * nothing to do for full data bus (data_bus_width = 0)
265 bits += data_bus_width;
270 static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
272 /* Count row address bits */
276 reg = readl(&ctl->addrmap5);
277 /* addrmap5.addrmap_row_b0 */
278 val = (reg & GENMASK(3, 0)) >> 0;
281 /* addrmap5.addrmap_row_b1 */
282 val = (reg & GENMASK(11, 8)) >> 8;
285 /* addrmap5.addrmap_row_b2_10 */
286 val = (reg & GENMASK(19, 16)) >> 16;
290 printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
291 /* addrmap5.addrmap_row_b11 */
292 val = (reg & GENMASK(27, 24)) >> 24;
296 reg = readl(&ctl->addrmap6);
297 /* addrmap6.addrmap_row_b12 */
298 val = (reg & GENMASK(3, 0)) >> 0;
301 /* addrmap6.addrmap_row_b13 */
302 val = (reg & GENMASK(11, 8)) >> 8;
305 /* addrmap6.addrmap_row_b14 */
306 val = (reg & GENMASK(19, 16)) >> 16;
309 /* addrmap6.addrmap_row_b15 */
310 val = (reg & GENMASK(27, 24)) >> 24;
320 * Get the current DRAM size from the DDR CTL registers
324 u32 stm32mp1_ddr_size(struct udevice *dev)
329 struct ddr_info *priv = dev_get_priv(dev);
330 struct stm32mp1_ddrctl *ctl = priv->ctl;
331 struct stm32mp1_ddr_cfg *cfg = (struct stm32mp1_ddr_cfg *)dev_get_driver_data(dev);
332 const u8 nb_bytes = cfg->nb_bytes;
334 data_bus_width = get_data_bus_width(ctl);
335 nb_bit = get_nb_bank(ctl) + get_nb_col(ctl, data_bus_width) +
339 debug("invalid DDR configuration: %d bits\n", nb_bit);
342 ddr_size = (nb_bytes >> data_bus_width) << nb_bit;
343 if (ddr_size > STM32_DDR_SIZE) {
344 ddr_size = STM32_DDR_SIZE;
345 debug("invalid DDR configuration: size = %x\n", ddr_size);
351 static int stm32mp1_ddr_probe(struct udevice *dev)
353 struct ddr_info *priv = dev_get_priv(dev);
359 ret = regmap_init_mem(dev_ofnode(dev), &map);
363 priv->ctl = regmap_get_range(map, 0);
364 priv->phy = regmap_get_range(map, 1);
366 priv->rcc = STM32_RCC_BASE;
368 priv->info.base = STM32_DDR_BASE;
370 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
372 ret = stm32mp1_ddr_setup(dev);
377 priv->info.size = stm32mp1_ddr_size(dev);
382 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
384 struct ddr_info *priv = dev_get_priv(dev);
391 static struct ram_ops stm32mp1_ddr_ops = {
392 .get_info = stm32mp1_ddr_get_info,
395 static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
399 static const struct udevice_id stm32mp1_ddr_ids[] = {
400 { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
404 U_BOOT_DRIVER(ddr_stm32mp1) = {
405 .name = "stm32mp1_ddr",
407 .of_match = stm32mp1_ddr_ids,
408 .ops = &stm32mp1_ddr_ops,
409 .probe = stm32mp1_ddr_probe,
410 .priv_auto = sizeof(struct ddr_info),