drivers/ram/stm32mp1/stm32mp1_ram.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_RAM
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/io.h>
  17 #include <dm/device_compat.h>
  18 #include "stm32mp1_ddr.h"
  19
  20 static const char *const clkname[] = {
  21         "ddrc1",
  22         "ddrc2",
  23         "ddrcapb",
  24         "ddrphycapb",
  25         "ddrphyc" /* LAST clock => used for get_rate() */
  26 };
  27
  28 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  29 {
  30         unsigned long ddrphy_clk;
  31         unsigned long ddr_clk;
  32         struct clk clk;
  33         int ret;
  34         unsigned int idx;
  35
  36         for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  37                 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  38
  39                 if (!ret)
  40                         ret = clk_enable(&clk);
  41
  42                 if (ret) {
  43                         log_err("error for %s : %d\n", clkname[idx], ret);
  44                         return ret;
  45                 }
  46         }
  47
  48         priv->clk = clk;
  49         ddrphy_clk = clk_get_rate(&priv->clk);
  50
  51         log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  52                   mem_speed, (u32)(ddrphy_clk / 1000));
  53         /* max 10% frequency delta */
  54         ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  55         if (ddr_clk > (mem_speed * 100)) {
  56                 log_err("DDR expected freq %d kHz, current is %d kHz\n",
  57                         mem_speed, (u32)(ddrphy_clk / 1000));
  58                 return -EINVAL;
  59         }
  60
  61         return 0;
  62 }
  63
  64 __weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  65                                                 const char *name)
  66 {
  67         return 0;       /* Always match */
  68 }
  69
  70 static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
  71 {
  72         const char *name;
  73         ofnode node;
  74
  75         dev_for_each_subnode(node, dev) {
  76                 name = ofnode_get_property(node, "compatible", NULL);
  77
  78                 if (!board_stm32mp1_ddr_config_name_match(dev, name))
  79                         return node;
  80         }
  81
  82         return dev_ofnode(dev);
  83 }
  84
  85 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  86 {
  87         struct ddr_info *priv = dev_get_priv(dev);
  88         int ret;
  89         unsigned int idx;
  90         struct clk axidcg;
  91         struct stm32mp1_ddr_config config;
  92         ofnode node = stm32mp1_ddr_get_ofnode(dev);
  93
  94 #define PARAM(x, y, z)                                                  \
  95         {       .name = x,                                              \
  96                 .offset = offsetof(struct stm32mp1_ddr_config, y),      \
  97                 .size = sizeof(config.y) / sizeof(u32),                 \
  98                 .present = z,                                           \
  99         }
 100
 101 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
 102 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
 103 #define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
 104
 105         const struct {
 106                 const char *name; /* name in DT */
 107                 const u32 offset; /* offset in config struct */
 108                 const u32 size;   /* size of parameters */
 109                 bool * const present;  /* presence indication for opt */
 110         } param[] = {
 111                 CTL_PARAM(reg),
 112                 CTL_PARAM(timing),
 113                 CTL_PARAM(map),
 114                 CTL_PARAM(perf),
 115                 PHY_PARAM(reg),
 116                 PHY_PARAM(timing),
 117                 PHY_PARAM_OPT(cal)
 118         };
 119
 120         config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
 121         config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 122         config.info.name = ofnode_read_string(node, "st,mem-name");
 123         if (!config.info.name) {
 124                 dev_dbg(dev, "no st,mem-name\n");
 125                 return -EINVAL;
 126         }
 127         printf("RAM: %s\n", config.info.name);
 128
 129         for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
 130                 ret = ofnode_read_u32_array(node, param[idx].name,
 131                                          (void *)((u32)&config +
 132                                                   param[idx].offset),
 133                                          param[idx].size);
 134                 dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
 135                         param[idx].name, param[idx].size, ret);
 136                 if (ret &&
 137                     (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
 138                         dev_err(dev, "Cannot read %s, error=%d\n",
 139                                 param[idx].name, ret);
 140                         return -EINVAL;
 141                 }
 142                 if (param[idx].present) {
 143                         /* save presence of optional parameters */
 144                         *param[idx].present = true;
 145                         if (ret == -FDT_ERR_NOTFOUND) {
 146                                 *param[idx].present = false;
 147 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 148                                 /* reset values if used later */
 149                                 memset((void *)((u32)&config +
 150                                                 param[idx].offset),
 151                                         0, param[idx].size * sizeof(u32));
 152 #endif
 153                         }
 154                 }
 155         }
 156
 157         ret = clk_get_by_name(dev, "axidcg", &axidcg);
 158         if (ret) {
 159                 dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
 160                 return -EINVAL;
 161         }
 162         clk_disable(&axidcg); /* disable clock gating during init */
 163
 164         stm32mp1_ddr_init(priv, &config);
 165
 166         clk_enable(&axidcg); /* enable clock gating */
 167
 168         /* check size */
 169         dev_dbg(dev, "get_ram_size(%x, %x)\n",
 170                 (u32)priv->info.base, (u32)STM32_DDR_SIZE);
 171
 172         priv->info.size = get_ram_size((long *)priv->info.base,
 173                                        STM32_DDR_SIZE);
 174
 175         dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
 176
 177         /* check memory access for all memory */
 178         if (config.info.size != priv->info.size) {
 179                 printf("DDR invalid size : 0x%x, expected 0x%x\n",
 180                        priv->info.size, config.info.size);
 181                 return -EINVAL;
 182         }
 183         return 0;
 184 }
 185
 186 static int stm32mp1_ddr_probe(struct udevice *dev)
 187 {
 188         struct ddr_info *priv = dev_get_priv(dev);
 189         struct regmap *map;
 190         int ret;
 191
 192         priv->dev = dev;
 193
 194         ret = regmap_init_mem(dev_ofnode(dev), &map);
 195         if (ret)
 196                 return log_ret(ret);
 197
 198         priv->ctl = regmap_get_range(map, 0);
 199         priv->phy = regmap_get_range(map, 1);
 200
 201         priv->rcc = STM32_RCC_BASE;
 202
 203         priv->info.base = STM32_DDR_BASE;
 204
 205 #if !defined(CONFIG_TFABOOT) && \
 206         (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 207         priv->info.size = 0;
 208         ret = stm32mp1_ddr_setup(dev);
 209
 210         return log_ret(ret);
 211 #else
 212         ofnode node = stm32mp1_ddr_get_ofnode(dev);
 213         priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 214         return 0;
 215 #endif
 216 }
 217
 218 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
 219 {
 220         struct ddr_info *priv = dev_get_priv(dev);
 221
 222         *info = priv->info;
 223
 224         return 0;
 225 }
 226
 227 static struct ram_ops stm32mp1_ddr_ops = {
 228         .get_info = stm32mp1_ddr_get_info,
 229 };
 230
 231 static const struct udevice_id stm32mp1_ddr_ids[] = {
 232         { .compatible = "st,stm32mp1-ddr" },
 233         { }
 234 };
 235
 236 U_BOOT_DRIVER(ddr_stm32mp1) = {
 237         .name = "stm32mp1_ddr",
 238         .id = UCLASS_RAM,
 239         .of_match = stm32mp1_ddr_ids,
 240         .ops = &stm32mp1_ddr_ops,
 241         .probe = stm32mp1_ddr_probe,
 242         .priv_auto      = sizeof(struct ddr_info),
 243 };