1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 #include <asm/arch/ddr.h>
14 #include <linux/delay.h>
15 #include <linux/iopoll.h>
16 #include "stm32mp1_ddr.h"
17 #include "stm32mp1_ddr_regs.h"
19 #define RCC_DDRITFCR 0xD8
21 #define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
22 #define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
23 #define RCC_DDRITFCR_DDRCORERST (BIT(16))
24 #define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
25 #define RCC_DDRITFCR_DPHYRST (BIT(18))
26 #define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
30 u16 offset; /* offset for base address */
31 u8 par_offset; /* offset for parameter array */
34 #define INVALID_OFFSET 0xFF
36 #define DDRCTL_REG(x, y) \
38 offsetof(struct stm32mp1_ddrctl, x),\
39 offsetof(struct y, x)}
41 #define DDRPHY_REG(x, y) \
43 offsetof(struct stm32mp1_ddrphy, x),\
44 offsetof(struct y, x)}
46 #define DDR_REG_DYN(x) \
48 offsetof(struct stm32mp1_ddrctl, x),\
51 #define DDRPHY_REG_DYN(x) \
53 offsetof(struct stm32mp1_ddrphy, x),\
56 /***********************************************************
57 * PARAMETERS: value get from device tree :
58 * size / order need to be aligned with binding
59 * modification NOT ALLOWED !!!
60 ***********************************************************/
61 #define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
62 #define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
63 #define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
64 #define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
66 #define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
67 #define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
68 #define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
70 #define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
71 static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
73 DDRCTL_REG_REG(mrctrl0),
74 DDRCTL_REG_REG(mrctrl1),
75 DDRCTL_REG_REG(derateen),
76 DDRCTL_REG_REG(derateint),
77 DDRCTL_REG_REG(pwrctl),
78 DDRCTL_REG_REG(pwrtmg),
79 DDRCTL_REG_REG(hwlpctl),
80 DDRCTL_REG_REG(rfshctl0),
81 DDRCTL_REG_REG(rfshctl3),
82 DDRCTL_REG_REG(crcparctl0),
83 DDRCTL_REG_REG(zqctl0),
84 DDRCTL_REG_REG(dfitmg0),
85 DDRCTL_REG_REG(dfitmg1),
86 DDRCTL_REG_REG(dfilpcfg0),
87 DDRCTL_REG_REG(dfiupd0),
88 DDRCTL_REG_REG(dfiupd1),
89 DDRCTL_REG_REG(dfiupd2),
90 DDRCTL_REG_REG(dfiphymstr),
91 DDRCTL_REG_REG(odtmap),
94 DDRCTL_REG_REG(dbgcmd),
95 DDRCTL_REG_REG(poisoncfg),
96 DDRCTL_REG_REG(pccfg),
99 #define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
100 static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
101 DDRCTL_REG_TIMING(rfshtmg),
102 DDRCTL_REG_TIMING(dramtmg0),
103 DDRCTL_REG_TIMING(dramtmg1),
104 DDRCTL_REG_TIMING(dramtmg2),
105 DDRCTL_REG_TIMING(dramtmg3),
106 DDRCTL_REG_TIMING(dramtmg4),
107 DDRCTL_REG_TIMING(dramtmg5),
108 DDRCTL_REG_TIMING(dramtmg6),
109 DDRCTL_REG_TIMING(dramtmg7),
110 DDRCTL_REG_TIMING(dramtmg8),
111 DDRCTL_REG_TIMING(dramtmg14),
112 DDRCTL_REG_TIMING(odtcfg),
115 #define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
116 static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
117 DDRCTL_REG_MAP(addrmap1),
118 DDRCTL_REG_MAP(addrmap2),
119 DDRCTL_REG_MAP(addrmap3),
120 DDRCTL_REG_MAP(addrmap4),
121 DDRCTL_REG_MAP(addrmap5),
122 DDRCTL_REG_MAP(addrmap6),
123 DDRCTL_REG_MAP(addrmap9),
124 DDRCTL_REG_MAP(addrmap10),
125 DDRCTL_REG_MAP(addrmap11),
128 #define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
129 static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
130 DDRCTL_REG_PERF(sched),
131 DDRCTL_REG_PERF(sched1),
132 DDRCTL_REG_PERF(perfhpr1),
133 DDRCTL_REG_PERF(perflpr1),
134 DDRCTL_REG_PERF(perfwr1),
135 DDRCTL_REG_PERF(pcfgr_0),
136 DDRCTL_REG_PERF(pcfgw_0),
137 DDRCTL_REG_PERF(pcfgqos0_0),
138 DDRCTL_REG_PERF(pcfgqos1_0),
139 DDRCTL_REG_PERF(pcfgwqos0_0),
140 DDRCTL_REG_PERF(pcfgwqos1_0),
141 DDRCTL_REG_PERF(pcfgr_1),
142 DDRCTL_REG_PERF(pcfgw_1),
143 DDRCTL_REG_PERF(pcfgqos0_1),
144 DDRCTL_REG_PERF(pcfgqos1_1),
145 DDRCTL_REG_PERF(pcfgwqos0_1),
146 DDRCTL_REG_PERF(pcfgwqos1_1),
149 #define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
150 static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
151 DDRPHY_REG_REG(pgcr),
152 DDRPHY_REG_REG(aciocr),
153 DDRPHY_REG_REG(dxccr),
154 DDRPHY_REG_REG(dsgcr),
156 DDRPHY_REG_REG(odtcr),
157 DDRPHY_REG_REG(zq0cr1),
158 DDRPHY_REG_REG(dx0gcr),
159 DDRPHY_REG_REG(dx1gcr),
160 DDRPHY_REG_REG(dx2gcr),
161 DDRPHY_REG_REG(dx3gcr),
164 #define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
165 static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
166 DDRPHY_REG_TIMING(ptr0),
167 DDRPHY_REG_TIMING(ptr1),
168 DDRPHY_REG_TIMING(ptr2),
169 DDRPHY_REG_TIMING(dtpr0),
170 DDRPHY_REG_TIMING(dtpr1),
171 DDRPHY_REG_TIMING(dtpr2),
172 DDRPHY_REG_TIMING(mr0),
173 DDRPHY_REG_TIMING(mr1),
174 DDRPHY_REG_TIMING(mr2),
175 DDRPHY_REG_TIMING(mr3),
178 #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
179 static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
180 DDRPHY_REG_CAL(dx0dllcr),
181 DDRPHY_REG_CAL(dx0dqtr),
182 DDRPHY_REG_CAL(dx0dqstr),
183 DDRPHY_REG_CAL(dx1dllcr),
184 DDRPHY_REG_CAL(dx1dqtr),
185 DDRPHY_REG_CAL(dx1dqstr),
186 DDRPHY_REG_CAL(dx2dllcr),
187 DDRPHY_REG_CAL(dx2dqtr),
188 DDRPHY_REG_CAL(dx2dqstr),
189 DDRPHY_REG_CAL(dx3dllcr),
190 DDRPHY_REG_CAL(dx3dqtr),
191 DDRPHY_REG_CAL(dx3dqstr),
194 /**************************************************************
195 * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
196 **************************************************************/
197 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
198 static const struct reg_desc ddr_dyn[] = {
201 DDR_REG_DYN(dfimisc),
202 DDR_REG_DYN(dfistat),
205 DDR_REG_DYN(pctrl_0),
206 DDR_REG_DYN(pctrl_1),
209 #define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn)
211 static const struct reg_desc ddrphy_dyn[] = {
213 DDRPHY_REG_DYN(pgsr),
214 DDRPHY_REG_DYN(zq0sr0),
215 DDRPHY_REG_DYN(zq0sr1),
216 DDRPHY_REG_DYN(dx0gsr0),
217 DDRPHY_REG_DYN(dx0gsr1),
218 DDRPHY_REG_DYN(dx1gsr0),
219 DDRPHY_REG_DYN(dx1gsr1),
220 DDRPHY_REG_DYN(dx2gsr0),
221 DDRPHY_REG_DYN(dx2gsr1),
222 DDRPHY_REG_DYN(dx3gsr0),
223 DDRPHY_REG_DYN(dx3gsr1),
226 #define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
230 /*****************************************************************
231 * REGISTERS ARRAY: used to parse device tree and interactive mode
232 *****************************************************************/
241 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
242 /* dynamic registers => managed in driver or not changed,
243 * can be dumped in interactive mode
257 struct ddr_reg_info {
259 const struct reg_desc *desc;
264 #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
266 const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
268 "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
270 "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
272 "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
274 "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
276 "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
278 "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
280 "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
281 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
283 "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
285 "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
290 const char *base_name[] = {
292 [DDRPHY_BASE] = "phy",
295 static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
297 if (base == DDRPHY_BASE)
298 return (u32)priv->phy;
300 return (u32)priv->ctl;
303 static void set_reg(const struct ddr_info *priv,
308 unsigned int *ptr, value;
309 enum base_type base = ddr_registers[type].base;
310 u32 base_addr = get_base_addr(priv, base);
311 const struct reg_desc *desc = ddr_registers[type].desc;
313 debug("init %s\n", ddr_registers[type].name);
314 for (i = 0; i < ddr_registers[type].size; i++) {
315 ptr = (unsigned int *)(base_addr + desc[i].offset);
316 if (desc[i].par_offset == INVALID_OFFSET) {
317 pr_err("invalid parameter offset for %s", desc[i].name);
319 value = *((u32 *)((u32)param +
320 desc[i].par_offset));
322 debug("[0x%x] %s= 0x%08x\n",
323 (u32)ptr, desc[i].name, value);
328 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
329 static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
333 ptr = (unsigned int *)(base_addr + desc->offset);
334 printf("%s= 0x%08x\n", desc->name, readl(ptr));
337 static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
341 ptr = (unsigned int *)(par_addr + desc->par_offset);
342 printf("%s= 0x%08x\n", desc->name, readl(ptr));
345 static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
348 const struct reg_desc *desc;
350 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
351 desc = ddr_registers[i].desc;
352 for (j = 0; j < ddr_registers[i].size; j++) {
353 if (strcmp(name, desc[j].name) == 0) {
363 int stm32mp1_dump_reg(const struct ddr_info *priv,
367 const struct reg_desc *desc;
369 enum base_type p_base;
372 enum base_type filter = NONE_BASE;
376 if (strcmp(name, base_name[DDR_BASE]) == 0)
378 else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
379 filter = DDRPHY_BASE;
382 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
383 p_base = ddr_registers[i].base;
384 p_name = ddr_registers[i].name;
385 if (!name || (filter == p_base || !strcmp(name, p_name))) {
387 desc = ddr_registers[i].desc;
388 base_addr = get_base_addr(priv, p_base);
389 printf("==%s.%s==\n", base_name[p_base], p_name);
390 for (j = 0; j < ddr_registers[i].size; j++)
391 stm32mp1_dump_reg_desc(base_addr, &desc[j]);
395 desc = found_reg(name, &type);
397 p_base = ddr_registers[type].base;
398 base_addr = get_base_addr(priv, p_base);
399 stm32mp1_dump_reg_desc(base_addr, desc);
406 void stm32mp1_edit_reg(const struct ddr_info *priv,
407 char *name, char *string)
409 unsigned long *ptr, value;
412 const struct reg_desc *desc;
415 desc = found_reg(name, &type);
418 printf("%s not found\n", name);
421 if (strict_strtoul(string, 16, &value) < 0) {
422 printf("invalid value %s\n", string);
425 base = ddr_registers[type].base;
426 base_addr = get_base_addr(priv, base);
427 ptr = (unsigned long *)(base_addr + desc->offset);
429 printf("%s= 0x%08x\n", desc->name, readl(ptr));
432 static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
439 par_addr = (u32)&config->c_reg;
442 par_addr = (u32)&config->c_timing;
445 par_addr = (u32)&config->c_perf;
448 par_addr = (u32)&config->c_map;
451 par_addr = (u32)&config->p_reg;
454 par_addr = (u32)&config->p_timing;
457 par_addr = (u32)&config->p_cal;
462 par_addr = (u32)NULL;
469 int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
473 const struct reg_desc *desc;
475 enum base_type p_base;
478 enum base_type filter = NONE_BASE;
479 int result = -EINVAL;
482 if (strcmp(name, base_name[DDR_BASE]) == 0)
484 else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
485 filter = DDRPHY_BASE;
488 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
489 par_addr = get_par_addr(config, i);
492 p_base = ddr_registers[i].base;
493 p_name = ddr_registers[i].name;
494 if (!name || (filter == p_base || !strcmp(name, p_name))) {
496 desc = ddr_registers[i].desc;
497 printf("==%s.%s==\n", base_name[p_base], p_name);
498 for (j = 0; j < ddr_registers[i].size; j++)
499 stm32mp1_dump_param_desc(par_addr, &desc[j]);
503 desc = found_reg(name, &type);
505 par_addr = get_par_addr(config, type);
507 stm32mp1_dump_param_desc(par_addr, desc);
515 void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
516 char *name, char *string)
518 unsigned long *ptr, value;
520 const struct reg_desc *desc;
523 desc = found_reg(name, &type);
525 printf("%s not found\n", name);
528 if (strict_strtoul(string, 16, &value) < 0) {
529 printf("invalid value %s\n", string);
532 par_addr = get_par_addr(config, type);
534 printf("no parameter %s\n", name);
537 ptr = (unsigned long *)(par_addr + desc->par_offset);
539 printf("%s= 0x%08x\n", desc->name, readl(ptr));
543 __weak bool stm32mp1_ddr_interactive(void *priv,
544 enum stm32mp1_ddr_interact_step step,
545 const struct stm32mp1_ddr_config *config)
550 #define INTERACTIVE(step)\
551 stm32mp1_ddr_interactive(priv, step, config)
553 static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
558 ret = readl_poll_timeout(&phy->pgsr, pgsr,
559 pgsr & (DDRPHYC_PGSR_IDONE |
561 DDRPHYC_PGSR_DTIERR |
562 DDRPHYC_PGSR_DFTERR |
564 DDRPHYC_PGSR_RVEIRR),
566 debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
567 (u32)&phy->pgsr, pgsr, ret);
570 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
572 pir |= DDRPHYC_PIR_INIT;
573 writel(pir, &phy->pir);
574 debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
575 (u32)&phy->pir, pir, readl(&phy->pir));
577 /* need to wait 10 configuration clock before start polling */
580 /* Wait DRAM initialization and Gate Training Evaluation complete */
581 ddrphy_idone_wait(phy);
584 /* start quasi dynamic register update */
585 static void start_sw_done(struct stm32mp1_ddrctl *ctl)
587 clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
590 /* wait quasi dynamic register update */
591 static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
596 setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
598 ret = readl_poll_timeout(&ctl->swstat, swstat,
599 swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
602 panic("Timeout initialising DRAM : DDR->swstat = %x\n",
605 debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
608 /* wait quasi dynamic register update */
609 static void wait_operating_mode(struct ddr_info *priv, int mode)
611 u32 stat, val, mask, val2 = 0, mask2 = 0;
614 mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
616 /* self-refresh due to software => check also STAT.selfref_type */
617 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
618 mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
619 val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
620 } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
621 /* normal mode: handle also automatic self refresh */
622 mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
623 DDRCTRL_STAT_SELFREF_TYPE_MASK;
624 val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
625 DDRCTRL_STAT_SELFREF_TYPE_ASR;
628 ret = readl_poll_timeout(&priv->ctl->stat, stat,
629 ((stat & mask) == val) ||
630 (mask2 && ((stat & mask2) == val2)),
634 panic("Timeout DRAM : DDR->stat = %x\n", stat);
636 debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
639 void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
642 /* quasi-dynamic register update*/
643 setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
644 clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
645 DDRCTRL_PWRCTL_SELFREF_EN);
646 clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
647 wait_sw_done_ack(ctl);
650 void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
651 u32 rfshctl3, u32 pwrctl)
654 if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
655 clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
656 if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
657 setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
658 if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
659 setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
660 setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
661 wait_sw_done_ack(ctl);
664 /* board-specific DDR power initializations. */
665 __weak int board_ddr_power_init(enum ddr_type ddr_type)
671 void stm32mp1_ddr_init(struct ddr_info *priv,
672 const struct stm32mp1_ddr_config *config)
678 switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
679 case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
682 case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
691 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
692 ret = board_ddr_power_init(STM32MP_DDR3);
693 else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
695 ret = board_ddr_power_init(STM32MP_LPDDR2_32);
697 ret = board_ddr_power_init(STM32MP_LPDDR2_16);
698 } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
700 ret = board_ddr_power_init(STM32MP_LPDDR3_32);
702 ret = board_ddr_power_init(STM32MP_LPDDR3_16);
705 panic("ddr power init failed\n");
708 debug("name = %s\n", config->info.name);
709 debug("speed = %d kHz\n", config->info.speed);
710 debug("size = 0x%x\n", config->info.size);
712 * 1. Program the DWC_ddr_umctl2 registers
713 * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
715 /* Assert All DDR part */
716 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
717 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
718 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
719 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
720 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
721 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
723 /* 1.2. start CLOCK */
724 if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
725 panic("invalid DRAM clock : %d kHz\n",
728 /* 1.3. deassert reset */
729 /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
730 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
731 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
732 /* De-assert presetn once the clocks are active
733 * and stable via DDRCAPBRST bit
735 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
737 /* 1.4. wait 128 cycles to permit initialization of end logic */
739 /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
741 if (INTERACTIVE(STEP_DDR_RESET))
744 /* 1.5. initialize registers ddr_umctl2 */
745 /* Stop uMCTL2 before PHY is ready */
746 clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
747 debug("[0x%08x] dfimisc = 0x%08x\n",
748 (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
750 set_reg(priv, REG_REG, &config->c_reg);
751 set_reg(priv, REG_TIMING, &config->c_timing);
752 set_reg(priv, REG_MAP, &config->c_map);
754 /* skip CTRL init, SDRAM init is done by PHY PUBL */
755 clrsetbits_le32(&priv->ctl->init0,
756 DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
757 DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
759 set_reg(priv, REG_PERF, &config->c_perf);
761 if (INTERACTIVE(STEP_CTL_INIT))
764 /* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
765 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
766 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
767 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
769 /* 3. start PHY init by accessing relevant PUBL registers
770 * (DXGCR, DCR, PTR*, MR*, DTPR*)
772 set_reg(priv, REGPHY_REG, &config->p_reg);
773 set_reg(priv, REGPHY_TIMING, &config->p_timing);
774 if (config->p_cal_present)
775 set_reg(priv, REGPHY_CAL, &config->p_cal);
777 if (INTERACTIVE(STEP_PHY_INIT))
780 /* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
781 * Perform DDR PHY DRAM initialization and Gate Training Evaluation
783 ddrphy_idone_wait(priv->phy);
785 /* 5. Indicate to PUBL that controller performs SDRAM initialization
786 * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
787 * DRAM init is done by PHY, init0.skip_dram.init = 1
789 pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
790 DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
792 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
793 pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
795 stm32mp1_ddrphy_init(priv->phy, pir);
797 /* 6. SET DFIMISC.dfi_init_complete_en to 1 */
798 /* Enable quasi-dynamic register programming*/
799 start_sw_done(priv->ctl);
800 setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
801 wait_sw_done_ack(priv->ctl);
803 /* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
804 * by monitoring STAT.operating_mode signal
806 /* wait uMCTL2 ready */
808 wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
810 if (config->p_cal_present) {
811 debug("DDR DQS training skipped.\n");
813 debug("DDR DQS training : ");
814 /* 8. Disable Auto refresh and power down by setting
815 * - RFSHCTL3.dis_au_refresh = 1
816 * - PWRCTL.powerdown_en = 0
817 * - DFIMISC.dfiinit_complete_en = 0
819 stm32mp1_refresh_disable(priv->ctl);
821 /* 9. Program PUBL PGCR to enable refresh during training and rank to train
822 * not done => keep the programed value in PGCR
825 /* 10. configure PUBL PIR register to specify which training step to run */
826 /* warning : RVTRN is not supported by this PUBL */
827 stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
829 /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
830 ddrphy_idone_wait(priv->phy);
832 /* 12. set back registers in step 8 to the orginal values if desidered */
833 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
834 config->c_reg.pwrctl);
835 } /* if (config->p_cal_present) */
837 /* enable uMCTL2 AXI port 0 and 1 */
838 setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
839 setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
841 if (INTERACTIVE(STEP_DDR_READY))