drivers/ram/stm32_sdram.c

   1 /*
   2  * (C) Copyright 2017
   3  * Vikas Manocha, <vikas.manocha@st.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <ram.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/fmc.h>
  14 #include <asm/arch/stm32.h>
  15
  16 static inline u32 _ns2clk(u32 ns, u32 freq)
  17 {
  18         u32 tmp = freq/1000000;
  19         return (tmp * ns) / 1000;
  20 }
  21
  22 #define NS2CLK(ns) (_ns2clk(ns, freq))
  23
  24 /*
  25  * Following are timings for IS42S16400J, from corresponding datasheet
  26  */
  27 #define SDRAM_CAS       3       /* 3 cycles */
  28 #define SDRAM_NB        1       /* Number of banks */
  29 #define SDRAM_MWID      1       /* 16 bit memory */
  30
  31 #define SDRAM_NR        0x1     /* 12-bit row */
  32 #define SDRAM_NC        0x0     /* 8-bit col */
  33 #define SDRAM_RBURST    0x1     /* Single read requests always as bursts */
  34 #define SDRAM_RPIPE     0x0     /* No HCLK clock cycle delay */
  35
  36 #define SDRAM_TRRD      NS2CLK(12)
  37 #define SDRAM_TRCD      NS2CLK(18)
  38 #define SDRAM_TRP       NS2CLK(18)
  39 #define SDRAM_TRAS      NS2CLK(42)
  40 #define SDRAM_TRC       NS2CLK(60)
  41 #define SDRAM_TRFC      NS2CLK(60)
  42 #define SDRAM_TCDL      (1 - 1)
  43 #define SDRAM_TRDL      NS2CLK(12)
  44 #define SDRAM_TBDL      (1 - 1)
  45 #define SDRAM_TREF      (NS2CLK(64000000 / 8192) - 20)
  46 #define SDRAM_TCCD      (1 - 1)
  47
  48 #define SDRAM_TXSR      SDRAM_TRFC      /* Row cycle time after precharge */
  49 #define SDRAM_TMRD      1               /* Page 10, Mode Register Set */
  50
  51
  52 /* Last data in to row precharge, need also comply ineq on page 1648 */
  53 #define SDRAM_TWR       max(\
  54                 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
  55                 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
  56                 )
  57
  58
  59 #define SDRAM_MODE_BL_SHIFT     0
  60 #define SDRAM_MODE_CAS_SHIFT    4
  61 #define SDRAM_MODE_BL           0
  62 #define SDRAM_MODE_CAS          SDRAM_CAS
  63
  64 int stm32_sdram_init(void)
  65 {
  66         u32 freq;
  67
  68         /*
  69          * Get frequency for NS2CLK calculation.
  70          */
  71         freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
  72
  73         writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
  74                         | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
  75                         | SDRAM_NB << FMC_SDCR_NB_SHIFT
  76                         | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
  77                         | SDRAM_NR << FMC_SDCR_NR_SHIFT
  78                         | SDRAM_NC << FMC_SDCR_NC_SHIFT
  79                         | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
  80                         | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
  81                         &STM32_SDRAM_FMC->sdcr1);
  82
  83         writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
  84                         | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
  85                         | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
  86                         | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
  87                         | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
  88                         | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
  89                         | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
  90                         &STM32_SDRAM_FMC->sdtr1);
  91
  92         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
  93                &STM32_SDRAM_FMC->sdcmr);
  94         udelay(200);    /* 200 us delay, page 10, "Power-Up" */
  95         FMC_BUSY_WAIT();
  96
  97         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
  98                &STM32_SDRAM_FMC->sdcmr);
  99         udelay(100);
 100         FMC_BUSY_WAIT();
 101
 102         writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
 103                 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
 104         udelay(100);
 105         FMC_BUSY_WAIT();
 106
 107         writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 108                | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
 109                << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 110                &STM32_SDRAM_FMC->sdcmr);
 111         udelay(100);
 112         FMC_BUSY_WAIT();
 113
 114         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
 115                &STM32_SDRAM_FMC->sdcmr);
 116         FMC_BUSY_WAIT();
 117
 118         /* Refresh timer */
 119         writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
 120
 121         return 0;
 122 }
 123
 124 static int stm32_fmc_probe(struct udevice *dev)
 125 {
 126 #ifdef CONFIG_CLK
 127         int ret;
 128         struct clk clk;
 129         ret = clk_get_by_index(dev, 0, &clk);
 130         if (ret < 0)
 131                 return ret;
 132
 133         ret = clk_enable(&clk);
 134
 135         if (ret) {
 136                 dev_err(dev, "failed to enable clock\n");
 137                 return ret;
 138         }
 139 #endif
 140         stm32_sdram_init();
 141         return 0;
 142 }
 143
 144 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 145 {
 146         info->size = CONFIG_SYS_RAM_SIZE;
 147         return 0;
 148 }
 149
 150 static struct ram_ops stm32_fmc_ops = {
 151         .get_info = stm32_fmc_get_info,
 152 };
 153
 154 static const struct udevice_id stm32_fmc_ids[] = {
 155         { .compatible = "st,stm32-fmc" },
 156         { }
 157 };
 158
 159 U_BOOT_DRIVER(stm32_fmc) = {
 160         .name = "stm32_fmc",
 161         .id = UCLASS_RAM,
 162         .of_match = stm32_fmc_ids,
 163         .ops = &stm32_fmc_ops,
 164         .probe = stm32_fmc_probe,
 165 };