3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fmc.h>
11 #include <asm/arch/stm32.h>
13 static inline u32 _ns2clk(u32 ns, u32 freq)
15 u32 tmp = freq/1000000;
16 return (tmp * ns) / 1000;
19 #define NS2CLK(ns) (_ns2clk(ns, freq))
22 * Following are timings for IS42S16400J, from corresponding datasheet
24 #define SDRAM_CAS 3 /* 3 cycles */
25 #define SDRAM_NB 1 /* Number of banks */
26 #define SDRAM_MWID 1 /* 16 bit memory */
28 #define SDRAM_NR 0x1 /* 12-bit row */
29 #define SDRAM_NC 0x0 /* 8-bit col */
30 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
31 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
33 #define SDRAM_TRRD NS2CLK(12)
34 #define SDRAM_TRCD NS2CLK(18)
35 #define SDRAM_TRP NS2CLK(18)
36 #define SDRAM_TRAS NS2CLK(42)
37 #define SDRAM_TRC NS2CLK(60)
38 #define SDRAM_TRFC NS2CLK(60)
39 #define SDRAM_TCDL (1 - 1)
40 #define SDRAM_TRDL NS2CLK(12)
41 #define SDRAM_TBDL (1 - 1)
42 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
43 #define SDRAM_TCCD (1 - 1)
45 #define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
46 #define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
49 /* Last data in to row precharge, need also comply ineq on page 1648 */
50 #define SDRAM_TWR max(\
51 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
52 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
56 #define SDRAM_MODE_BL_SHIFT 0
57 #define SDRAM_MODE_CAS_SHIFT 4
58 #define SDRAM_MODE_BL 0
59 #define SDRAM_MODE_CAS SDRAM_CAS
61 int stm32_sdram_init(void)
66 * Get frequency for NS2CLK calculation.
68 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
70 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
71 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT
72 | SDRAM_NB << FMC_SDCR_NB_SHIFT
73 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT
74 | SDRAM_NR << FMC_SDCR_NR_SHIFT
75 | SDRAM_NC << FMC_SDCR_NC_SHIFT
76 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
77 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
78 &STM32_SDRAM_FMC->sdcr1);
80 writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
81 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT
82 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT
83 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT
84 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
85 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
86 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
87 &STM32_SDRAM_FMC->sdtr1);
89 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
90 &STM32_SDRAM_FMC->sdcmr);
91 udelay(200); /* 200 us delay, page 10, "Power-Up" */
94 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
95 &STM32_SDRAM_FMC->sdcmr);
99 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
100 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
104 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
105 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
106 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
107 &STM32_SDRAM_FMC->sdcmr);
111 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
112 &STM32_SDRAM_FMC->sdcmr);
116 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);