3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/fmc.h>
14 #include <asm/arch/stm32.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 struct stm32_sdram_control {
28 struct stm32_sdram_timing {
36 struct stm32_sdram_params {
38 struct stm32_sdram_control sdram_control;
39 struct stm32_sdram_timing sdram_timing;
41 static inline u32 _ns2clk(u32 ns, u32 freq)
43 u32 tmp = freq/1000000;
44 return (tmp * ns) / 1000;
47 #define NS2CLK(ns) (_ns2clk(ns, freq))
49 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
51 #define SDRAM_MODE_BL_SHIFT 0
52 #define SDRAM_MODE_CAS_SHIFT 4
53 #define SDRAM_MODE_BL 0
54 #define SDRAM_MODE_CAS 3
58 int stm32_sdram_init(struct udevice *dev)
62 struct stm32_sdram_params *params = dev_get_platdata(dev);
65 * Get frequency for NS2CLK calculation.
67 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
68 debug("%s, sdram freq = %d\n", __func__, freq);
70 /* Last data in to row precharge, need also comply ineq on page 1648 */
72 max(SDRAM_TRDL, params->sdram_timing.tras
73 - params->sdram_timing.trcd),
74 params->sdram_timing.trc - params->sdram_timing.trcd
75 - params->sdram_timing.trp
78 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
79 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
80 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
81 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
82 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
83 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
84 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
85 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
86 &STM32_SDRAM_FMC->sdcr1);
88 writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT
89 | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT
90 | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT
91 | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT
92 | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT
93 | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT
94 | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT,
95 &STM32_SDRAM_FMC->sdtr1);
97 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
98 &STM32_SDRAM_FMC->sdcmr);
99 udelay(200); /* 200 us delay, page 10, "Power-Up" */
102 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
103 &STM32_SDRAM_FMC->sdcmr);
107 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
108 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
112 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
113 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
114 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
115 &STM32_SDRAM_FMC->sdcmr);
119 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
120 &STM32_SDRAM_FMC->sdcmr);
124 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
129 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
132 int node = dev->of_offset;
133 const void *blob = gd->fdt_blob;
134 struct stm32_sdram_params *params = dev_get_platdata(dev);
136 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
137 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
139 fdt_for_each_subnode(node, blob, node) {
140 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
141 (u8 *)¶ms->sdram_control,
142 sizeof(params->sdram_control));
146 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
147 (u8 *)¶ms->sdram_timing,
148 sizeof(params->sdram_timing));
156 static int stm32_fmc_probe(struct udevice *dev)
162 ret = clk_get_by_index(dev, 0, &clk);
166 ret = clk_enable(&clk);
169 dev_err(dev, "failed to enable clock\n");
173 ret = stm32_sdram_init(dev);
180 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
185 static struct ram_ops stm32_fmc_ops = {
186 .get_info = stm32_fmc_get_info,
189 static const struct udevice_id stm32_fmc_ids[] = {
190 { .compatible = "st,stm32-fmc" },
194 U_BOOT_DRIVER(stm32_fmc) = {
197 .of_match = stm32_fmc_ids,
198 .ops = &stm32_fmc_ops,
199 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
200 .probe = stm32_fmc_probe,
201 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),