drivers/ram/stm32_sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <ram.h>
  11 #include <asm/io.h>
  12
  13 #define MEM_MODE_MASK   GENMASK(2, 0)
  14 #define SWP_FMC_OFFSET 10
  15 #define SWP_FMC_MASK    GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
  16 #define NOT_FOUND       0xff
  17
  18 struct stm32_fmc_regs {
  19         /* 0x0 */
  20         u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  21         u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  22         u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  23         u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  24         u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  25         u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  26         u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  27         u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  28         u32 reserved1[24];
  29
  30         /* 0x80 */
  31         u32 pcr;        /* NAND Flash control register */
  32         u32 sr;         /* FIFO status and interrupt register */
  33         u32 pmem;       /* Common memory space timing register */
  34         u32 patt;       /* Attribute memory space timing registers  */
  35         u32 reserved2[1];
  36         u32 eccr;       /* ECC result registers */
  37         u32 reserved3[27];
  38
  39         /* 0x104 */
  40         u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  41         u32 reserved4[1];
  42         u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  43         u32 reserved5[1];
  44         u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  45         u32 reserved6[1];
  46         u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  47         u32 reserved7[8];
  48
  49         /* 0x140 */
  50         u32 sdcr1;      /* SDRAM Control register 1 */
  51         u32 sdcr2;      /* SDRAM Control register 2 */
  52         u32 sdtr1;      /* SDRAM Timing register 1 */
  53         u32 sdtr2;      /* SDRAM Timing register 2 */
  54         u32 sdcmr;      /* SDRAM Mode register */
  55         u32 sdrtr;      /* SDRAM Refresh timing register */
  56         u32 sdsr;       /* SDRAM Status register */
  57 };
  58
  59 /*
  60  * NOR/PSRAM Control register BCR1
  61  * FMC controller Enable, only availabe for H7
  62  */
  63 #define FMC_BCR1_FMCEN          BIT(31)
  64
  65 /* Control register SDCR */
  66 #define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  67 #define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  68 #define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  69 #define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  70 #define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  71 #define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  72 #define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  73 #define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  74 #define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  75
  76 /* Timings register SDTR */
  77 #define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  78 #define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  79 #define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  80 #define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  81 #define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  82 #define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  83 #define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  84
  85 #define FMC_SDCMR_NRFS_SHIFT    5
  86
  87 #define FMC_SDCMR_MODE_NORMAL           0
  88 #define FMC_SDCMR_MODE_START_CLOCK      1
  89 #define FMC_SDCMR_MODE_PRECHARGE        2
  90 #define FMC_SDCMR_MODE_AUTOREFRESH      3
  91 #define FMC_SDCMR_MODE_WRITE_MODE       4
  92 #define FMC_SDCMR_MODE_SELFREFRESH      5
  93 #define FMC_SDCMR_MODE_POWERDOWN        6
  94
  95 #define FMC_SDCMR_BANK_1                BIT(4)
  96 #define FMC_SDCMR_BANK_2                BIT(3)
  97
  98 #define FMC_SDCMR_MODE_REGISTER_SHIFT   9
  99
 100 #define FMC_SDSR_BUSY                   BIT(5)
 101
 102 #define FMC_BUSY_WAIT(regs)     do { \
 103                 __asm__ __volatile__ ("dsb" : : : "memory"); \
 104                 while (regs->sdsr & FMC_SDSR_BUSY) \
 105                         ; \
 106         } while (0)
 107
 108 struct stm32_sdram_control {
 109         u8 no_columns;
 110         u8 no_rows;
 111         u8 memory_width;
 112         u8 no_banks;
 113         u8 cas_latency;
 114         u8 sdclk;
 115         u8 rd_burst;
 116         u8 rd_pipe_delay;
 117 };
 118
 119 struct stm32_sdram_timing {
 120         u8 tmrd;
 121         u8 txsr;
 122         u8 tras;
 123         u8 trc;
 124         u8 trp;
 125         u8 twr;
 126         u8 trcd;
 127 };
 128 enum stm32_fmc_bank {
 129         SDRAM_BANK1,
 130         SDRAM_BANK2,
 131         MAX_SDRAM_BANK,
 132 };
 133
 134 enum stm32_fmc_family {
 135         STM32F7_FMC,
 136         STM32H7_FMC,
 137 };
 138
 139 struct bank_params {
 140         struct stm32_sdram_control *sdram_control;
 141         struct stm32_sdram_timing *sdram_timing;
 142         u32 sdram_ref_count;
 143         enum stm32_fmc_bank target_bank;
 144 };
 145
 146 struct stm32_sdram_params {
 147         struct stm32_fmc_regs *base;
 148         u8 no_sdram_banks;
 149         struct bank_params bank_params[MAX_SDRAM_BANK];
 150         enum stm32_fmc_family family;
 151 };
 152
 153 #define SDRAM_MODE_BL_SHIFT     0
 154 #define SDRAM_MODE_CAS_SHIFT    4
 155 #define SDRAM_MODE_BL           0
 156
 157 int stm32_sdram_init(struct udevice *dev)
 158 {
 159         struct stm32_sdram_params *params = dev_get_platdata(dev);
 160         struct stm32_sdram_control *control;
 161         struct stm32_sdram_timing *timing;
 162         struct stm32_fmc_regs *regs = params->base;
 163         enum stm32_fmc_bank target_bank;
 164         u32 ctb; /* SDCMR register: Command Target Bank */
 165         u32 ref_count;
 166         u8 i;
 167
 168         /* disable the FMC controller */
 169         if (params->family == STM32H7_FMC)
 170                 clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 171
 172         for (i = 0; i < params->no_sdram_banks; i++) {
 173                 control = params->bank_params[i].sdram_control;
 174                 timing = params->bank_params[i].sdram_timing;
 175                 target_bank = params->bank_params[i].target_bank;
 176                 ref_count = params->bank_params[i].sdram_ref_count;
 177
 178                 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 179                         | control->cas_latency << FMC_SDCR_CAS_SHIFT
 180                         | control->no_banks << FMC_SDCR_NB_SHIFT
 181                         | control->memory_width << FMC_SDCR_MWID_SHIFT
 182                         | control->no_rows << FMC_SDCR_NR_SHIFT
 183                         | control->no_columns << FMC_SDCR_NC_SHIFT
 184                         | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 185                         | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 186                         &regs->sdcr1);
 187
 188                 if (target_bank == SDRAM_BANK2)
 189                         writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
 190                                 | control->no_banks << FMC_SDCR_NB_SHIFT
 191                                 | control->memory_width << FMC_SDCR_MWID_SHIFT
 192                                 | control->no_rows << FMC_SDCR_NR_SHIFT
 193                                 | control->no_columns << FMC_SDCR_NC_SHIFT,
 194                                 &regs->sdcr2);
 195
 196                 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 197                         | timing->trp << FMC_SDTR_TRP_SHIFT
 198                         | timing->twr << FMC_SDTR_TWR_SHIFT
 199                         | timing->trc << FMC_SDTR_TRC_SHIFT
 200                         | timing->tras << FMC_SDTR_TRAS_SHIFT
 201                         | timing->txsr << FMC_SDTR_TXSR_SHIFT
 202                         | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 203                         &regs->sdtr1);
 204
 205                 if (target_bank == SDRAM_BANK2)
 206                         writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 207                                 | timing->trp << FMC_SDTR_TRP_SHIFT
 208                                 | timing->twr << FMC_SDTR_TWR_SHIFT
 209                                 | timing->trc << FMC_SDTR_TRC_SHIFT
 210                                 | timing->tras << FMC_SDTR_TRAS_SHIFT
 211                                 | timing->txsr << FMC_SDTR_TXSR_SHIFT
 212                                 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 213                                 &regs->sdtr2);
 214
 215                 if (target_bank == SDRAM_BANK1)
 216                         ctb = FMC_SDCMR_BANK_1;
 217                 else
 218                         ctb = FMC_SDCMR_BANK_2;
 219
 220                 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
 221                 udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 222                 FMC_BUSY_WAIT(regs);
 223
 224                 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
 225                 udelay(100);
 226                 FMC_BUSY_WAIT(regs);
 227
 228                 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
 229                        &regs->sdcmr);
 230                 udelay(100);
 231                 FMC_BUSY_WAIT(regs);
 232
 233                 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 234                        | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 235                        << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 236                        &regs->sdcmr);
 237                 udelay(100);
 238                 FMC_BUSY_WAIT(regs);
 239
 240                 writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
 241                 FMC_BUSY_WAIT(regs);
 242
 243                 /* Refresh timer */
 244                 writel(ref_count << 1, &regs->sdrtr);
 245         }
 246
 247         /* enable the FMC controller */
 248         if (params->family == STM32H7_FMC)
 249                 setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 250
 251         return 0;
 252 }
 253
 254 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 255 {
 256         struct stm32_sdram_params *params = dev_get_platdata(dev);
 257         struct bank_params *bank_params;
 258         struct ofnode_phandle_args args;
 259         u32 *syscfg_base;
 260         u32 mem_remap;
 261         u32 swp_fmc;
 262         ofnode bank_node;
 263         char *bank_name;
 264         u8 bank = 0;
 265         int ret;
 266
 267         ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 268                                                  &args);
 269         if (ret) {
 270                 dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
 271         } else {
 272                 syscfg_base = (u32 *)ofnode_get_addr(args.node);
 273
 274                 mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
 275                 if (mem_remap != NOT_FOUND) {
 276                         /* set memory mapping selection */
 277                         clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
 278                 } else {
 279                         dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
 280                 }
 281
 282                 swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
 283                 if (swp_fmc != NOT_FOUND) {
 284                         /* set fmc swapping selection */
 285                         clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
 286                 } else {
 287                         dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
 288                 }
 289
 290                 dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
 291         }
 292
 293         dev_for_each_subnode(bank_node, dev) {
 294                 /* extract the bank index from DT */
 295                 bank_name = (char *)ofnode_get_name(bank_node);
 296                 strsep(&bank_name, "@");
 297                 if (!bank_name) {
 298                         pr_err("missing sdram bank index");
 299                         return -EINVAL;
 300                 }
 301
 302                 bank_params = &params->bank_params[bank];
 303                 strict_strtoul(bank_name, 10,
 304                                (long unsigned int *)&bank_params->target_bank);
 305
 306                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 307                         pr_err("Found bank %d , but only bank 0 and 1 are supported",
 308                               bank_params->target_bank);
 309                         return -EINVAL;
 310                 }
 311
 312                 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
 313
 314                 params->bank_params[bank].sdram_control =
 315                         (struct stm32_sdram_control *)
 316                          ofnode_read_u8_array_ptr(bank_node,
 317                                                   "st,sdram-control",
 318                                                   sizeof(struct stm32_sdram_control));
 319
 320                 if (!params->bank_params[bank].sdram_control) {
 321                         pr_err("st,sdram-control not found for %s",
 322                               ofnode_get_name(bank_node));
 323                         return -EINVAL;
 324                 }
 325
 326
 327                 params->bank_params[bank].sdram_timing =
 328                         (struct stm32_sdram_timing *)
 329                          ofnode_read_u8_array_ptr(bank_node,
 330                                                   "st,sdram-timing",
 331                                                   sizeof(struct stm32_sdram_timing));
 332
 333                 if (!params->bank_params[bank].sdram_timing) {
 334                         pr_err("st,sdram-timing not found for %s",
 335                               ofnode_get_name(bank_node));
 336                         return -EINVAL;
 337                 }
 338
 339
 340                 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 341                                                 "st,sdram-refcount", 8196);
 342                 bank++;
 343         }
 344
 345         params->no_sdram_banks = bank;
 346         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 347
 348         return 0;
 349 }
 350
 351 static int stm32_fmc_probe(struct udevice *dev)
 352 {
 353         struct stm32_sdram_params *params = dev_get_platdata(dev);
 354         int ret;
 355         fdt_addr_t addr;
 356
 357         addr = dev_read_addr(dev);
 358         if (addr == FDT_ADDR_T_NONE)
 359                 return -EINVAL;
 360
 361         params->base = (struct stm32_fmc_regs *)addr;
 362         params->family = dev_get_driver_data(dev);
 363
 364 #ifdef CONFIG_CLK
 365         struct clk clk;
 366
 367         ret = clk_get_by_index(dev, 0, &clk);
 368         if (ret < 0)
 369                 return ret;
 370
 371         ret = clk_enable(&clk);
 372
 373         if (ret) {
 374                 dev_err(dev, "failed to enable clock\n");
 375                 return ret;
 376         }
 377 #endif
 378         ret = stm32_sdram_init(dev);
 379         if (ret)
 380                 return ret;
 381
 382         return 0;
 383 }
 384
 385 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 386 {
 387         return 0;
 388 }
 389
 390 static struct ram_ops stm32_fmc_ops = {
 391         .get_info = stm32_fmc_get_info,
 392 };
 393
 394 static const struct udevice_id stm32_fmc_ids[] = {
 395         { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
 396         { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
 397         { }
 398 };
 399
 400 U_BOOT_DRIVER(stm32_fmc) = {
 401         .name = "stm32_fmc",
 402         .id = UCLASS_RAM,
 403         .of_match = stm32_fmc_ids,
 404         .ops = &stm32_fmc_ops,
 405         .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
 406         .probe = stm32_fmc_probe,
 407         .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
 408 };