drivers/ram/stm32_sdram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_RAM
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <ram.h>
  15 #include <asm/io.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/bitops.h>
  18 #include <linux/delay.h>
  19
  20 #define MEM_MODE_MASK   GENMASK(2, 0)
  21 #define SWP_FMC_OFFSET 10
  22 #define SWP_FMC_MASK    GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
  23 #define NOT_FOUND       0xff
  24
  25 struct stm32_fmc_regs {
  26         /* 0x0 */
  27         u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  28         u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  29         u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  30         u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  31         u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  32         u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  33         u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  34         u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  35         u32 reserved1[24];
  36
  37         /* 0x80 */
  38         u32 pcr;        /* NAND Flash control register */
  39         u32 sr;         /* FIFO status and interrupt register */
  40         u32 pmem;       /* Common memory space timing register */
  41         u32 patt;       /* Attribute memory space timing registers  */
  42         u32 reserved2[1];
  43         u32 eccr;       /* ECC result registers */
  44         u32 reserved3[27];
  45
  46         /* 0x104 */
  47         u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  48         u32 reserved4[1];
  49         u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  50         u32 reserved5[1];
  51         u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  52         u32 reserved6[1];
  53         u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  54         u32 reserved7[8];
  55
  56         /* 0x140 */
  57         u32 sdcr1;      /* SDRAM Control register 1 */
  58         u32 sdcr2;      /* SDRAM Control register 2 */
  59         u32 sdtr1;      /* SDRAM Timing register 1 */
  60         u32 sdtr2;      /* SDRAM Timing register 2 */
  61         u32 sdcmr;      /* SDRAM Mode register */
  62         u32 sdrtr;      /* SDRAM Refresh timing register */
  63         u32 sdsr;       /* SDRAM Status register */
  64 };
  65
  66 /*
  67  * NOR/PSRAM Control register BCR1
  68  * FMC controller Enable, only availabe for H7
  69  */
  70 #define FMC_BCR1_FMCEN          BIT(31)
  71
  72 /* Control register SDCR */
  73 #define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  74 #define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  75 #define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  76 #define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  77 #define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  78 #define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  79 #define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  80 #define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  81 #define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  82
  83 /* Timings register SDTR */
  84 #define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  85 #define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  86 #define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  87 #define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  88 #define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  89 #define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  90 #define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  91
  92 #define FMC_SDCMR_NRFS_SHIFT    5
  93
  94 #define FMC_SDCMR_MODE_NORMAL           0
  95 #define FMC_SDCMR_MODE_START_CLOCK      1
  96 #define FMC_SDCMR_MODE_PRECHARGE        2
  97 #define FMC_SDCMR_MODE_AUTOREFRESH      3
  98 #define FMC_SDCMR_MODE_WRITE_MODE       4
  99 #define FMC_SDCMR_MODE_SELFREFRESH      5
 100 #define FMC_SDCMR_MODE_POWERDOWN        6
 101
 102 #define FMC_SDCMR_BANK_1                BIT(4)
 103 #define FMC_SDCMR_BANK_2                BIT(3)
 104
 105 #define FMC_SDCMR_MODE_REGISTER_SHIFT   9
 106
 107 #define FMC_SDSR_BUSY                   BIT(5)
 108
 109 #define FMC_BUSY_WAIT(regs)     do { \
 110                 __asm__ __volatile__ ("dsb" : : : "memory"); \
 111                 while (regs->sdsr & FMC_SDSR_BUSY) \
 112                         ; \
 113         } while (0)
 114
 115 struct stm32_sdram_control {
 116         u8 no_columns;
 117         u8 no_rows;
 118         u8 memory_width;
 119         u8 no_banks;
 120         u8 cas_latency;
 121         u8 sdclk;
 122         u8 rd_burst;
 123         u8 rd_pipe_delay;
 124 };
 125
 126 struct stm32_sdram_timing {
 127         u8 tmrd;
 128         u8 txsr;
 129         u8 tras;
 130         u8 trc;
 131         u8 trp;
 132         u8 twr;
 133         u8 trcd;
 134 };
 135 enum stm32_fmc_bank {
 136         SDRAM_BANK1,
 137         SDRAM_BANK2,
 138         MAX_SDRAM_BANK,
 139 };
 140
 141 enum stm32_fmc_family {
 142         STM32F7_FMC,
 143         STM32H7_FMC,
 144 };
 145
 146 struct bank_params {
 147         struct stm32_sdram_control *sdram_control;
 148         struct stm32_sdram_timing *sdram_timing;
 149         u32 sdram_ref_count;
 150         enum stm32_fmc_bank target_bank;
 151 };
 152
 153 struct stm32_sdram_params {
 154         struct stm32_fmc_regs *base;
 155         u8 no_sdram_banks;
 156         struct bank_params bank_params[MAX_SDRAM_BANK];
 157         enum stm32_fmc_family family;
 158 };
 159
 160 #define SDRAM_MODE_BL_SHIFT     0
 161 #define SDRAM_MODE_CAS_SHIFT    4
 162 #define SDRAM_MODE_BL           0
 163
 164 int stm32_sdram_init(struct udevice *dev)
 165 {
 166         struct stm32_sdram_params *params = dev_get_plat(dev);
 167         struct stm32_sdram_control *control;
 168         struct stm32_sdram_timing *timing;
 169         struct stm32_fmc_regs *regs = params->base;
 170         enum stm32_fmc_bank target_bank;
 171         u32 ctb; /* SDCMR register: Command Target Bank */
 172         u32 ref_count;
 173         u8 i;
 174
 175         /* disable the FMC controller */
 176         if (params->family == STM32H7_FMC)
 177                 clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 178
 179         for (i = 0; i < params->no_sdram_banks; i++) {
 180                 control = params->bank_params[i].sdram_control;
 181                 timing = params->bank_params[i].sdram_timing;
 182                 target_bank = params->bank_params[i].target_bank;
 183                 ref_count = params->bank_params[i].sdram_ref_count;
 184
 185                 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 186                         | control->cas_latency << FMC_SDCR_CAS_SHIFT
 187                         | control->no_banks << FMC_SDCR_NB_SHIFT
 188                         | control->memory_width << FMC_SDCR_MWID_SHIFT
 189                         | control->no_rows << FMC_SDCR_NR_SHIFT
 190                         | control->no_columns << FMC_SDCR_NC_SHIFT
 191                         | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 192                         | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 193                         &regs->sdcr1);
 194
 195                 if (target_bank == SDRAM_BANK2)
 196                         writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
 197                                 | control->no_banks << FMC_SDCR_NB_SHIFT
 198                                 | control->memory_width << FMC_SDCR_MWID_SHIFT
 199                                 | control->no_rows << FMC_SDCR_NR_SHIFT
 200                                 | control->no_columns << FMC_SDCR_NC_SHIFT,
 201                                 &regs->sdcr2);
 202
 203                 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 204                         | timing->trp << FMC_SDTR_TRP_SHIFT
 205                         | timing->twr << FMC_SDTR_TWR_SHIFT
 206                         | timing->trc << FMC_SDTR_TRC_SHIFT
 207                         | timing->tras << FMC_SDTR_TRAS_SHIFT
 208                         | timing->txsr << FMC_SDTR_TXSR_SHIFT
 209                         | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 210                         &regs->sdtr1);
 211
 212                 if (target_bank == SDRAM_BANK2)
 213                         writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 214                                 | timing->trp << FMC_SDTR_TRP_SHIFT
 215                                 | timing->twr << FMC_SDTR_TWR_SHIFT
 216                                 | timing->trc << FMC_SDTR_TRC_SHIFT
 217                                 | timing->tras << FMC_SDTR_TRAS_SHIFT
 218                                 | timing->txsr << FMC_SDTR_TXSR_SHIFT
 219                                 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 220                                 &regs->sdtr2);
 221
 222                 if (target_bank == SDRAM_BANK1)
 223                         ctb = FMC_SDCMR_BANK_1;
 224                 else
 225                         ctb = FMC_SDCMR_BANK_2;
 226
 227                 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
 228                 udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 229                 FMC_BUSY_WAIT(regs);
 230
 231                 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
 232                 udelay(100);
 233                 FMC_BUSY_WAIT(regs);
 234
 235                 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
 236                        &regs->sdcmr);
 237                 udelay(100);
 238                 FMC_BUSY_WAIT(regs);
 239
 240                 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 241                        | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 242                        << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 243                        &regs->sdcmr);
 244                 udelay(100);
 245                 FMC_BUSY_WAIT(regs);
 246
 247                 writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
 248                 FMC_BUSY_WAIT(regs);
 249
 250                 /* Refresh timer */
 251                 writel(ref_count << 1, &regs->sdrtr);
 252         }
 253
 254         /* enable the FMC controller */
 255         if (params->family == STM32H7_FMC)
 256                 setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 257
 258         return 0;
 259 }
 260
 261 static int stm32_fmc_of_to_plat(struct udevice *dev)
 262 {
 263         struct stm32_sdram_params *params = dev_get_plat(dev);
 264         struct bank_params *bank_params;
 265         struct ofnode_phandle_args args;
 266         u32 *syscfg_base;
 267         u32 mem_remap;
 268         u32 swp_fmc;
 269         ofnode bank_node;
 270         char *bank_name;
 271         char _bank_name[128] = {0};
 272         u8 bank = 0;
 273         int ret;
 274
 275         ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 276                                                  &args);
 277         if (ret) {
 278                 dev_dbg(dev, "can't find syscon device (%d)\n", ret);
 279         } else {
 280                 syscfg_base = (u32 *)ofnode_get_addr(args.node);
 281
 282                 mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
 283                 if (mem_remap != NOT_FOUND) {
 284                         /* set memory mapping selection */
 285                         clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
 286                 } else {
 287                         dev_dbg(dev, "cannot find st,mem_remap property\n");
 288                 }
 289
 290                 swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
 291                 if (swp_fmc != NOT_FOUND) {
 292                         /* set fmc swapping selection */
 293                         clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
 294                 } else {
 295                         dev_dbg(dev, "cannot find st,swp_fmc property\n");
 296                 }
 297
 298                 dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
 299         }
 300
 301         dev_for_each_subnode(bank_node, dev) {
 302                 /* extract the bank index from DT */
 303                 bank_name = (char *)ofnode_get_name(bank_node);
 304                 strlcpy(_bank_name, bank_name, sizeof(_bank_name));
 305                 bank_name = (char *)_bank_name;
 306                 strsep(&bank_name, "@");
 307                 if (!bank_name) {
 308                         pr_err("missing sdram bank index");
 309                         return -EINVAL;
 310                 }
 311
 312                 bank_params = &params->bank_params[bank];
 313                 strict_strtoul(bank_name, 10,
 314                                (long unsigned int *)&bank_params->target_bank);
 315
 316                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 317                         pr_err("Found bank %d , but only bank 0 and 1 are supported",
 318                               bank_params->target_bank);
 319                         return -EINVAL;
 320                 }
 321
 322                 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
 323
 324                 params->bank_params[bank].sdram_control =
 325                         (struct stm32_sdram_control *)
 326                          ofnode_read_u8_array_ptr(bank_node,
 327                                                   "st,sdram-control",
 328                                                   sizeof(struct stm32_sdram_control));
 329
 330                 if (!params->bank_params[bank].sdram_control) {
 331                         pr_err("st,sdram-control not found for %s",
 332                               ofnode_get_name(bank_node));
 333                         return -EINVAL;
 334                 }
 335
 336
 337                 params->bank_params[bank].sdram_timing =
 338                         (struct stm32_sdram_timing *)
 339                          ofnode_read_u8_array_ptr(bank_node,
 340                                                   "st,sdram-timing",
 341                                                   sizeof(struct stm32_sdram_timing));
 342
 343                 if (!params->bank_params[bank].sdram_timing) {
 344                         pr_err("st,sdram-timing not found for %s",
 345                               ofnode_get_name(bank_node));
 346                         return -EINVAL;
 347                 }
 348
 349
 350                 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 351                                                 "st,sdram-refcount", 8196);
 352                 bank++;
 353         }
 354
 355         params->no_sdram_banks = bank;
 356         dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
 357
 358         return 0;
 359 }
 360
 361 static int stm32_fmc_probe(struct udevice *dev)
 362 {
 363         struct stm32_sdram_params *params = dev_get_plat(dev);
 364         int ret;
 365         fdt_addr_t addr;
 366
 367         addr = dev_read_addr(dev);
 368         if (addr == FDT_ADDR_T_NONE)
 369                 return -EINVAL;
 370
 371         params->base = (struct stm32_fmc_regs *)addr;
 372         params->family = dev_get_driver_data(dev);
 373
 374 #ifdef CONFIG_CLK
 375         struct clk clk;
 376
 377         ret = clk_get_by_index(dev, 0, &clk);
 378         if (ret < 0)
 379                 return ret;
 380
 381         ret = clk_enable(&clk);
 382
 383         if (ret) {
 384                 dev_err(dev, "failed to enable clock\n");
 385                 return ret;
 386         }
 387 #endif
 388         ret = stm32_sdram_init(dev);
 389         if (ret)
 390                 return ret;
 391
 392         return 0;
 393 }
 394
 395 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 396 {
 397         return 0;
 398 }
 399
 400 static struct ram_ops stm32_fmc_ops = {
 401         .get_info = stm32_fmc_get_info,
 402 };
 403
 404 static const struct udevice_id stm32_fmc_ids[] = {
 405         { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
 406         { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
 407         { }
 408 };
 409
 410 U_BOOT_DRIVER(stm32_fmc) = {
 411         .name = "stm32_fmc",
 412         .id = UCLASS_RAM,
 413         .of_match = stm32_fmc_ids,
 414         .ops = &stm32_fmc_ops,
 415         .of_to_plat = stm32_fmc_of_to_plat,
 416         .probe = stm32_fmc_probe,
 417         .plat_auto      = sizeof(struct stm32_sdram_params),
 418 };