3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/stm32.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct stm32_fmc_regs {
18 u32 sdcr1; /* Control register 1 */
19 u32 sdcr2; /* Control register 2 */
20 u32 sdtr1; /* Timing register 1 */
21 u32 sdtr2; /* Timing register 2 */
22 u32 sdcmr; /* Mode register */
23 u32 sdrtr; /* Refresh timing register */
24 u32 sdsr; /* Status register */
30 #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
32 /* Control register SDCR */
33 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
34 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
35 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
36 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
37 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
38 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
39 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
40 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
41 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
43 /* Timings register SDTR */
44 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
45 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
46 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
47 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
48 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
49 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
50 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
52 #define FMC_SDCMR_NRFS_SHIFT 5
54 #define FMC_SDCMR_MODE_NORMAL 0
55 #define FMC_SDCMR_MODE_START_CLOCK 1
56 #define FMC_SDCMR_MODE_PRECHARGE 2
57 #define FMC_SDCMR_MODE_AUTOREFRESH 3
58 #define FMC_SDCMR_MODE_WRITE_MODE 4
59 #define FMC_SDCMR_MODE_SELFREFRESH 5
60 #define FMC_SDCMR_MODE_POWERDOWN 6
62 #define FMC_SDCMR_BANK_1 BIT(4)
63 #define FMC_SDCMR_BANK_2 BIT(3)
65 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
67 #define FMC_SDSR_BUSY BIT(5)
69 #define FMC_BUSY_WAIT() do { \
70 __asm__ __volatile__ ("dsb" : : : "memory"); \
71 while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
75 struct stm32_sdram_control {
86 struct stm32_sdram_timing {
95 struct stm32_sdram_params {
97 struct stm32_sdram_control sdram_control;
98 struct stm32_sdram_timing sdram_timing;
102 #define SDRAM_MODE_BL_SHIFT 0
103 #define SDRAM_MODE_CAS_SHIFT 4
104 #define SDRAM_MODE_BL 0
106 int stm32_sdram_init(struct udevice *dev)
108 struct stm32_sdram_params *params = dev_get_platdata(dev);
110 writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
111 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
112 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
113 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
114 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
115 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
116 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
117 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
118 &STM32_SDRAM_FMC->sdcr1);
120 writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
121 | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
122 | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
123 | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
124 | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
125 | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
126 | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
127 &STM32_SDRAM_FMC->sdtr1);
129 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
130 &STM32_SDRAM_FMC->sdcmr);
131 udelay(200); /* 200 us delay, page 10, "Power-Up" */
134 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
135 &STM32_SDRAM_FMC->sdcmr);
139 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
140 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
144 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
145 | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
146 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
147 &STM32_SDRAM_FMC->sdcmr);
151 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
152 &STM32_SDRAM_FMC->sdcmr);
156 writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);
161 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
164 int node = dev_of_offset(dev);
165 const void *blob = gd->fdt_blob;
166 struct stm32_sdram_params *params = dev_get_platdata(dev);
168 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
169 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
171 fdt_for_each_subnode(node, blob, node) {
172 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
173 (u8 *)¶ms->sdram_control,
174 sizeof(params->sdram_control));
177 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
178 (u8 *)¶ms->sdram_timing,
179 sizeof(params->sdram_timing));
183 params->sdram_ref_count = fdtdec_get_int(blob, node,
184 "st,sdram-refcount", 8196);
190 static int stm32_fmc_probe(struct udevice *dev)
196 ret = clk_get_by_index(dev, 0, &clk);
200 ret = clk_enable(&clk);
203 dev_err(dev, "failed to enable clock\n");
207 ret = stm32_sdram_init(dev);
214 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
219 static struct ram_ops stm32_fmc_ops = {
220 .get_info = stm32_fmc_get_info,
223 static const struct udevice_id stm32_fmc_ids[] = {
224 { .compatible = "st,stm32-fmc" },
228 U_BOOT_DRIVER(stm32_fmc) = {
231 .of_match = stm32_fmc_ids,
232 .ops = &stm32_fmc_ops,
233 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
234 .probe = stm32_fmc_probe,
235 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),