drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  39                                         ((n) << (8 + (ch) * 4)))
  40 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  41                                         ((n) << (9 + (ch) * 4)))
  42 struct chan_info {
  43         struct rk3399_ddr_pctl_regs *pctl;
  44         struct rk3399_ddr_pi_regs *pi;
  45         struct rk3399_ddr_publ_regs *publ;
  46         struct rk3399_msch_regs *msch;
  47 };
  48
  49 struct dram_info {
  50 #if defined(CONFIG_TPL_BUILD) || \
  51         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  52         struct chan_info chan[2];
  53         struct clk ddr_clk;
  54         struct rk3399_cru *cru;
  55         struct rk3399_pmucru *pmucru;
  56         struct rk3399_pmusgrf_regs *pmusgrf;
  57         struct rk3399_ddr_cic_regs *cic;
  58 #endif
  59         struct ram_info info;
  60         struct rk3399_pmugrf_regs *pmugrf;
  61 };
  62
  63 #if defined(CONFIG_TPL_BUILD) || \
  64         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  65
  66 struct rockchip_dmc_plat {
  67 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  68         struct dtd_rockchip_rk3399_dmc dtplat;
  69 #else
  70         struct rk3399_sdram_params sdram_params;
  71 #endif
  72         struct regmap *map;
  73 };
  74
  75 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  76 {
  77         int i;
  78
  79         for (i = 0; i < n / sizeof(u32); i++) {
  80                 writel(*src, dest);
  81                 src++;
  82                 dest++;
  83         }
  84 }
  85
  86 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
  87                             u32 phy)
  88 {
  89         channel &= 0x1;
  90         ctl &= 0x1;
  91         phy &= 0x1;
  92         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
  93                                    CRU_SFTRST_DDR_PHY(channel, phy),
  94                                    &cru->softrst_con[4]);
  95 }
  96
  97 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
  98 {
  99         rkclk_ddr_reset(cru, channel, 1, 1);
 100         udelay(10);
 101
 102         rkclk_ddr_reset(cru, channel, 1, 0);
 103         udelay(10);
 104
 105         rkclk_ddr_reset(cru, channel, 0, 0);
 106         udelay(10);
 107 }
 108
 109 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 110                                u32 freq)
 111 {
 112         u32 *denali_phy = ddr_publ_regs->denali_phy;
 113
 114         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 115         if (freq <= 125) {
 116                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 117                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 118                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 119                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 120                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 121
 122                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 123                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 124                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 125                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 126         } else {
 127                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 128                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 129                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 130                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 131                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 132
 133                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 134                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 135                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 136                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 137         }
 138 }
 139
 140 static void set_memory_map(const struct chan_info *chan, u32 channel,
 141                            const struct rk3399_sdram_params *params)
 142 {
 143         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 144         u32 *denali_ctl = chan->pctl->denali_ctl;
 145         u32 *denali_pi = chan->pi->denali_pi;
 146         u32 cs_map;
 147         u32 reduc;
 148         u32 row;
 149
 150         /* Get row number from ddrconfig setting */
 151         if (sdram_ch->cap_info.ddrconfig < 2 ||
 152             sdram_ch->cap_info.ddrconfig == 4)
 153                 row = 16;
 154         else if (sdram_ch->cap_info.ddrconfig == 3)
 155                 row = 14;
 156         else
 157                 row = 15;
 158
 159         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 160         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 161
 162         /* Set the dram configuration to ctrl */
 163         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 164         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 165                         ((3 - sdram_ch->cap_info.bk) << 16) |
 166                         ((16 - row) << 24));
 167
 168         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 169                         cs_map | (reduc << 16));
 170
 171         /* PI_199 PI_COL_DIFF:RW:0:4 */
 172         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 173
 174         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 175         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 176                         ((3 - sdram_ch->cap_info.bk) << 16) |
 177                         ((16 - row) << 24));
 178         /* PI_41 PI_CS_MAP:RW:24:4 */
 179         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 180         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 181                 writel(0x2EC7FFFF, &denali_pi[34]);
 182 }
 183
 184 static void set_ds_odt(const struct chan_info *chan,
 185                        const struct rk3399_sdram_params *params)
 186 {
 187         u32 *denali_phy = chan->publ->denali_phy;
 188
 189         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 190         u32 tsel_idle_select_p, tsel_rd_select_p;
 191         u32 tsel_idle_select_n, tsel_rd_select_n;
 192         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 193         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 194         u32 reg_value;
 195
 196         if (params->base.dramtype == LPDDR4) {
 197                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 198                 tsel_rd_select_n = PHY_DRV_ODT_240;
 199
 200                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 201                 tsel_idle_select_n = PHY_DRV_ODT_240;
 202
 203                 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 204                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 205
 206                 tsel_wr_select_ca_p = PHY_DRV_ODT_40;
 207                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 208         } else if (params->base.dramtype == LPDDR3) {
 209                 tsel_rd_select_p = PHY_DRV_ODT_240;
 210                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 211
 212                 tsel_idle_select_p = PHY_DRV_ODT_240;
 213                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 214
 215                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 216                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 217
 218                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 219                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 220         } else {
 221                 tsel_rd_select_p = PHY_DRV_ODT_240;
 222                 tsel_rd_select_n = PHY_DRV_ODT_240;
 223
 224                 tsel_idle_select_p = PHY_DRV_ODT_240;
 225                 tsel_idle_select_n = PHY_DRV_ODT_240;
 226
 227                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 228                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 229
 230                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 231                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 232         }
 233
 234         if (params->base.odt == 1)
 235                 tsel_rd_en = 1;
 236         else
 237                 tsel_rd_en = 0;
 238
 239         tsel_wr_en = 0;
 240         tsel_idle_en = 0;
 241
 242         /*
 243          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 244          * sets termination values for read/idle cycles and drive strength
 245          * for write cycles for DQ/DM
 246          */
 247         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 248                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 249                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 250         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 251         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 252         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 253         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 254
 255         /*
 256          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 257          * sets termination values for read/idle cycles and drive strength
 258          * for write cycles for DQS
 259          */
 260         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 261         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 262         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 263         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 264
 265         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 266         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 267         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 268         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 269         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 270
 271         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 272         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 273
 274         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 275         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 276
 277         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 278         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 279
 280         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 281         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 282
 283         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 284         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 285
 286         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 287         clrsetbits_le32(&denali_phy[924], 0xff,
 288                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 289         clrsetbits_le32(&denali_phy[925], 0xff,
 290                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 291
 292         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 293         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 294                 << 16;
 295         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 296         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 297         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 298         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 299
 300         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 301         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 302                 << 24;
 303         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 304         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 305         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 306         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 307
 308         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 309         reg_value = tsel_wr_en << 8;
 310         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 311         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 312         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 313
 314         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 315         reg_value = tsel_wr_en << 17;
 316         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 317         /*
 318          * pad_rst/cke/cs/clk_term tsel 1bits
 319          * DENALI_PHY_938/936/940/934 offset_17
 320          */
 321         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 322         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 323         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 324         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 325
 326         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 327         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 328 }
 329
 330 static int phy_io_config(const struct chan_info *chan,
 331                          const struct rk3399_sdram_params *params)
 332 {
 333         u32 *denali_phy = chan->publ->denali_phy;
 334         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 335         u32 mode_sel;
 336         u32 reg_value;
 337         u32 drv_value, odt_value;
 338         u32 speed;
 339
 340         /* vref setting */
 341         if (params->base.dramtype == LPDDR4) {
 342                 /* LPDDR4 */
 343                 vref_mode_dq = 0x6;
 344                 vref_value_dq = 0x1f;
 345                 vref_mode_ac = 0x6;
 346                 vref_value_ac = 0x1f;
 347         } else if (params->base.dramtype == LPDDR3) {
 348                 if (params->base.odt == 1) {
 349                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 350                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 351                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 352                         if (drv_value == PHY_DRV_ODT_48) {
 353                                 switch (odt_value) {
 354                                 case PHY_DRV_ODT_240:
 355                                         vref_value_dq = 0x16;
 356                                         break;
 357                                 case PHY_DRV_ODT_120:
 358                                         vref_value_dq = 0x26;
 359                                         break;
 360                                 case PHY_DRV_ODT_60:
 361                                         vref_value_dq = 0x36;
 362                                         break;
 363                                 default:
 364                                         debug("Invalid ODT value.\n");
 365                                         return -EINVAL;
 366                                 }
 367                         } else if (drv_value == PHY_DRV_ODT_40) {
 368                                 switch (odt_value) {
 369                                 case PHY_DRV_ODT_240:
 370                                         vref_value_dq = 0x19;
 371                                         break;
 372                                 case PHY_DRV_ODT_120:
 373                                         vref_value_dq = 0x23;
 374                                         break;
 375                                 case PHY_DRV_ODT_60:
 376                                         vref_value_dq = 0x31;
 377                                         break;
 378                                 default:
 379                                         debug("Invalid ODT value.\n");
 380                                         return -EINVAL;
 381                                 }
 382                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 383                                 switch (odt_value) {
 384                                 case PHY_DRV_ODT_240:
 385                                         vref_value_dq = 0x17;
 386                                         break;
 387                                 case PHY_DRV_ODT_120:
 388                                         vref_value_dq = 0x20;
 389                                         break;
 390                                 case PHY_DRV_ODT_60:
 391                                         vref_value_dq = 0x2e;
 392                                         break;
 393                                 default:
 394                                         debug("Invalid ODT value.\n");
 395                                         return -EINVAL;
 396                                 }
 397                         } else {
 398                                 debug("Invalid DRV value.\n");
 399                                 return -EINVAL;
 400                         }
 401                 } else {
 402                         vref_mode_dq = 0x2;  /* LPDDR3 */
 403                         vref_value_dq = 0x1f;
 404                 }
 405                 vref_mode_ac = 0x2;
 406                 vref_value_ac = 0x1f;
 407         } else if (params->base.dramtype == DDR3) {
 408                 /* DDR3L */
 409                 vref_mode_dq = 0x1;
 410                 vref_value_dq = 0x1f;
 411                 vref_mode_ac = 0x1;
 412                 vref_value_ac = 0x1f;
 413         } else {
 414                 debug("Unknown DRAM type.\n");
 415                 return -EINVAL;
 416         }
 417
 418         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 419
 420         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 421         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 422         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 423         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 424         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 425         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 426         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 427         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 428
 429         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 430
 431         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 432         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 433
 434         if (params->base.dramtype == LPDDR4)
 435                 mode_sel = 0x6;
 436         else if (params->base.dramtype == LPDDR3)
 437                 mode_sel = 0x0;
 438         else if (params->base.dramtype == DDR3)
 439                 mode_sel = 0x1;
 440         else
 441                 return -EINVAL;
 442
 443         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 444         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 445         /* PHY_926 PHY_PAD_DATA_DRIVE */
 446         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 447         /* PHY_927 PHY_PAD_DQS_DRIVE */
 448         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 449         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 450         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 451         /* PHY_929 PHY_PAD_CLK_DRIVE */
 452         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 453         /* PHY_935 PHY_PAD_CKE_DRIVE */
 454         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 455         /* PHY_937 PHY_PAD_RST_DRIVE */
 456         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 457         /* PHY_939 PHY_PAD_CS_DRIVE */
 458         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 459
 460         /* speed setting */
 461         if (params->base.ddr_freq < 400)
 462                 speed = 0x0;
 463         else if (params->base.ddr_freq < 800)
 464                 speed = 0x1;
 465         else if (params->base.ddr_freq < 1200)
 466                 speed = 0x2;
 467         else
 468                 speed = 0x3;
 469
 470         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 471         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 472         /* PHY_926 PHY_PAD_DATA_DRIVE */
 473         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 474         /* PHY_927 PHY_PAD_DQS_DRIVE */
 475         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 476         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 477         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 478         /* PHY_929 PHY_PAD_CLK_DRIVE */
 479         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 480         /* PHY_935 PHY_PAD_CKE_DRIVE */
 481         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 482         /* PHY_937 PHY_PAD_RST_DRIVE */
 483         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 484         /* PHY_939 PHY_PAD_CS_DRIVE */
 485         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 486
 487         return 0;
 488 }
 489
 490 static int pctl_cfg(const struct chan_info *chan, u32 channel,
 491                     const struct rk3399_sdram_params *params)
 492 {
 493         u32 *denali_ctl = chan->pctl->denali_ctl;
 494         u32 *denali_pi = chan->pi->denali_pi;
 495         u32 *denali_phy = chan->publ->denali_phy;
 496         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 497         const u32 *params_phy = params->phy_regs.denali_phy;
 498         u32 tmp, tmp1, tmp2;
 499         u32 pwrup_srefresh_exit;
 500         int ret;
 501         const ulong timeout_ms = 200;
 502
 503         /*
 504          * work around controller bug:
 505          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 506          */
 507         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 508                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 509         writel(params_ctl[0], &denali_ctl[0]);
 510
 511         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 512                     sizeof(struct rk3399_ddr_pi_regs));
 513
 514         /* rank count need to set for init */
 515         set_memory_map(chan, channel, params);
 516
 517         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 518         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 519         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 520
 521         pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
 522         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 523
 524         /* PHY_DLL_RST_EN */
 525         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 526
 527         setbits_le32(&denali_pi[0], START);
 528         setbits_le32(&denali_ctl[0], START);
 529
 530         /* Waiting for phy DLL lock */
 531         while (1) {
 532                 tmp = readl(&denali_phy[920]);
 533                 tmp1 = readl(&denali_phy[921]);
 534                 tmp2 = readl(&denali_phy[922]);
 535                 if ((((tmp >> 16) & 0x1) == 0x1) &&
 536                     (((tmp1 >> 16) & 0x1) == 0x1) &&
 537                     (((tmp1 >> 0) & 0x1) == 0x1) &&
 538                     (((tmp2 >> 0) & 0x1) == 0x1))
 539                         break;
 540         }
 541
 542         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 543         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 544         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 545         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 546         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 547         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 548         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 549         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 550         set_ds_odt(chan, params);
 551
 552         /*
 553          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 554          * dqs_tsel_wr_end[7:4] add Half cycle
 555          */
 556         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 557         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 558         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 559         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 560         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 561         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 562         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 563         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 564
 565         /*
 566          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 567          * dq_tsel_wr_end[7:4] add Half cycle
 568          */
 569         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 570         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 571         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 572         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 573         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 574         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 575         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 576         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 577
 578         ret = phy_io_config(chan, params);
 579         if (ret)
 580                 return ret;
 581
 582         /* PHY_DLL_RST_EN */
 583         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 584
 585         /* Waiting for PHY and DRAM init complete */
 586         tmp = get_timer(0);
 587         do {
 588                 if (get_timer(tmp) > timeout_ms) {
 589                         pr_err("DRAM (%s): phy failed to lock within  %ld ms\n",
 590                                __func__, timeout_ms);
 591                         return -ETIME;
 592                 }
 593         } while (!(readl(&denali_ctl[203]) & (1 << 3)));
 594         debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 595
 596         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 597                         pwrup_srefresh_exit);
 598         return 0;
 599 }
 600
 601 static void select_per_cs_training_index(const struct chan_info *chan,
 602                                          u32 rank)
 603 {
 604         u32 *denali_phy = chan->publ->denali_phy;
 605
 606         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 607         if ((readl(&denali_phy[84]) >> 16) & 1) {
 608                 /*
 609                  * PHY_8/136/264/392
 610                  * phy_per_cs_training_index_X 1bit offset_24
 611                  */
 612                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 613                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 614                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 615                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 616         }
 617 }
 618
 619 static void override_write_leveling_value(const struct chan_info *chan)
 620 {
 621         u32 *denali_ctl = chan->pctl->denali_ctl;
 622         u32 *denali_phy = chan->publ->denali_phy;
 623         u32 byte;
 624
 625         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 626         setbits_le32(&denali_phy[896], 1);
 627
 628         /*
 629          * PHY_8/136/264/392
 630          * phy_per_cs_training_multicast_en_X 1bit offset_16
 631          */
 632         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 633         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 634         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 635         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 636
 637         for (byte = 0; byte < 4; byte++)
 638                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 639                                 0x200 << 16);
 640
 641         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 642         clrbits_le32(&denali_phy[896], 1);
 643
 644         /* CTL_200 ctrlupd_req 1bit offset_8 */
 645         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 646 }
 647
 648 static int data_training_ca(const struct chan_info *chan, u32 channel,
 649                             const struct rk3399_sdram_params *params)
 650 {
 651         u32 *denali_pi = chan->pi->denali_pi;
 652         u32 *denali_phy = chan->publ->denali_phy;
 653         u32 i, tmp;
 654         u32 obs_0, obs_1, obs_2, obs_err = 0;
 655         u32 rank = params->ch[channel].cap_info.rank;
 656         u32 rank_mask;
 657
 658         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 659         writel(0x00003f7c, (&denali_pi[175]));
 660
 661         rank_mask = (rank == 1) ? 0x1 : 0x3;
 662
 663         for (i = 0; i < 4; i++) {
 664                 if (!(rank_mask & (1 << i)))
 665                         continue;
 666
 667                 select_per_cs_training_index(chan, i);
 668
 669                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 670                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 671
 672                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 673                 clrsetbits_le32(&denali_pi[92],
 674                                 (0x1 << 16) | (0x3 << 24),
 675                                 (0x1 << 16) | (i << 24));
 676
 677                 /* Waiting for training complete */
 678                 while (1) {
 679                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 680                         tmp = readl(&denali_pi[174]) >> 8;
 681                         /*
 682                          * check status obs
 683                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 684                          */
 685                         obs_0 = readl(&denali_phy[532]);
 686                         obs_1 = readl(&denali_phy[660]);
 687                         obs_2 = readl(&denali_phy[788]);
 688                         if (((obs_0 >> 30) & 0x3) ||
 689                             ((obs_1 >> 30) & 0x3) ||
 690                             ((obs_2 >> 30) & 0x3))
 691                                 obs_err = 1;
 692                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 693                             (((tmp >> 13) & 0x1) == 0x1) &&
 694                             (((tmp >> 5) & 0x1) == 0x0) &&
 695                             obs_err == 0)
 696                                 break;
 697                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 698                                  (obs_err == 1))
 699                                 return -EIO;
 700                 }
 701
 702                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 703                 writel(0x00003f7c, (&denali_pi[175]));
 704         }
 705
 706         clrbits_le32(&denali_pi[100], 0x3 << 8);
 707
 708         return 0;
 709 }
 710
 711 static int data_training_wl(const struct chan_info *chan, u32 channel,
 712                             const struct rk3399_sdram_params *params)
 713 {
 714         u32 *denali_pi = chan->pi->denali_pi;
 715         u32 *denali_phy = chan->publ->denali_phy;
 716         u32 i, tmp;
 717         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 718         u32 rank = params->ch[channel].cap_info.rank;
 719
 720         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 721         writel(0x00003f7c, (&denali_pi[175]));
 722
 723         for (i = 0; i < rank; i++) {
 724                 select_per_cs_training_index(chan, i);
 725
 726                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 727                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 728
 729                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 730                 clrsetbits_le32(&denali_pi[59],
 731                                 (0x1 << 8) | (0x3 << 16),
 732                                 (0x1 << 8) | (i << 16));
 733
 734                 /* Waiting for training complete */
 735                 while (1) {
 736                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 737                         tmp = readl(&denali_pi[174]) >> 8;
 738
 739                         /*
 740                          * check status obs, if error maybe can not
 741                          * get leveling done PHY_40/168/296/424
 742                          * phy_wrlvl_status_obs_X:0:13
 743                          */
 744                         obs_0 = readl(&denali_phy[40]);
 745                         obs_1 = readl(&denali_phy[168]);
 746                         obs_2 = readl(&denali_phy[296]);
 747                         obs_3 = readl(&denali_phy[424]);
 748                         if (((obs_0 >> 12) & 0x1) ||
 749                             ((obs_1 >> 12) & 0x1) ||
 750                             ((obs_2 >> 12) & 0x1) ||
 751                             ((obs_3 >> 12) & 0x1))
 752                                 obs_err = 1;
 753                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 754                             (((tmp >> 13) & 0x1) == 0x1) &&
 755                             (((tmp >> 4) & 0x1) == 0x0) &&
 756                             obs_err == 0)
 757                                 break;
 758                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 759                                  (obs_err == 1))
 760                                 return -EIO;
 761                 }
 762
 763                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 764                 writel(0x00003f7c, (&denali_pi[175]));
 765         }
 766
 767         override_write_leveling_value(chan);
 768         clrbits_le32(&denali_pi[60], 0x3 << 8);
 769
 770         return 0;
 771 }
 772
 773 static int data_training_rg(const struct chan_info *chan, u32 channel,
 774                             const struct rk3399_sdram_params *params)
 775 {
 776         u32 *denali_pi = chan->pi->denali_pi;
 777         u32 *denali_phy = chan->publ->denali_phy;
 778         u32 i, tmp;
 779         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 780         u32 rank = params->ch[channel].cap_info.rank;
 781
 782         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 783         writel(0x00003f7c, (&denali_pi[175]));
 784
 785         for (i = 0; i < rank; i++) {
 786                 select_per_cs_training_index(chan, i);
 787
 788                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 789                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 790
 791                 /*
 792                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 793                  * PI_RDLVL_CS:RW:24:2
 794                  */
 795                 clrsetbits_le32(&denali_pi[74],
 796                                 (0x1 << 16) | (0x3 << 24),
 797                                 (0x1 << 16) | (i << 24));
 798
 799                 /* Waiting for training complete */
 800                 while (1) {
 801                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 802                         tmp = readl(&denali_pi[174]) >> 8;
 803
 804                         /*
 805                          * check status obs
 806                          * PHY_43/171/299/427
 807                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 808                          */
 809                         obs_0 = readl(&denali_phy[43]);
 810                         obs_1 = readl(&denali_phy[171]);
 811                         obs_2 = readl(&denali_phy[299]);
 812                         obs_3 = readl(&denali_phy[427]);
 813                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 814                             ((obs_1 >> (16 + 6)) & 0x3) ||
 815                             ((obs_2 >> (16 + 6)) & 0x3) ||
 816                             ((obs_3 >> (16 + 6)) & 0x3))
 817                                 obs_err = 1;
 818                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 819                             (((tmp >> 13) & 0x1) == 0x1) &&
 820                             (((tmp >> 3) & 0x1) == 0x0) &&
 821                             obs_err == 0)
 822                                 break;
 823                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 824                                  (obs_err == 1))
 825                                 return -EIO;
 826                 }
 827
 828                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 829                 writel(0x00003f7c, (&denali_pi[175]));
 830         }
 831
 832         clrbits_le32(&denali_pi[80], 0x3 << 24);
 833
 834         return 0;
 835 }
 836
 837 static int data_training_rl(const struct chan_info *chan, u32 channel,
 838                             const struct rk3399_sdram_params *params)
 839 {
 840         u32 *denali_pi = chan->pi->denali_pi;
 841         u32 i, tmp;
 842         u32 rank = params->ch[channel].cap_info.rank;
 843
 844         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 845         writel(0x00003f7c, (&denali_pi[175]));
 846
 847         for (i = 0; i < rank; i++) {
 848                 select_per_cs_training_index(chan, i);
 849
 850                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 851                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 852
 853                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 854                 clrsetbits_le32(&denali_pi[74],
 855                                 (0x1 << 8) | (0x3 << 24),
 856                                 (0x1 << 8) | (i << 24));
 857
 858                 /* Waiting for training complete */
 859                 while (1) {
 860                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 861                         tmp = readl(&denali_pi[174]) >> 8;
 862
 863                         /*
 864                          * make sure status obs not report error bit
 865                          * PHY_46/174/302/430
 866                          *     phy_rdlvl_status_obs_X:16:8
 867                          */
 868                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 869                             (((tmp >> 13) & 0x1) == 0x1) &&
 870                             (((tmp >> 2) & 0x1) == 0x0))
 871                                 break;
 872                         else if (((tmp >> 2) & 0x1) == 0x1)
 873                                 return -EIO;
 874                 }
 875
 876                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 877                 writel(0x00003f7c, (&denali_pi[175]));
 878         }
 879
 880         clrbits_le32(&denali_pi[80], 0x3 << 16);
 881
 882         return 0;
 883 }
 884
 885 static int data_training_wdql(const struct chan_info *chan, u32 channel,
 886                               const struct rk3399_sdram_params *params)
 887 {
 888         u32 *denali_pi = chan->pi->denali_pi;
 889         u32 i, tmp;
 890         u32 rank = params->ch[channel].cap_info.rank;
 891         u32 rank_mask;
 892
 893         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 894         writel(0x00003f7c, (&denali_pi[175]));
 895
 896         rank_mask = (rank == 1) ? 0x1 : 0x3;
 897
 898         for (i = 0; i < 4; i++) {
 899                 if (!(rank_mask & (1 << i)))
 900                         continue;
 901
 902                 select_per_cs_training_index(chan, i);
 903
 904                 /*
 905                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
 906                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
 907                  */
 908                 clrbits_le32(&denali_pi[181], 0x1 << 8);
 909
 910                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
 911                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
 912
 913                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
 914                 clrsetbits_le32(&denali_pi[121],
 915                                 (0x1 << 8) | (0x3 << 16),
 916                                 (0x1 << 8) | (i << 16));
 917
 918                 /* Waiting for training complete */
 919                 while (1) {
 920                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 921                         tmp = readl(&denali_pi[174]) >> 8;
 922                         if ((((tmp >> 12) & 0x1) == 0x1) &&
 923                             (((tmp >> 13) & 0x1) == 0x1) &&
 924                             (((tmp >> 6) & 0x1) == 0x0))
 925                                 break;
 926                         else if (((tmp >> 6) & 0x1) == 0x1)
 927                                 return -EIO;
 928                 }
 929
 930                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 931                 writel(0x00003f7c, (&denali_pi[175]));
 932         }
 933
 934         clrbits_le32(&denali_pi[124], 0x3 << 16);
 935
 936         return 0;
 937 }
 938
 939 static int data_training(const struct chan_info *chan, u32 channel,
 940                          const struct rk3399_sdram_params *params,
 941                          u32 training_flag)
 942 {
 943         u32 *denali_phy = chan->publ->denali_phy;
 944         int ret;
 945
 946         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 947         setbits_le32(&denali_phy[927], (1 << 22));
 948
 949         if (training_flag == PI_FULL_TRAINING) {
 950                 if (params->base.dramtype == LPDDR4) {
 951                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 952                                         PI_READ_GATE_TRAINING |
 953                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
 954                 } else if (params->base.dramtype == LPDDR3) {
 955                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 956                                         PI_READ_GATE_TRAINING;
 957                 } else if (params->base.dramtype == DDR3) {
 958                         training_flag = PI_WRITE_LEVELING |
 959                                         PI_READ_GATE_TRAINING |
 960                                         PI_READ_LEVELING;
 961                 }
 962         }
 963
 964         /* ca training(LPDDR4,LPDDR3 support) */
 965         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
 966                 ret = data_training_ca(chan, channel, params);
 967                 if (ret < 0) {
 968                         debug("%s: data training ca failed\n", __func__);
 969                         return ret;
 970                 }
 971         }
 972
 973         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 974         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
 975                 ret = data_training_wl(chan, channel, params);
 976                 if (ret < 0) {
 977                         debug("%s: data training wl failed\n", __func__);
 978                         return ret;
 979                 }
 980         }
 981
 982         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 983         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
 984                 ret = data_training_rg(chan, channel, params);
 985                 if (ret < 0) {
 986                         debug("%s: data training rg failed\n", __func__);
 987                         return ret;
 988                 }
 989         }
 990
 991         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 992         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
 993                 ret = data_training_rl(chan, channel, params);
 994                 if (ret < 0) {
 995                         debug("%s: data training rl failed\n", __func__);
 996                         return ret;
 997                 }
 998         }
 999
1000         /* wdq leveling(LPDDR4 support) */
1001         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1002                 ret = data_training_wdql(chan, channel, params);
1003                 if (ret < 0) {
1004                         debug("%s: data training wdql failed\n", __func__);
1005                         return ret;
1006                 }
1007         }
1008
1009         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1010         clrbits_le32(&denali_phy[927], (1 << 22));
1011
1012         return 0;
1013 }
1014
1015 static void set_ddrconfig(const struct chan_info *chan,
1016                           const struct rk3399_sdram_params *params,
1017                           unsigned char channel, u32 ddrconfig)
1018 {
1019         /* only need to set ddrconfig */
1020         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1021         unsigned int cs0_cap = 0;
1022         unsigned int cs1_cap = 0;
1023
1024         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1025                         + params->ch[channel].cap_info.col
1026                         + params->ch[channel].cap_info.bk
1027                         + params->ch[channel].cap_info.bw - 20));
1028         if (params->ch[channel].cap_info.rank > 1)
1029                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1030                                 - params->ch[channel].cap_info.cs1_row);
1031         if (params->ch[channel].cap_info.row_3_4) {
1032                 cs0_cap = cs0_cap * 3 / 4;
1033                 cs1_cap = cs1_cap * 3 / 4;
1034         }
1035
1036         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1037         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1038                &ddr_msch_regs->ddrsize);
1039 }
1040
1041 static void dram_all_config(struct dram_info *dram,
1042                             const struct rk3399_sdram_params *params)
1043 {
1044         u32 sys_reg = 0;
1045         unsigned int channel, idx;
1046
1047         sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
1048         sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
1049
1050         for (channel = 0, idx = 0;
1051              (idx < params->base.num_channels) && (channel < 2);
1052              channel++) {
1053                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1054                 struct rk3399_msch_regs *ddr_msch_regs;
1055                 const struct rk3399_msch_timings *noc_timing;
1056
1057                 if (params->ch[channel].cap_info.col == 0)
1058                         continue;
1059                 idx++;
1060                 sys_reg |= info->cap_info.row_3_4 <<
1061                            SYS_REG_ROW_3_4_SHIFT(channel);
1062                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
1063                 sys_reg |= (info->cap_info.rank - 1) <<
1064                            SYS_REG_RANK_SHIFT(channel);
1065                 sys_reg |= (info->cap_info.col - 9) <<
1066                            SYS_REG_COL_SHIFT(channel);
1067                 sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
1068                            SYS_REG_BK_SHIFT(channel);
1069                 sys_reg |= (info->cap_info.cs0_row - 13) <<
1070                             SYS_REG_CS0_ROW_SHIFT(channel);
1071                 sys_reg |= (info->cap_info.cs1_row - 13) <<
1072                             SYS_REG_CS1_ROW_SHIFT(channel);
1073                 sys_reg |= (2 >> info->cap_info.bw) <<
1074                            SYS_REG_BW_SHIFT(channel);
1075                 sys_reg |= (2 >> info->cap_info.dbw) <<
1076                            SYS_REG_DBW_SHIFT(channel);
1077
1078                 ddr_msch_regs = dram->chan[channel].msch;
1079                 noc_timing = &params->ch[channel].noc_timings;
1080                 writel(noc_timing->ddrtiminga0,
1081                        &ddr_msch_regs->ddrtiminga0);
1082                 writel(noc_timing->ddrtimingb0,
1083                        &ddr_msch_regs->ddrtimingb0);
1084                 writel(noc_timing->ddrtimingc0,
1085                        &ddr_msch_regs->ddrtimingc0);
1086                 writel(noc_timing->devtodev0,
1087                        &ddr_msch_regs->devtodev0);
1088                 writel(noc_timing->ddrmode,
1089                        &ddr_msch_regs->ddrmode);
1090
1091                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1092                 if (params->ch[channel].cap_info.rank == 1)
1093                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1094                                      1 << 17);
1095         }
1096
1097         writel(sys_reg, &dram->pmugrf->os_reg2);
1098         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1099                      params->base.stride << 10);
1100
1101         /* reboot hold register set */
1102         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1103                 PRESET_GPIO1_HOLD(1),
1104                 &dram->pmucru->pmucru_rstnhold_con[1]);
1105         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1106 }
1107
1108 static int switch_to_phy_index1(struct dram_info *dram,
1109                                 const struct rk3399_sdram_params *params)
1110 {
1111         u32 channel;
1112         u32 *denali_phy;
1113         u32 ch_count = params->base.num_channels;
1114         int ret;
1115         int i = 0;
1116
1117         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1118                              1 << 4 | 1 << 2 | 1),
1119                         &dram->cic->cic_ctrl0);
1120         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1121                 mdelay(10);
1122                 i++;
1123                 if (i > 10) {
1124                         debug("index1 frequency change overtime\n");
1125                         return -ETIME;
1126                 }
1127         }
1128
1129         i = 0;
1130         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1131         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1132                 mdelay(10);
1133                 i++;
1134                 if (i > 10) {
1135                         debug("index1 frequency done overtime\n");
1136                         return -ETIME;
1137                 }
1138         }
1139
1140         for (channel = 0; channel < ch_count; channel++) {
1141                 denali_phy = dram->chan[channel].publ->denali_phy;
1142                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1143                 ret = data_training(&dram->chan[channel], channel,
1144                                     params, PI_FULL_TRAINING);
1145                 if (ret < 0) {
1146                         debug("index1 training failed\n");
1147                         return ret;
1148                 }
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int sdram_init(struct dram_info *dram,
1155                       const struct rk3399_sdram_params *params)
1156 {
1157         unsigned char dramtype = params->base.dramtype;
1158         unsigned int ddr_freq = params->base.ddr_freq;
1159         struct rk3399_cru *cru = dram->cru;
1160         int channel;
1161         int ret;
1162
1163         debug("Starting SDRAM initialization...\n");
1164
1165         if ((dramtype == DDR3 && ddr_freq > 933) ||
1166             (dramtype == LPDDR3 && ddr_freq > 933) ||
1167             (dramtype == LPDDR4 && ddr_freq > 800)) {
1168                 debug("SDRAM frequency is to high!");
1169                 return -E2BIG;
1170         }
1171
1172         for (channel = 0; channel < 2; channel++) {
1173                 const struct chan_info *chan = &dram->chan[channel];
1174                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1175
1176                 phy_pctrl_reset(cru, channel);
1177                 phy_dll_bypass_set(publ, ddr_freq);
1178
1179                 if (channel >= params->base.num_channels)
1180                         continue;
1181
1182                 ret = pctl_cfg(chan, channel, params);
1183                 if (ret < 0) {
1184                         printf("%s: pctl config failed\n", __func__);
1185                         return ret;
1186                 }
1187
1188                 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1189                 if (dramtype == LPDDR3)
1190                         udelay(10);
1191
1192                 if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
1193                         printf("%s: data training failed\n", __func__);
1194                         return -EIO;
1195                 }
1196
1197                 set_ddrconfig(chan, params, channel,
1198                               params->ch[channel].cap_info.ddrconfig);
1199         }
1200         dram_all_config(dram, params);
1201         switch_to_phy_index1(dram, params);
1202
1203         debug("Finish SDRAM initialization...\n");
1204         return 0;
1205 }
1206
1207 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1208 {
1209 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1210         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1211         int ret;
1212
1213         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1214                                  (u32 *)&plat->sdram_params,
1215                                  sizeof(plat->sdram_params) / sizeof(u32));
1216         if (ret) {
1217                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1218                        __func__, ret);
1219                 return ret;
1220         }
1221         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1222         if (ret)
1223                 printf("%s: regmap failed %d\n", __func__, ret);
1224
1225 #endif
1226         return 0;
1227 }
1228
1229 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1230 static int conv_of_platdata(struct udevice *dev)
1231 {
1232         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1233         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1234         int ret;
1235
1236         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1237                                        ARRAY_SIZE(dtplat->reg) / 2,
1238                                        &plat->map);
1239         if (ret)
1240                 return ret;
1241
1242         return 0;
1243 }
1244 #endif
1245
1246 static int rk3399_dmc_init(struct udevice *dev)
1247 {
1248         struct dram_info *priv = dev_get_priv(dev);
1249         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1250         int ret;
1251 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1252         struct rk3399_sdram_params *params = &plat->sdram_params;
1253 #else
1254         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1255         struct rk3399_sdram_params *params =
1256                                         (void *)dtplat->rockchip_sdram_params;
1257
1258         ret = conv_of_platdata(dev);
1259         if (ret)
1260                 return ret;
1261 #endif
1262
1263         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1264         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1265         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1266         priv->pmucru = rockchip_get_pmucru();
1267         priv->cru = rockchip_get_cru();
1268         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1269         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1270         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1271         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1272         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1273         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1274         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1275         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1276
1277         debug("con reg %p %p %p %p %p %p %p %p\n",
1278               priv->chan[0].pctl, priv->chan[0].pi,
1279               priv->chan[0].publ, priv->chan[0].msch,
1280               priv->chan[1].pctl, priv->chan[1].pi,
1281               priv->chan[1].publ, priv->chan[1].msch);
1282         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1283               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1284
1285 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1286         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1287 #else
1288         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1289 #endif
1290         if (ret) {
1291                 printf("%s clk get failed %d\n", __func__, ret);
1292                 return ret;
1293         }
1294
1295         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1296         if (ret < 0) {
1297                 printf("%s clk set failed %d\n", __func__, ret);
1298                 return ret;
1299         }
1300
1301         ret = sdram_init(priv, params);
1302         if (ret < 0) {
1303                 printf("%s DRAM init failed %d\n", __func__, ret);
1304                 return ret;
1305         }
1306
1307         return 0;
1308 }
1309 #endif
1310
1311 static int rk3399_dmc_probe(struct udevice *dev)
1312 {
1313 #if defined(CONFIG_TPL_BUILD) || \
1314         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1315         if (rk3399_dmc_init(dev))
1316                 return 0;
1317 #else
1318         struct dram_info *priv = dev_get_priv(dev);
1319
1320         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1321         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1322         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1323         priv->info.size =
1324                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1325 #endif
1326         return 0;
1327 }
1328
1329 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1330 {
1331         struct dram_info *priv = dev_get_priv(dev);
1332
1333         *info = priv->info;
1334
1335         return 0;
1336 }
1337
1338 static struct ram_ops rk3399_dmc_ops = {
1339         .get_info = rk3399_dmc_get_info,
1340 };
1341
1342 static const struct udevice_id rk3399_dmc_ids[] = {
1343         { .compatible = "rockchip,rk3399-dmc" },
1344         { }
1345 };
1346
1347 U_BOOT_DRIVER(dmc_rk3399) = {
1348         .name = "rockchip_rk3399_dmc",
1349         .id = UCLASS_RAM,
1350         .of_match = rk3399_dmc_ids,
1351         .ops = &rk3399_dmc_ops,
1352 #if defined(CONFIG_TPL_BUILD) || \
1353         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1354         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1355 #endif
1356         .probe = rk3399_dmc_probe,
1357         .priv_auto_alloc_size = sizeof(struct dram_info),
1358 #if defined(CONFIG_TPL_BUILD) || \
1359         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1360         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1361 #endif
1362 };