drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 struct chan_info {
  39         struct rk3399_ddr_pctl_regs *pctl;
  40         struct rk3399_ddr_pi_regs *pi;
  41         struct rk3399_ddr_publ_regs *publ;
  42         struct rk3399_msch_regs *msch;
  43 };
  44
  45 struct dram_info {
  46 #if defined(CONFIG_TPL_BUILD) || \
  47         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  48         struct chan_info chan[2];
  49         struct clk ddr_clk;
  50         struct rk3399_cru *cru;
  51         struct rk3399_pmucru *pmucru;
  52         struct rk3399_pmusgrf_regs *pmusgrf;
  53         struct rk3399_ddr_cic_regs *cic;
  54 #endif
  55         struct ram_info info;
  56         struct rk3399_pmugrf_regs *pmugrf;
  57 };
  58
  59 #if defined(CONFIG_TPL_BUILD) || \
  60         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  61
  62 struct rockchip_dmc_plat {
  63 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  64         struct dtd_rockchip_rk3399_dmc dtplat;
  65 #else
  66         struct rk3399_sdram_params sdram_params;
  67 #endif
  68         struct regmap *map;
  69 };
  70
  71 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  72 {
  73         int i;
  74
  75         for (i = 0; i < n / sizeof(u32); i++) {
  76                 writel(*src, dest);
  77                 src++;
  78                 dest++;
  79         }
  80 }
  81
  82 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
  83                                u32 freq)
  84 {
  85         u32 *denali_phy = ddr_publ_regs->denali_phy;
  86
  87         /* From IP spec, only freq small than 125 can enter dll bypass mode */
  88         if (freq <= 125) {
  89                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
  90                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
  91                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
  92                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
  93                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
  94
  95                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
  96                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
  97                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
  98                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
  99         } else {
 100                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 101                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 102                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 103                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 104                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 105
 106                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 107                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 108                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 109                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 110         }
 111 }
 112
 113 static void set_memory_map(const struct chan_info *chan, u32 channel,
 114                            const struct rk3399_sdram_params *params)
 115 {
 116         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 117         u32 *denali_ctl = chan->pctl->denali_ctl;
 118         u32 *denali_pi = chan->pi->denali_pi;
 119         u32 cs_map;
 120         u32 reduc;
 121         u32 row;
 122
 123         /* Get row number from ddrconfig setting */
 124         if (sdram_ch->cap_info.ddrconfig < 2 ||
 125             sdram_ch->cap_info.ddrconfig == 4)
 126                 row = 16;
 127         else if (sdram_ch->cap_info.ddrconfig == 3)
 128                 row = 14;
 129         else
 130                 row = 15;
 131
 132         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 133         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 134
 135         /* Set the dram configuration to ctrl */
 136         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 137         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 138                         ((3 - sdram_ch->cap_info.bk) << 16) |
 139                         ((16 - row) << 24));
 140
 141         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 142                         cs_map | (reduc << 16));
 143
 144         /* PI_199 PI_COL_DIFF:RW:0:4 */
 145         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 146
 147         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 148         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 149                         ((3 - sdram_ch->cap_info.bk) << 16) |
 150                         ((16 - row) << 24));
 151         /* PI_41 PI_CS_MAP:RW:24:4 */
 152         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 153         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 154                 writel(0x2EC7FFFF, &denali_pi[34]);
 155 }
 156
 157 static void set_ds_odt(const struct chan_info *chan,
 158                        const struct rk3399_sdram_params *params)
 159 {
 160         u32 *denali_phy = chan->publ->denali_phy;
 161
 162         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 163         u32 tsel_idle_select_p, tsel_rd_select_p;
 164         u32 tsel_idle_select_n, tsel_rd_select_n;
 165         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 166         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 167         u32 reg_value;
 168
 169         if (params->base.dramtype == LPDDR4) {
 170                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 171                 tsel_rd_select_n = PHY_DRV_ODT_240;
 172
 173                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 174                 tsel_idle_select_n = PHY_DRV_ODT_240;
 175
 176                 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 177                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 178
 179                 tsel_wr_select_ca_p = PHY_DRV_ODT_40;
 180                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 181         } else if (params->base.dramtype == LPDDR3) {
 182                 tsel_rd_select_p = PHY_DRV_ODT_240;
 183                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 184
 185                 tsel_idle_select_p = PHY_DRV_ODT_240;
 186                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 187
 188                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 189                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 190
 191                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 192                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 193         } else {
 194                 tsel_rd_select_p = PHY_DRV_ODT_240;
 195                 tsel_rd_select_n = PHY_DRV_ODT_240;
 196
 197                 tsel_idle_select_p = PHY_DRV_ODT_240;
 198                 tsel_idle_select_n = PHY_DRV_ODT_240;
 199
 200                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 201                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 202
 203                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 204                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 205         }
 206
 207         if (params->base.odt == 1)
 208                 tsel_rd_en = 1;
 209         else
 210                 tsel_rd_en = 0;
 211
 212         tsel_wr_en = 0;
 213         tsel_idle_en = 0;
 214
 215         /*
 216          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 217          * sets termination values for read/idle cycles and drive strength
 218          * for write cycles for DQ/DM
 219          */
 220         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 221                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 222                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 223         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 224         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 225         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 226         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 227
 228         /*
 229          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 230          * sets termination values for read/idle cycles and drive strength
 231          * for write cycles for DQS
 232          */
 233         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 234         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 235         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 236         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 237
 238         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 239         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 240         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 241         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 242         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 243
 244         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 245         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 246
 247         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 248         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 249
 250         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 251         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 252
 253         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 254         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 255
 256         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 257         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 258
 259         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 260         clrsetbits_le32(&denali_phy[924], 0xff,
 261                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 262         clrsetbits_le32(&denali_phy[925], 0xff,
 263                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 264
 265         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 266         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 267                 << 16;
 268         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 269         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 270         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 271         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 272
 273         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 274         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 275                 << 24;
 276         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 277         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 278         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 279         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 280
 281         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 282         reg_value = tsel_wr_en << 8;
 283         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 284         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 285         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 286
 287         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 288         reg_value = tsel_wr_en << 17;
 289         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 290         /*
 291          * pad_rst/cke/cs/clk_term tsel 1bits
 292          * DENALI_PHY_938/936/940/934 offset_17
 293          */
 294         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 295         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 296         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 297         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 298
 299         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 300         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 301 }
 302
 303 static int phy_io_config(const struct chan_info *chan,
 304                          const struct rk3399_sdram_params *params)
 305 {
 306         u32 *denali_phy = chan->publ->denali_phy;
 307         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 308         u32 mode_sel;
 309         u32 reg_value;
 310         u32 drv_value, odt_value;
 311         u32 speed;
 312
 313         /* vref setting */
 314         if (params->base.dramtype == LPDDR4) {
 315                 /* LPDDR4 */
 316                 vref_mode_dq = 0x6;
 317                 vref_value_dq = 0x1f;
 318                 vref_mode_ac = 0x6;
 319                 vref_value_ac = 0x1f;
 320         } else if (params->base.dramtype == LPDDR3) {
 321                 if (params->base.odt == 1) {
 322                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 323                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 324                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 325                         if (drv_value == PHY_DRV_ODT_48) {
 326                                 switch (odt_value) {
 327                                 case PHY_DRV_ODT_240:
 328                                         vref_value_dq = 0x16;
 329                                         break;
 330                                 case PHY_DRV_ODT_120:
 331                                         vref_value_dq = 0x26;
 332                                         break;
 333                                 case PHY_DRV_ODT_60:
 334                                         vref_value_dq = 0x36;
 335                                         break;
 336                                 default:
 337                                         debug("Invalid ODT value.\n");
 338                                         return -EINVAL;
 339                                 }
 340                         } else if (drv_value == PHY_DRV_ODT_40) {
 341                                 switch (odt_value) {
 342                                 case PHY_DRV_ODT_240:
 343                                         vref_value_dq = 0x19;
 344                                         break;
 345                                 case PHY_DRV_ODT_120:
 346                                         vref_value_dq = 0x23;
 347                                         break;
 348                                 case PHY_DRV_ODT_60:
 349                                         vref_value_dq = 0x31;
 350                                         break;
 351                                 default:
 352                                         debug("Invalid ODT value.\n");
 353                                         return -EINVAL;
 354                                 }
 355                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 356                                 switch (odt_value) {
 357                                 case PHY_DRV_ODT_240:
 358                                         vref_value_dq = 0x17;
 359                                         break;
 360                                 case PHY_DRV_ODT_120:
 361                                         vref_value_dq = 0x20;
 362                                         break;
 363                                 case PHY_DRV_ODT_60:
 364                                         vref_value_dq = 0x2e;
 365                                         break;
 366                                 default:
 367                                         debug("Invalid ODT value.\n");
 368                                         return -EINVAL;
 369                                 }
 370                         } else {
 371                                 debug("Invalid DRV value.\n");
 372                                 return -EINVAL;
 373                         }
 374                 } else {
 375                         vref_mode_dq = 0x2;  /* LPDDR3 */
 376                         vref_value_dq = 0x1f;
 377                 }
 378                 vref_mode_ac = 0x2;
 379                 vref_value_ac = 0x1f;
 380         } else if (params->base.dramtype == DDR3) {
 381                 /* DDR3L */
 382                 vref_mode_dq = 0x1;
 383                 vref_value_dq = 0x1f;
 384                 vref_mode_ac = 0x1;
 385                 vref_value_ac = 0x1f;
 386         } else {
 387                 debug("Unknown DRAM type.\n");
 388                 return -EINVAL;
 389         }
 390
 391         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 392
 393         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 394         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 395         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 396         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 397         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 398         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 399         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 400         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 401
 402         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 403
 404         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 405         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 406
 407         if (params->base.dramtype == LPDDR4)
 408                 mode_sel = 0x6;
 409         else if (params->base.dramtype == LPDDR3)
 410                 mode_sel = 0x0;
 411         else if (params->base.dramtype == DDR3)
 412                 mode_sel = 0x1;
 413         else
 414                 return -EINVAL;
 415
 416         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 417         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 418         /* PHY_926 PHY_PAD_DATA_DRIVE */
 419         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 420         /* PHY_927 PHY_PAD_DQS_DRIVE */
 421         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 422         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 423         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 424         /* PHY_929 PHY_PAD_CLK_DRIVE */
 425         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 426         /* PHY_935 PHY_PAD_CKE_DRIVE */
 427         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 428         /* PHY_937 PHY_PAD_RST_DRIVE */
 429         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 430         /* PHY_939 PHY_PAD_CS_DRIVE */
 431         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 432
 433         /* speed setting */
 434         if (params->base.ddr_freq < 400)
 435                 speed = 0x0;
 436         else if (params->base.ddr_freq < 800)
 437                 speed = 0x1;
 438         else if (params->base.ddr_freq < 1200)
 439                 speed = 0x2;
 440         else
 441                 speed = 0x3;
 442
 443         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 444         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 445         /* PHY_926 PHY_PAD_DATA_DRIVE */
 446         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 447         /* PHY_927 PHY_PAD_DQS_DRIVE */
 448         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 449         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 450         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 451         /* PHY_929 PHY_PAD_CLK_DRIVE */
 452         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 453         /* PHY_935 PHY_PAD_CKE_DRIVE */
 454         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 455         /* PHY_937 PHY_PAD_RST_DRIVE */
 456         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 457         /* PHY_939 PHY_PAD_CS_DRIVE */
 458         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 459
 460         return 0;
 461 }
 462
 463 static int pctl_cfg(const struct chan_info *chan, u32 channel,
 464                     const struct rk3399_sdram_params *params)
 465 {
 466         u32 *denali_ctl = chan->pctl->denali_ctl;
 467         u32 *denali_pi = chan->pi->denali_pi;
 468         u32 *denali_phy = chan->publ->denali_phy;
 469         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 470         const u32 *params_phy = params->phy_regs.denali_phy;
 471         u32 tmp, tmp1, tmp2;
 472         u32 pwrup_srefresh_exit;
 473         int ret;
 474         const ulong timeout_ms = 200;
 475
 476         /*
 477          * work around controller bug:
 478          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 479          */
 480         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 481                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 482         writel(params_ctl[0], &denali_ctl[0]);
 483
 484         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 485                     sizeof(struct rk3399_ddr_pi_regs));
 486
 487         /* rank count need to set for init */
 488         set_memory_map(chan, channel, params);
 489
 490         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 491         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 492         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 493
 494         pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
 495         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 496
 497         /* PHY_DLL_RST_EN */
 498         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 499
 500         setbits_le32(&denali_pi[0], START);
 501         setbits_le32(&denali_ctl[0], START);
 502
 503         /* Waiting for phy DLL lock */
 504         while (1) {
 505                 tmp = readl(&denali_phy[920]);
 506                 tmp1 = readl(&denali_phy[921]);
 507                 tmp2 = readl(&denali_phy[922]);
 508                 if ((((tmp >> 16) & 0x1) == 0x1) &&
 509                     (((tmp1 >> 16) & 0x1) == 0x1) &&
 510                     (((tmp1 >> 0) & 0x1) == 0x1) &&
 511                     (((tmp2 >> 0) & 0x1) == 0x1))
 512                         break;
 513         }
 514
 515         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 516         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 517         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 518         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 519         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 520         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 521         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 522         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 523         set_ds_odt(chan, params);
 524
 525         /*
 526          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 527          * dqs_tsel_wr_end[7:4] add Half cycle
 528          */
 529         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 530         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 531         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 532         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 533         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 534         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 535         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 536         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 537
 538         /*
 539          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 540          * dq_tsel_wr_end[7:4] add Half cycle
 541          */
 542         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 543         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 544         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 545         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 546         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 547         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 548         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 549         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 550
 551         ret = phy_io_config(chan, params);
 552         if (ret)
 553                 return ret;
 554
 555         /* PHY_DLL_RST_EN */
 556         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 557
 558         /* Waiting for PHY and DRAM init complete */
 559         tmp = get_timer(0);
 560         do {
 561                 if (get_timer(tmp) > timeout_ms) {
 562                         pr_err("DRAM (%s): phy failed to lock within  %ld ms\n",
 563                                __func__, timeout_ms);
 564                         return -ETIME;
 565                 }
 566         } while (!(readl(&denali_ctl[203]) & (1 << 3)));
 567         debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 568
 569         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 570                         pwrup_srefresh_exit);
 571         return 0;
 572 }
 573
 574 static void select_per_cs_training_index(const struct chan_info *chan,
 575                                          u32 rank)
 576 {
 577         u32 *denali_phy = chan->publ->denali_phy;
 578
 579         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 580         if ((readl(&denali_phy[84]) >> 16) & 1) {
 581                 /*
 582                  * PHY_8/136/264/392
 583                  * phy_per_cs_training_index_X 1bit offset_24
 584                  */
 585                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 586                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 587                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 588                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 589         }
 590 }
 591
 592 static void override_write_leveling_value(const struct chan_info *chan)
 593 {
 594         u32 *denali_ctl = chan->pctl->denali_ctl;
 595         u32 *denali_phy = chan->publ->denali_phy;
 596         u32 byte;
 597
 598         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 599         setbits_le32(&denali_phy[896], 1);
 600
 601         /*
 602          * PHY_8/136/264/392
 603          * phy_per_cs_training_multicast_en_X 1bit offset_16
 604          */
 605         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 606         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 607         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 608         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 609
 610         for (byte = 0; byte < 4; byte++)
 611                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 612                                 0x200 << 16);
 613
 614         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 615         clrbits_le32(&denali_phy[896], 1);
 616
 617         /* CTL_200 ctrlupd_req 1bit offset_8 */
 618         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 619 }
 620
 621 static int data_training_ca(const struct chan_info *chan, u32 channel,
 622                             const struct rk3399_sdram_params *params)
 623 {
 624         u32 *denali_pi = chan->pi->denali_pi;
 625         u32 *denali_phy = chan->publ->denali_phy;
 626         u32 i, tmp;
 627         u32 obs_0, obs_1, obs_2, obs_err = 0;
 628         u32 rank = params->ch[channel].cap_info.rank;
 629         u32 rank_mask;
 630
 631         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 632         writel(0x00003f7c, (&denali_pi[175]));
 633
 634         rank_mask = (rank == 1) ? 0x1 : 0x3;
 635
 636         for (i = 0; i < 4; i++) {
 637                 if (!(rank_mask & (1 << i)))
 638                         continue;
 639
 640                 select_per_cs_training_index(chan, i);
 641
 642                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 643                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 644
 645                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 646                 clrsetbits_le32(&denali_pi[92],
 647                                 (0x1 << 16) | (0x3 << 24),
 648                                 (0x1 << 16) | (i << 24));
 649
 650                 /* Waiting for training complete */
 651                 while (1) {
 652                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 653                         tmp = readl(&denali_pi[174]) >> 8;
 654                         /*
 655                          * check status obs
 656                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 657                          */
 658                         obs_0 = readl(&denali_phy[532]);
 659                         obs_1 = readl(&denali_phy[660]);
 660                         obs_2 = readl(&denali_phy[788]);
 661                         if (((obs_0 >> 30) & 0x3) ||
 662                             ((obs_1 >> 30) & 0x3) ||
 663                             ((obs_2 >> 30) & 0x3))
 664                                 obs_err = 1;
 665                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 666                             (((tmp >> 13) & 0x1) == 0x1) &&
 667                             (((tmp >> 5) & 0x1) == 0x0) &&
 668                             obs_err == 0)
 669                                 break;
 670                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 671                                  (obs_err == 1))
 672                                 return -EIO;
 673                 }
 674
 675                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 676                 writel(0x00003f7c, (&denali_pi[175]));
 677         }
 678
 679         clrbits_le32(&denali_pi[100], 0x3 << 8);
 680
 681         return 0;
 682 }
 683
 684 static int data_training_wl(const struct chan_info *chan, u32 channel,
 685                             const struct rk3399_sdram_params *params)
 686 {
 687         u32 *denali_pi = chan->pi->denali_pi;
 688         u32 *denali_phy = chan->publ->denali_phy;
 689         u32 i, tmp;
 690         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 691         u32 rank = params->ch[channel].cap_info.rank;
 692
 693         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 694         writel(0x00003f7c, (&denali_pi[175]));
 695
 696         for (i = 0; i < rank; i++) {
 697                 select_per_cs_training_index(chan, i);
 698
 699                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 700                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 701
 702                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 703                 clrsetbits_le32(&denali_pi[59],
 704                                 (0x1 << 8) | (0x3 << 16),
 705                                 (0x1 << 8) | (i << 16));
 706
 707                 /* Waiting for training complete */
 708                 while (1) {
 709                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 710                         tmp = readl(&denali_pi[174]) >> 8;
 711
 712                         /*
 713                          * check status obs, if error maybe can not
 714                          * get leveling done PHY_40/168/296/424
 715                          * phy_wrlvl_status_obs_X:0:13
 716                          */
 717                         obs_0 = readl(&denali_phy[40]);
 718                         obs_1 = readl(&denali_phy[168]);
 719                         obs_2 = readl(&denali_phy[296]);
 720                         obs_3 = readl(&denali_phy[424]);
 721                         if (((obs_0 >> 12) & 0x1) ||
 722                             ((obs_1 >> 12) & 0x1) ||
 723                             ((obs_2 >> 12) & 0x1) ||
 724                             ((obs_3 >> 12) & 0x1))
 725                                 obs_err = 1;
 726                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 727                             (((tmp >> 13) & 0x1) == 0x1) &&
 728                             (((tmp >> 4) & 0x1) == 0x0) &&
 729                             obs_err == 0)
 730                                 break;
 731                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 732                                  (obs_err == 1))
 733                                 return -EIO;
 734                 }
 735
 736                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 737                 writel(0x00003f7c, (&denali_pi[175]));
 738         }
 739
 740         override_write_leveling_value(chan);
 741         clrbits_le32(&denali_pi[60], 0x3 << 8);
 742
 743         return 0;
 744 }
 745
 746 static int data_training_rg(const struct chan_info *chan, u32 channel,
 747                             const struct rk3399_sdram_params *params)
 748 {
 749         u32 *denali_pi = chan->pi->denali_pi;
 750         u32 *denali_phy = chan->publ->denali_phy;
 751         u32 i, tmp;
 752         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 753         u32 rank = params->ch[channel].cap_info.rank;
 754
 755         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 756         writel(0x00003f7c, (&denali_pi[175]));
 757
 758         for (i = 0; i < rank; i++) {
 759                 select_per_cs_training_index(chan, i);
 760
 761                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 762                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 763
 764                 /*
 765                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 766                  * PI_RDLVL_CS:RW:24:2
 767                  */
 768                 clrsetbits_le32(&denali_pi[74],
 769                                 (0x1 << 16) | (0x3 << 24),
 770                                 (0x1 << 16) | (i << 24));
 771
 772                 /* Waiting for training complete */
 773                 while (1) {
 774                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 775                         tmp = readl(&denali_pi[174]) >> 8;
 776
 777                         /*
 778                          * check status obs
 779                          * PHY_43/171/299/427
 780                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 781                          */
 782                         obs_0 = readl(&denali_phy[43]);
 783                         obs_1 = readl(&denali_phy[171]);
 784                         obs_2 = readl(&denali_phy[299]);
 785                         obs_3 = readl(&denali_phy[427]);
 786                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 787                             ((obs_1 >> (16 + 6)) & 0x3) ||
 788                             ((obs_2 >> (16 + 6)) & 0x3) ||
 789                             ((obs_3 >> (16 + 6)) & 0x3))
 790                                 obs_err = 1;
 791                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 792                             (((tmp >> 13) & 0x1) == 0x1) &&
 793                             (((tmp >> 3) & 0x1) == 0x0) &&
 794                             obs_err == 0)
 795                                 break;
 796                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 797                                  (obs_err == 1))
 798                                 return -EIO;
 799                 }
 800
 801                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 802                 writel(0x00003f7c, (&denali_pi[175]));
 803         }
 804
 805         clrbits_le32(&denali_pi[80], 0x3 << 24);
 806
 807         return 0;
 808 }
 809
 810 static int data_training_rl(const struct chan_info *chan, u32 channel,
 811                             const struct rk3399_sdram_params *params)
 812 {
 813         u32 *denali_pi = chan->pi->denali_pi;
 814         u32 i, tmp;
 815         u32 rank = params->ch[channel].cap_info.rank;
 816
 817         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 818         writel(0x00003f7c, (&denali_pi[175]));
 819
 820         for (i = 0; i < rank; i++) {
 821                 select_per_cs_training_index(chan, i);
 822
 823                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 824                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 825
 826                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 827                 clrsetbits_le32(&denali_pi[74],
 828                                 (0x1 << 8) | (0x3 << 24),
 829                                 (0x1 << 8) | (i << 24));
 830
 831                 /* Waiting for training complete */
 832                 while (1) {
 833                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 834                         tmp = readl(&denali_pi[174]) >> 8;
 835
 836                         /*
 837                          * make sure status obs not report error bit
 838                          * PHY_46/174/302/430
 839                          *     phy_rdlvl_status_obs_X:16:8
 840                          */
 841                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 842                             (((tmp >> 13) & 0x1) == 0x1) &&
 843                             (((tmp >> 2) & 0x1) == 0x0))
 844                                 break;
 845                         else if (((tmp >> 2) & 0x1) == 0x1)
 846                                 return -EIO;
 847                 }
 848
 849                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 850                 writel(0x00003f7c, (&denali_pi[175]));
 851         }
 852
 853         clrbits_le32(&denali_pi[80], 0x3 << 16);
 854
 855         return 0;
 856 }
 857
 858 static int data_training_wdql(const struct chan_info *chan, u32 channel,
 859                               const struct rk3399_sdram_params *params)
 860 {
 861         u32 *denali_pi = chan->pi->denali_pi;
 862         u32 i, tmp;
 863         u32 rank = params->ch[channel].cap_info.rank;
 864         u32 rank_mask;
 865
 866         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 867         writel(0x00003f7c, (&denali_pi[175]));
 868
 869         rank_mask = (rank == 1) ? 0x1 : 0x3;
 870
 871         for (i = 0; i < 4; i++) {
 872                 if (!(rank_mask & (1 << i)))
 873                         continue;
 874
 875                 select_per_cs_training_index(chan, i);
 876
 877                 /*
 878                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
 879                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
 880                  */
 881                 clrbits_le32(&denali_pi[181], 0x1 << 8);
 882
 883                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
 884                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
 885
 886                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
 887                 clrsetbits_le32(&denali_pi[121],
 888                                 (0x1 << 8) | (0x3 << 16),
 889                                 (0x1 << 8) | (i << 16));
 890
 891                 /* Waiting for training complete */
 892                 while (1) {
 893                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 894                         tmp = readl(&denali_pi[174]) >> 8;
 895                         if ((((tmp >> 12) & 0x1) == 0x1) &&
 896                             (((tmp >> 13) & 0x1) == 0x1) &&
 897                             (((tmp >> 6) & 0x1) == 0x0))
 898                                 break;
 899                         else if (((tmp >> 6) & 0x1) == 0x1)
 900                                 return -EIO;
 901                 }
 902
 903                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 904                 writel(0x00003f7c, (&denali_pi[175]));
 905         }
 906
 907         clrbits_le32(&denali_pi[124], 0x3 << 16);
 908
 909         return 0;
 910 }
 911
 912 static int data_training(const struct chan_info *chan, u32 channel,
 913                          const struct rk3399_sdram_params *params,
 914                          u32 training_flag)
 915 {
 916         u32 *denali_phy = chan->publ->denali_phy;
 917         int ret;
 918
 919         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 920         setbits_le32(&denali_phy[927], (1 << 22));
 921
 922         if (training_flag == PI_FULL_TRAINING) {
 923                 if (params->base.dramtype == LPDDR4) {
 924                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 925                                         PI_READ_GATE_TRAINING |
 926                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
 927                 } else if (params->base.dramtype == LPDDR3) {
 928                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 929                                         PI_READ_GATE_TRAINING;
 930                 } else if (params->base.dramtype == DDR3) {
 931                         training_flag = PI_WRITE_LEVELING |
 932                                         PI_READ_GATE_TRAINING |
 933                                         PI_READ_LEVELING;
 934                 }
 935         }
 936
 937         /* ca training(LPDDR4,LPDDR3 support) */
 938         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
 939                 ret = data_training_ca(chan, channel, params);
 940                 if (ret < 0) {
 941                         debug("%s: data training ca failed\n", __func__);
 942                         return ret;
 943                 }
 944         }
 945
 946         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 947         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
 948                 ret = data_training_wl(chan, channel, params);
 949                 if (ret < 0) {
 950                         debug("%s: data training wl failed\n", __func__);
 951                         return ret;
 952                 }
 953         }
 954
 955         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 956         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
 957                 ret = data_training_rg(chan, channel, params);
 958                 if (ret < 0) {
 959                         debug("%s: data training rg failed\n", __func__);
 960                         return ret;
 961                 }
 962         }
 963
 964         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 965         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
 966                 ret = data_training_rl(chan, channel, params);
 967                 if (ret < 0) {
 968                         debug("%s: data training rl failed\n", __func__);
 969                         return ret;
 970                 }
 971         }
 972
 973         /* wdq leveling(LPDDR4 support) */
 974         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
 975                 ret = data_training_wdql(chan, channel, params);
 976                 if (ret < 0) {
 977                         debug("%s: data training wdql failed\n", __func__);
 978                         return ret;
 979                 }
 980         }
 981
 982         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 983         clrbits_le32(&denali_phy[927], (1 << 22));
 984
 985         return 0;
 986 }
 987
 988 static void set_ddrconfig(const struct chan_info *chan,
 989                           const struct rk3399_sdram_params *params,
 990                           unsigned char channel, u32 ddrconfig)
 991 {
 992         /* only need to set ddrconfig */
 993         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
 994         unsigned int cs0_cap = 0;
 995         unsigned int cs1_cap = 0;
 996
 997         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
 998                         + params->ch[channel].cap_info.col
 999                         + params->ch[channel].cap_info.bk
1000                         + params->ch[channel].cap_info.bw - 20));
1001         if (params->ch[channel].cap_info.rank > 1)
1002                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1003                                 - params->ch[channel].cap_info.cs1_row);
1004         if (params->ch[channel].cap_info.row_3_4) {
1005                 cs0_cap = cs0_cap * 3 / 4;
1006                 cs1_cap = cs1_cap * 3 / 4;
1007         }
1008
1009         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1010         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1011                &ddr_msch_regs->ddrsize);
1012 }
1013
1014 static void dram_all_config(struct dram_info *dram,
1015                             const struct rk3399_sdram_params *params)
1016 {
1017         u32 sys_reg = 0;
1018         unsigned int channel, idx;
1019
1020         sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
1021         sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
1022
1023         for (channel = 0, idx = 0;
1024              (idx < params->base.num_channels) && (channel < 2);
1025              channel++) {
1026                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1027                 struct rk3399_msch_regs *ddr_msch_regs;
1028                 const struct rk3399_msch_timings *noc_timing;
1029
1030                 if (params->ch[channel].cap_info.col == 0)
1031                         continue;
1032                 idx++;
1033                 sys_reg |= info->cap_info.row_3_4 <<
1034                            SYS_REG_ROW_3_4_SHIFT(channel);
1035                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
1036                 sys_reg |= (info->cap_info.rank - 1) <<
1037                            SYS_REG_RANK_SHIFT(channel);
1038                 sys_reg |= (info->cap_info.col - 9) <<
1039                            SYS_REG_COL_SHIFT(channel);
1040                 sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
1041                            SYS_REG_BK_SHIFT(channel);
1042                 sys_reg |= (info->cap_info.cs0_row - 13) <<
1043                             SYS_REG_CS0_ROW_SHIFT(channel);
1044                 sys_reg |= (info->cap_info.cs1_row - 13) <<
1045                             SYS_REG_CS1_ROW_SHIFT(channel);
1046                 sys_reg |= (2 >> info->cap_info.bw) <<
1047                            SYS_REG_BW_SHIFT(channel);
1048                 sys_reg |= (2 >> info->cap_info.dbw) <<
1049                            SYS_REG_DBW_SHIFT(channel);
1050
1051                 ddr_msch_regs = dram->chan[channel].msch;
1052                 noc_timing = &params->ch[channel].noc_timings;
1053                 writel(noc_timing->ddrtiminga0,
1054                        &ddr_msch_regs->ddrtiminga0);
1055                 writel(noc_timing->ddrtimingb0,
1056                        &ddr_msch_regs->ddrtimingb0);
1057                 writel(noc_timing->ddrtimingc0,
1058                        &ddr_msch_regs->ddrtimingc0);
1059                 writel(noc_timing->devtodev0,
1060                        &ddr_msch_regs->devtodev0);
1061                 writel(noc_timing->ddrmode,
1062                        &ddr_msch_regs->ddrmode);
1063
1064                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1065                 if (params->ch[channel].cap_info.rank == 1)
1066                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1067                                      1 << 17);
1068         }
1069
1070         writel(sys_reg, &dram->pmugrf->os_reg2);
1071         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1072                      params->base.stride << 10);
1073
1074         /* reboot hold register set */
1075         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1076                 PRESET_GPIO1_HOLD(1),
1077                 &dram->pmucru->pmucru_rstnhold_con[1]);
1078         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1079 }
1080
1081 static int switch_to_phy_index1(struct dram_info *dram,
1082                                 const struct rk3399_sdram_params *params)
1083 {
1084         u32 channel;
1085         u32 *denali_phy;
1086         u32 ch_count = params->base.num_channels;
1087         int ret;
1088         int i = 0;
1089
1090         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1091                              1 << 4 | 1 << 2 | 1),
1092                         &dram->cic->cic_ctrl0);
1093         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1094                 mdelay(10);
1095                 i++;
1096                 if (i > 10) {
1097                         debug("index1 frequency change overtime\n");
1098                         return -ETIME;
1099                 }
1100         }
1101
1102         i = 0;
1103         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1104         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1105                 mdelay(10);
1106                 i++;
1107                 if (i > 10) {
1108                         debug("index1 frequency done overtime\n");
1109                         return -ETIME;
1110                 }
1111         }
1112
1113         for (channel = 0; channel < ch_count; channel++) {
1114                 denali_phy = dram->chan[channel].publ->denali_phy;
1115                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1116                 ret = data_training(&dram->chan[channel], channel,
1117                                     params, PI_FULL_TRAINING);
1118                 if (ret < 0) {
1119                         debug("index1 training failed\n");
1120                         return ret;
1121                 }
1122         }
1123
1124         return 0;
1125 }
1126
1127 static int sdram_init(struct dram_info *dram,
1128                       const struct rk3399_sdram_params *params)
1129 {
1130         unsigned char dramtype = params->base.dramtype;
1131         unsigned int ddr_freq = params->base.ddr_freq;
1132         int channel;
1133         int ret;
1134
1135         debug("Starting SDRAM initialization...\n");
1136
1137         if ((dramtype == DDR3 && ddr_freq > 933) ||
1138             (dramtype == LPDDR3 && ddr_freq > 933) ||
1139             (dramtype == LPDDR4 && ddr_freq > 800)) {
1140                 debug("SDRAM frequency is to high!");
1141                 return -E2BIG;
1142         }
1143
1144         for (channel = 0; channel < 2; channel++) {
1145                 const struct chan_info *chan = &dram->chan[channel];
1146                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1147
1148                 phy_dll_bypass_set(publ, ddr_freq);
1149
1150                 if (channel >= params->base.num_channels)
1151                         continue;
1152
1153                 ret = pctl_cfg(chan, channel, params);
1154                 if (ret < 0) {
1155                         printf("%s: pctl config failed\n", __func__);
1156                         return ret;
1157                 }
1158
1159                 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1160                 if (dramtype == LPDDR3)
1161                         udelay(10);
1162
1163                 if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
1164                         printf("%s: data training failed\n", __func__);
1165                         return -EIO;
1166                 }
1167
1168                 set_ddrconfig(chan, params, channel,
1169                               params->ch[channel].cap_info.ddrconfig);
1170         }
1171         dram_all_config(dram, params);
1172         switch_to_phy_index1(dram, params);
1173
1174         debug("Finish SDRAM initialization...\n");
1175         return 0;
1176 }
1177
1178 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1179 {
1180 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1181         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1182         int ret;
1183
1184         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1185                                  (u32 *)&plat->sdram_params,
1186                                  sizeof(plat->sdram_params) / sizeof(u32));
1187         if (ret) {
1188                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1189                        __func__, ret);
1190                 return ret;
1191         }
1192         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1193         if (ret)
1194                 printf("%s: regmap failed %d\n", __func__, ret);
1195
1196 #endif
1197         return 0;
1198 }
1199
1200 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1201 static int conv_of_platdata(struct udevice *dev)
1202 {
1203         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1204         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1205         int ret;
1206
1207         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1208                                        ARRAY_SIZE(dtplat->reg) / 2,
1209                                        &plat->map);
1210         if (ret)
1211                 return ret;
1212
1213         return 0;
1214 }
1215 #endif
1216
1217 static int rk3399_dmc_init(struct udevice *dev)
1218 {
1219         struct dram_info *priv = dev_get_priv(dev);
1220         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1221         int ret;
1222 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1223         struct rk3399_sdram_params *params = &plat->sdram_params;
1224 #else
1225         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1226         struct rk3399_sdram_params *params =
1227                                         (void *)dtplat->rockchip_sdram_params;
1228
1229         ret = conv_of_platdata(dev);
1230         if (ret)
1231                 return ret;
1232 #endif
1233
1234         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1235         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1236         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1237         priv->pmucru = rockchip_get_pmucru();
1238         priv->cru = rockchip_get_cru();
1239         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1240         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1241         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1242         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1243         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1244         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1245         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1246         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1247
1248         debug("con reg %p %p %p %p %p %p %p %p\n",
1249               priv->chan[0].pctl, priv->chan[0].pi,
1250               priv->chan[0].publ, priv->chan[0].msch,
1251               priv->chan[1].pctl, priv->chan[1].pi,
1252               priv->chan[1].publ, priv->chan[1].msch);
1253         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1254               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1255
1256 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1257         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1258 #else
1259         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1260 #endif
1261         if (ret) {
1262                 printf("%s clk get failed %d\n", __func__, ret);
1263                 return ret;
1264         }
1265
1266         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1267         if (ret < 0) {
1268                 printf("%s clk set failed %d\n", __func__, ret);
1269                 return ret;
1270         }
1271
1272         ret = sdram_init(priv, params);
1273         if (ret < 0) {
1274                 printf("%s DRAM init failed %d\n", __func__, ret);
1275                 return ret;
1276         }
1277
1278         return 0;
1279 }
1280 #endif
1281
1282 static int rk3399_dmc_probe(struct udevice *dev)
1283 {
1284 #if defined(CONFIG_TPL_BUILD) || \
1285         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1286         if (rk3399_dmc_init(dev))
1287                 return 0;
1288 #else
1289         struct dram_info *priv = dev_get_priv(dev);
1290
1291         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1292         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1293         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1294         priv->info.size =
1295                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1296 #endif
1297         return 0;
1298 }
1299
1300 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1301 {
1302         struct dram_info *priv = dev_get_priv(dev);
1303
1304         *info = priv->info;
1305
1306         return 0;
1307 }
1308
1309 static struct ram_ops rk3399_dmc_ops = {
1310         .get_info = rk3399_dmc_get_info,
1311 };
1312
1313 static const struct udevice_id rk3399_dmc_ids[] = {
1314         { .compatible = "rockchip,rk3399-dmc" },
1315         { }
1316 };
1317
1318 U_BOOT_DRIVER(dmc_rk3399) = {
1319         .name = "rockchip_rk3399_dmc",
1320         .id = UCLASS_RAM,
1321         .of_match = rk3399_dmc_ids,
1322         .ops = &rk3399_dmc_ops,
1323 #if defined(CONFIG_TPL_BUILD) || \
1324         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1325         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1326 #endif
1327         .probe = rk3399_dmc_probe,
1328         .priv_auto_alloc_size = sizeof(struct dram_info),
1329 #if defined(CONFIG_TPL_BUILD) || \
1330         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1331         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1332 #endif
1333 };