1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
7 #include <debug_uart.h>
9 #include <dt-structs.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk3328.h>
16 #include <asm/arch-rockchip/grf_rk3328.h>
17 #include <asm/arch-rockchip/sdram_common.h>
18 #include <asm/arch-rockchip/sdram_rk3328.h>
19 #include <asm/arch-rockchip/uart.h>
22 #ifdef CONFIG_TPL_BUILD
23 struct rk3328_ddr_pctl_regs *pctl;
24 struct rk3328_ddr_phy_regs *phy;
26 struct rk3328_cru *cru;
27 struct rk3328_msch_regs *msch;
28 struct rk3328_ddr_grf_regs *ddr_grf;
31 struct rk3328_grf_regs *grf;
34 #ifdef CONFIG_TPL_BUILD
36 struct rk3328_sdram_channel sdram_ch;
38 struct rockchip_dmc_plat {
39 #if CONFIG_IS_ENABLED(OF_PLATDATA)
40 struct dtd_rockchip_rk3328_dmc dtplat;
42 struct rk3328_sdram_params sdram_params;
47 #if CONFIG_IS_ENABLED(OF_PLATDATA)
48 static int conv_of_platdata(struct udevice *dev)
50 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
51 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
54 ret = regmap_init_mem_platdata(dev, dtplat->reg,
55 ARRAY_SIZE(dtplat->reg) / 2,
64 static void rkclk_ddr_reset(struct dram_info *dram,
65 u32 ctl_srstn, u32 ctl_psrstn,
66 u32 phy_srstn, u32 phy_psrstn)
68 writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
69 ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
70 &dram->cru->softrst_con[5]);
71 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
74 static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz)
76 unsigned int refdiv, postdiv1, postdiv2, fbdiv;
83 } else if (mhz <= 400) {
86 } else if (mhz <= 600) {
89 } else if (mhz <= 800) {
92 } else if (mhz <= 1600) {
99 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
101 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
102 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
103 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
104 &dram->cru->dpll_con[1]);
108 if (LOCK(readl(&dram->cru->dpll_con[1])))
113 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
116 static void rkclk_configure_ddr(struct dram_info *dram,
117 struct rk3328_sdram_params *sdram_params)
119 void __iomem *phy_base = dram->phy;
121 /* choose DPLL for ddr clk source */
122 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
124 /* for inno ddr phy need 2*freq */
125 rkclk_set_dpll(dram, sdram_params->ddr_freq * 2);
128 static void phy_soft_reset(struct dram_info *dram)
130 void __iomem *phy_base = dram->phy;
132 clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
134 setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
136 setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
140 static int pctl_cfg(struct dram_info *dram,
141 struct rk3328_sdram_params *sdram_params)
144 void __iomem *pctl_base = dram->pctl;
146 for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
147 writel(sdram_params->pctl_regs.pctl[i][1],
148 pctl_base + sdram_params->pctl_regs.pctl[i][0]);
150 clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
152 ((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f));
154 * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2
157 if (sdram_params->dramtype == LPDDR3) {
158 setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1);
159 clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0,
163 clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
167 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
168 setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31);
173 /* return ddrconfig value
174 * (-1), find ddrconfig fail
175 * other, the ddrconfig value
176 * only support cs0_row >= cs1_row
178 static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
180 static const u16 ddr_cfg_2_rbc[] = {
181 /***************************
183 * [3] cs(0:0 cs, 1:2 cs)
184 * [2] bank(0:0bank,1:8bank)
186 ****************************/
187 /* row, cs, bank, col */
188 ((3 << 4) | (0 << 3) | (1 << 2) | 0),
189 ((3 << 4) | (0 << 3) | (1 << 2) | 1),
190 ((2 << 4) | (0 << 3) | (1 << 2) | 2),
191 ((3 << 4) | (0 << 3) | (1 << 2) | 2),
192 ((2 << 4) | (0 << 3) | (1 << 2) | 3),
193 ((3 << 4) | (1 << 3) | (1 << 2) | 0),
194 ((3 << 4) | (1 << 3) | (1 << 2) | 1),
195 ((2 << 4) | (1 << 3) | (1 << 2) | 2),
196 ((3 << 4) | (0 << 3) | (0 << 2) | 1),
197 ((2 << 4) | (0 << 3) | (1 << 2) | 1),
200 static const u16 ddr4_cfg_2_rbc[] = {
201 /***************************
202 * [6] cs 0:0cs 1:2 cs
204 * [2] cs(0:0 cs, 1:2 cs)
205 * [1] bw 0: 16bit 1:32bit
206 * [0] diebw 0:8bit 1:16bit
207 ***************************/
208 /* cs, row, cs, bw, diebw */
209 ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
210 ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
211 ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
212 ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
213 ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
214 ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
215 ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
216 ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
217 ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
218 ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
219 ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
222 u32 cs, bw, die_bw, col, row, bank;
228 die_bw = sdram_ch.dbw;
230 row = sdram_ch.cs0_row;
233 if (sdram_params->dramtype == DDR4) {
234 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
235 for (i = 10; i < 17; i++) {
236 if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
237 ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
238 ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
249 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
250 for (i = 0; i < 5; i++)
251 if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
252 ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
260 printf("calculate_ddrconfig error\n");
266 static void copy_to_reg(u32 *dest, u32 *src, u32 n)
270 for (i = 0; i < n / sizeof(u32); i++) {
278 * calculate controller dram address map, and setting to register.
279 * argument sdram_ch.ddrconf must be right value before
280 * call this function.
282 static void set_ctl_address_map(struct dram_info *dram,
283 struct rk3328_sdram_params *sdram_params)
285 void __iomem *pctl_base = dram->pctl;
287 copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
288 &addrmap[sdram_ch.ddrconfig][0], 9 * 4);
289 if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4)
290 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
291 if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1)
292 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
294 if (sdram_ch.rank == 1)
295 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
298 static void phy_dll_bypass_set(struct dram_info *dram, u32 freq)
301 void __iomem *phy_base = dram->phy;
303 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
304 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
305 setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4);
306 clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3);
307 setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4);
308 clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3);
309 setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4);
310 clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3);
311 setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4);
312 clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
314 if (freq <= (400 * MHz))
316 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
318 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
319 if (freq <= (680 * MHz))
323 writel(tmp, PHY_REG(phy_base, 0x28));
324 writel(tmp, PHY_REG(phy_base, 0x38));
325 writel(tmp, PHY_REG(phy_base, 0x48));
326 writel(tmp, PHY_REG(phy_base, 0x58));
329 static void set_ds_odt(struct dram_info *dram,
330 struct rk3328_sdram_params *sdram_params)
332 u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
333 void __iomem *phy_base = dram->phy;
335 if (sdram_params->dramtype == DDR3) {
336 cmd_drv = PHY_DDR3_RON_RTT_34ohm;
337 clk_drv = PHY_DDR3_RON_RTT_45ohm;
338 dqs_drv = PHY_DDR3_RON_RTT_34ohm;
339 dqs_odt = PHY_DDR3_RON_RTT_225ohm;
341 cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
342 clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
343 dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
344 dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
347 writel(cmd_drv, PHY_REG(phy_base, 0x11));
348 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
349 writel(clk_drv, PHY_REG(phy_base, 0x16));
350 writel(clk_drv, PHY_REG(phy_base, 0x18));
351 writel(dqs_drv, PHY_REG(phy_base, 0x20));
352 writel(dqs_drv, PHY_REG(phy_base, 0x2f));
353 writel(dqs_drv, PHY_REG(phy_base, 0x30));
354 writel(dqs_drv, PHY_REG(phy_base, 0x3f));
355 writel(dqs_drv, PHY_REG(phy_base, 0x40));
356 writel(dqs_drv, PHY_REG(phy_base, 0x4f));
357 writel(dqs_drv, PHY_REG(phy_base, 0x50));
358 writel(dqs_drv, PHY_REG(phy_base, 0x5f));
360 writel(dqs_odt, PHY_REG(phy_base, 0x21));
361 writel(dqs_odt, PHY_REG(phy_base, 0x2e));
362 writel(dqs_odt, PHY_REG(phy_base, 0x31));
363 writel(dqs_odt, PHY_REG(phy_base, 0x3e));
364 writel(dqs_odt, PHY_REG(phy_base, 0x41));
365 writel(dqs_odt, PHY_REG(phy_base, 0x4e));
366 writel(dqs_odt, PHY_REG(phy_base, 0x51));
367 writel(dqs_odt, PHY_REG(phy_base, 0x5e));
370 static void phy_cfg(struct dram_info *dram,
371 struct rk3328_sdram_params *sdram_params)
374 void __iomem *phy_base = dram->phy;
376 phy_dll_bypass_set(dram, sdram_params->ddr_freq);
377 for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) {
378 writel(sdram_params->phy_regs.phy[i][1],
379 phy_base + sdram_params->phy_regs.phy[i][0]);
381 if (sdram_ch.bw == 2) {
382 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
384 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
385 /* disable DQS2,DQS3 tx dll for saving power */
386 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
387 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
389 set_ds_odt(dram, sdram_params);
391 setbits_le32(PHY_REG(phy_base, 2), 8);
392 copy_to_reg(PHY_REG(phy_base, 0xb0),
393 &sdram_params->skew.a0_a1_skew[0], 15 * 4);
394 copy_to_reg(PHY_REG(phy_base, 0x70),
395 &sdram_params->skew.cs0_dm0_skew[0], 44 * 4);
396 copy_to_reg(PHY_REG(phy_base, 0xc0),
397 &sdram_params->skew.cs0_dm1_skew[0], 44 * 4);
400 static int update_refresh_reg(struct dram_info *dram)
402 void __iomem *pctl_base = dram->pctl;
405 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
406 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
411 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
415 void __iomem *pctl_base = dram->pctl;
416 void __iomem *phy_base = dram->phy;
419 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
422 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
424 /* disable auto refresh */
425 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
426 update_refresh_reg(dram);
428 if (dramtype == DDR4) {
429 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
430 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
431 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
432 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
434 /* choose training cs */
435 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
436 /* enable gate training */
437 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
439 ret = readl(PHY_REG(phy_base, 0xff));
440 /* disable gate training */
441 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
444 clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
445 /* restore auto refresh */
446 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
447 update_refresh_reg(dram);
449 if (dramtype == DDR4) {
450 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
451 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
452 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
453 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
459 ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
460 ret = (ret == 0) ? 0 : -1;
467 * rank = 3: cs0 & cs1
468 * note: be careful of keep mr original val
470 static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg,
473 void __iomem *pctl_base = dram->pctl;
475 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
477 if (dramtype == DDR3 || dramtype == DDR4) {
478 writel((mr_num << 12) | (rank << 4) | (0 << 0),
479 pctl_base + DDR_PCTL2_MRCTRL0);
480 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
482 writel((rank << 4) | (0 << 0),
483 pctl_base + DDR_PCTL2_MRCTRL0);
484 writel((mr_num << 8) | (arg & 0xff),
485 pctl_base + DDR_PCTL2_MRCTRL1);
488 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
489 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
491 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
498 * rank : 1:cs0, 2:cs1, 3:cs0&cs1
499 * vrefrate: 4500: 45%,
501 static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate,
506 void __iomem *pctl_base = dram->pctl;
508 if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200)
511 tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
512 tccd_l = (tccd_l - 4) << 10;
514 if (vrefrate > 7500) {
516 value = ((vrefrate - 6000) / 65) | tccd_l;
519 value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
523 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
526 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
528 /* disable auto refresh */
529 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
530 update_refresh_reg(dram);
532 /* enable vrefdq calibratin */
533 write_mr(dram, rank, 6, value | (1 << 7), dramtype);
534 udelay(1);/* tvrefdqe */
535 /* write vrefdq value */
536 write_mr(dram, rank, 6, value | (1 << 7), dramtype);
537 udelay(1);/* tvref_time */
538 write_mr(dram, rank, 6, value | (0 << 7), dramtype);
539 udelay(1);/* tvrefdqx */
543 clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
544 /* restore auto refresh */
545 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
546 update_refresh_reg(dram);
551 #define _MAX_(x, y) ((x) > (y) ? (x) : (y))
553 static void rx_deskew_switch_adjust(struct dram_info *dram)
557 void __iomem *phy_base = dram->phy;
559 for (i = 0; i < 4; i++)
560 gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
562 deskew_val = (gate_val >> 3) + 1;
563 deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
564 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
565 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
566 (deskew_val & 0x1c) << 2);
571 static void tx_deskew_switch_adjust(struct dram_info *dram)
573 void __iomem *phy_base = dram->phy;
575 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
578 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
580 writel(ddrconfig, &dram->msch->ddrconf);
583 static void dram_all_config(struct dram_info *dram,
584 struct rk3328_sdram_params *sdram_params)
586 u32 sys_reg = 0, tmp = 0;
588 set_ddrconfig(dram, sdram_ch.ddrconfig);
590 sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
591 sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0);
592 sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0);
593 sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0);
594 sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0);
595 SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0);
596 if (sdram_ch.cs1_row)
597 SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0);
598 sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0);
599 sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0);
601 writel(sys_reg, &dram->grf->os_reg[2]);
603 writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming);
605 writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode);
606 writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency);
608 writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate);
609 writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev);
610 writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing);
611 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0);
612 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1);
613 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2);
614 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3);
615 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4);
616 writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5);
619 static void enable_low_power(struct dram_info *dram,
620 struct rk3328_sdram_params *sdram_params)
622 void __iomem *pctl_base = dram->pctl;
624 /* enable upctl2 axi clock auto gating */
625 writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
626 writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
627 /* enable upctl2 core clock auto gating */
628 writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
631 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
633 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
635 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
637 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
638 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
641 static int sdram_init(struct dram_info *dram,
642 struct rk3328_sdram_params *sdram_params, u32 pre_init)
644 void __iomem *pctl_base = dram->pctl;
646 rkclk_ddr_reset(dram, 1, 1, 1, 1);
649 * dereset ddr phy psrstn to config pll,
650 * if using phy pll psrstn must be dereset
653 rkclk_ddr_reset(dram, 1, 1, 1, 0);
654 rkclk_configure_ddr(dram, sdram_params);
656 switch (sdram_params->dramtype) {
669 /* release phy srst to provide clk to ctrl */
670 rkclk_ddr_reset(dram, 1, 1, 0, 0);
672 phy_soft_reset(dram);
673 /* release ctrl presetn, and config ctl registers */
674 rkclk_ddr_reset(dram, 1, 0, 0, 0);
675 pctl_cfg(dram, sdram_params);
676 sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params);
677 set_ctl_address_map(dram, sdram_params);
678 phy_cfg(dram, sdram_params);
680 /* enable dfi_init_start to init phy after ctl srstn deassert */
681 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
682 rkclk_ddr_reset(dram, 0, 0, 0, 0);
683 /* wait for dfi_init_done and dram init complete */
684 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
687 /* do ddr gate training */
688 if (data_training(dram, 0, sdram_params->dramtype) != 0) {
689 printf("data training error\n");
693 if (sdram_params->dramtype == DDR4)
694 write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype);
697 rx_deskew_switch_adjust(dram);
698 tx_deskew_switch_adjust(dram);
701 dram_all_config(dram, sdram_params);
702 enable_low_power(dram, sdram_params);
707 static u64 dram_detect_cap(struct dram_info *dram,
708 struct rk3328_sdram_params *sdram_params,
709 unsigned char channel)
711 void __iomem *pctl_base = dram->pctl;
714 * for ddr3: ddrconf = 3
715 * for ddr4: ddrconf = 12
716 * for lpddr3: ddrconf = 3
721 u32 row, rowtmp, row_3_4;
722 void __iomem *test_addr, *test_addr1;
727 u32 dram_type = sdram_params->dramtype;
730 if (dram_type != DDR4) {
731 /* detect col and bk for ddr3/lpddr3 */
736 for (col = coltmp; col >= 9; col -= 1) {
737 writel(0, SDRAM_ADDR);
738 test_addr = (void __iomem *)(SDRAM_ADDR +
739 (1ul << (col + bw - 1ul)));
740 writel(PATTERN, test_addr);
741 if ((readl(test_addr) == PATTERN) &&
742 (readl(SDRAM_ADDR) == 0))
746 printf("col error\n");
750 test_addr = (void __iomem *)(SDRAM_ADDR +
751 (1ul << (coltmp + bktmp + bw - 1ul)));
752 writel(0, SDRAM_ADDR);
753 writel(PATTERN, test_addr);
754 if ((readl(test_addr) == PATTERN) &&
755 (readl(SDRAM_ADDR) == 0))
759 if (dram_type == LPDDR3)
764 /* detect bg for ddr4 */
771 test_addr = (void __iomem *)(SDRAM_ADDR +
772 (1ul << (coltmp + bw + 1ul)));
773 writel(0, SDRAM_ADDR);
774 writel(PATTERN, test_addr);
775 if ((readl(test_addr) == PATTERN) &&
776 (readl(SDRAM_ADDR) == 0))
782 for (row = rowtmp; row > 12; row--) {
783 writel(0, SDRAM_ADDR);
784 test_addr = (void __iomem *)(SDRAM_ADDR +
785 (1ul << (row + bktmp + coltmp + bw - 1ul)));
786 writel(PATTERN, test_addr);
787 if ((readl(test_addr) == PATTERN) &&
788 (readl(SDRAM_ADDR) == 0))
796 test_addr = SDRAM_ADDR;
797 test_addr1 = (void __iomem *)(SDRAM_ADDR +
798 (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
800 writel(0, test_addr);
801 writel(PATTERN, test_addr1);
802 if ((readl(test_addr) == 0) &&
803 (readl(test_addr1) == PATTERN))
808 /* disable auto low-power */
809 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
810 writel(0, pctl_base + DDR_PCTL2_PWRCTL);
812 /* bw and cs detect using phy read gate training */
813 if (data_training(dram, 1, dram_type) == 0)
820 /* restore auto low-power */
821 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
823 sdram_ch.rank = cs + 1;
828 sdram_ch.cs0_row = row;
830 sdram_ch.cs1_row = row;
832 sdram_ch.cs1_row = 0;
833 sdram_ch.row_3_4 = row_3_4;
835 if (dram_type == DDR4)
836 cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw);
838 cap = 1llu << (cs + row + bk + col + bw);
846 static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params)
848 u32 tmp = 0, tmp_adr = 0, i;
850 for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
851 if (sdram_params->pctl_regs.pctl[i][0] == 0) {
852 tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */
857 tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
859 switch (sdram_ch.dbw) {
872 if (sdram_ch.rank == 2)
877 tmp |= (2 - sdram_ch.bw) << 12;
879 sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp;
881 if (sdram_ch.bw == 2)
882 sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
884 sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
889 static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params,
890 unsigned char channel)
894 void __iomem *test_addr, *cs1_addr;
895 u32 row, bktmp, coltmp, bw;
896 u32 ddrconf = sdram_ch.ddrconfig;
898 if (sdram_ch.rank == 2) {
899 cs1_bit = addrmap[ddrconf][0] + 8;
904 cs1_addr = (void __iomem *)(1ul << cs1_bit);
910 if (sdram_params->dramtype == DDR4) {
911 if (sdram_ch.dbw == 0)
912 bktmp = sdram_ch.bk + 2;
914 bktmp = sdram_ch.bk + 1;
919 coltmp = sdram_ch.col;
922 for (row = sdram_ch.cs0_row; row > 12; row--) {
923 test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr +
924 (1ul << (row + cs1_bit + bktmp +
925 coltmp + bw - 1ul)));
926 writel(0, SDRAM_ADDR + cs1_addr);
927 writel(PATTERN, test_addr);
928 if ((readl(test_addr) == PATTERN) &&
929 (readl(SDRAM_ADDR + cs1_addr) == 0)) {
940 static int sdram_init_detect(struct dram_info *dram,
941 struct rk3328_sdram_params *sdram_params)
943 debug("Starting SDRAM initialization...\n");
945 memcpy(&sdram_ch, &sdram_params->ch,
946 sizeof(struct rk3328_sdram_channel));
948 sdram_init(dram, sdram_params, 1);
949 dram_detect_cap(dram, sdram_params, 0);
951 /* modify bw, cs related timing */
952 remodify_sdram_params(sdram_params);
953 /* reinit sdram by real dram cap */
954 sdram_init(dram, sdram_params, 0);
956 /* redetect cs1 row */
958 dram_detect_cs1_row(sdram_params, 0);
963 static int rk3328_dmc_init(struct udevice *dev)
965 struct dram_info *priv = dev_get_priv(dev);
966 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
969 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
970 struct rk3328_sdram_params *params = &plat->sdram_params;
972 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
973 struct rk3328_sdram_params *params =
974 (void *)dtplat->rockchip_sdram_params;
976 ret = conv_of_platdata(dev);
980 priv->phy = regmap_get_range(plat->map, 0);
981 priv->pctl = regmap_get_range(plat->map, 1);
982 priv->grf = regmap_get_range(plat->map, 2);
983 priv->cru = regmap_get_range(plat->map, 3);
984 priv->msch = regmap_get_range(plat->map, 4);
985 priv->ddr_grf = regmap_get_range(plat->map, 5);
987 debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
988 __func__, priv->phy, priv->pctl, priv->grf, priv->cru,
989 priv->msch, priv->ddr_grf);
990 ret = sdram_init_detect(priv, params);
992 printf("%s DRAM init failed%d\n", __func__, ret);
999 static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
1001 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1002 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1005 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1006 (u32 *)&plat->sdram_params,
1007 sizeof(plat->sdram_params) / sizeof(u32));
1009 printf("%s: Cannot read rockchip,sdram-params %d\n",
1013 ret = regmap_init_mem(dev, &plat->map);
1015 printf("%s: regmap failed %d\n", __func__, ret);
1022 static int rk3328_dmc_probe(struct udevice *dev)
1024 #ifdef CONFIG_TPL_BUILD
1025 if (rk3328_dmc_init(dev))
1028 struct dram_info *priv = dev_get_priv(dev);
1030 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1031 debug("%s: grf=%p\n", __func__, priv->grf);
1032 priv->info.base = CONFIG_SYS_SDRAM_BASE;
1033 priv->info.size = rockchip_sdram_size(
1034 (phys_addr_t)&priv->grf->os_reg[2]);
1039 static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
1041 struct dram_info *priv = dev_get_priv(dev);
1048 static struct ram_ops rk3328_dmc_ops = {
1049 .get_info = rk3328_dmc_get_info,
1052 static const struct udevice_id rk3328_dmc_ids[] = {
1053 { .compatible = "rockchip,rk3328-dmc" },
1057 U_BOOT_DRIVER(dmc_rk3328) = {
1058 .name = "rockchip_rk3328_dmc",
1060 .of_match = rk3328_dmc_ids,
1061 .ops = &rk3328_dmc_ops,
1062 #ifdef CONFIG_TPL_BUILD
1063 .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
1065 .probe = rk3328_dmc_probe,
1066 .priv_auto_alloc_size = sizeof(struct dram_info),
1067 #ifdef CONFIG_TPL_BUILD
1068 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),