1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
6 * Adapted from coreboot.
12 #include <dt-structs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/cru_rk3288.h>
20 #include <asm/arch/ddr_rk3288.h>
21 #include <asm/arch/grf_rk3288.h>
22 #include <asm/arch/pmu_rk3288.h>
23 #include <asm/arch/sdram.h>
24 #include <asm/arch/sdram_common.h>
25 #include <linux/err.h>
26 #include <power/regulator.h>
27 #include <power/rk8xx_pmic.h>
30 struct rk3288_ddr_pctl *pctl;
31 struct rk3288_ddr_publ *publ;
32 struct rk3288_msch *msch;
36 struct chan_info chan[2];
39 struct rk3288_cru *cru;
40 struct rk3288_grf *grf;
41 struct rk3288_sgrf *sgrf;
42 struct rk3288_pmu *pmu;
46 struct rk3288_sdram_params {
47 #if CONFIG_IS_ENABLED(OF_PLATDATA)
48 struct dtd_rockchip_rk3288_dmc of_plat;
50 struct rk3288_sdram_channel ch[2];
51 struct rk3288_sdram_pctl_timing pctl_timing;
52 struct rk3288_sdram_phy_timing phy_timing;
53 struct rk3288_base_params base;
58 const int ddrconf_table[] = {
61 ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
62 ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
63 ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
64 ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
65 ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
66 ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
67 ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
68 ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
69 ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
70 ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
78 #define TEST_PATTEN 0x5aa5f00f
79 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
80 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
82 #ifdef CONFIG_SPL_BUILD
83 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
87 for (i = 0; i < n / sizeof(u32); i++) {
94 static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
96 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
97 u32 ctl_psrstn_shift = 3 + 5 * ch;
98 u32 ctl_srstn_shift = 2 + 5 * ch;
99 u32 phy_psrstn_shift = 1 + 5 * ch;
100 u32 phy_srstn_shift = 5 * ch;
102 rk_clrsetreg(&cru->cru_softrst_con[10],
103 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
104 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
105 1 << phy_srstn_shift,
106 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
107 ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
108 phy << phy_srstn_shift);
111 static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
113 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
115 rk_clrsetreg(&cru->cru_softrst_con[10],
116 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
119 static void phy_pctrl_reset(struct rk3288_cru *cru,
120 struct rk3288_ddr_publ *publ,
125 ddr_reset(cru, channel, 1, 1);
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
128 for (i = 0; i < 4; i++)
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
133 for (i = 0; i < 4; i++)
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
137 ddr_reset(cru, channel, 1, 0);
139 ddr_reset(cru, channel, 0, 0);
143 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
148 if (freq <= 250000000) {
149 if (freq <= 150000000)
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
152 setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
153 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
154 for (i = 0; i < 4; i++)
155 setbits_le32(&publ->datx8[i].dxdllcr,
158 setbits_le32(&publ->pir, PIR_DLLBYP);
160 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
161 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
162 for (i = 0; i < 4; i++) {
163 clrbits_le32(&publ->datx8[i].dxdllcr,
167 clrbits_le32(&publ->pir, PIR_DLLBYP);
171 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
173 writel(DFI_INIT_START, &pctl->dfistcfg0);
174 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
176 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
177 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
180 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
181 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
182 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
183 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
184 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
185 writel(1, &pctl->dfitphyupdtype0);
187 /* cs0 and cs1 write odt enable */
188 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
190 /* odt write length */
191 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
192 /* phyupd and ctrlupd disabled */
193 writel(0, &pctl->dfiupdcfg);
196 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable)
201 val = 1 << (channel ? DDR1_16BIT_EN_SHIFT :
202 DDR0_16BIT_EN_SHIFT);
204 rk_clrsetreg(&grf->soc_con0,
205 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT),
209 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel,
214 mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT);
215 val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT :
216 MSCH0_MAINDDR3_SHIFT);
217 rk_clrsetreg(&grf->soc_con0, mask, val);
220 static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
221 bool enable, bool enable_bst, bool enable_odt)
224 bool disable_bst = !enable_bst;
227 (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT |
228 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) :
229 (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT |
230 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT);
231 rk_clrsetreg(&grf->soc_con2, mask,
232 enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) |
233 disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT :
234 UPCTL0_BST_DIABLE_SHIFT) |
235 enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT :
236 UPCTL0_LPDDR3_ODT_EN_SHIFT));
239 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
240 struct rk3288_sdram_params *sdram_params,
241 struct rk3288_grf *grf)
243 unsigned int burstlen;
245 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;
246 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
247 sizeof(sdram_params->pctl_timing));
248 switch (sdram_params->base.dramtype) {
250 writel(sdram_params->pctl_timing.tcl - 1,
251 &pctl->dfitrddataen);
252 writel(sdram_params->pctl_timing.tcwl,
253 &pctl->dfitphywrlat);
255 writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
256 LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT |
257 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
258 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
260 ddr_set_ddr3_mode(grf, channel, false);
261 ddr_set_enable(grf, channel, true);
262 ddr_set_en_bst_odt(grf, channel, true, false,
263 sdram_params->base.odt);
266 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
267 writel(sdram_params->pctl_timing.tcl - 3,
268 &pctl->dfitrddataen);
270 writel(sdram_params->pctl_timing.tcl - 2,
271 &pctl->dfitrddataen);
273 writel(sdram_params->pctl_timing.tcwl - 1,
274 &pctl->dfitphywrlat);
275 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
276 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
277 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
279 ddr_set_ddr3_mode(grf, channel, true);
280 ddr_set_enable(grf, channel, true);
282 ddr_set_en_bst_odt(grf, channel, false, true, false);
286 setbits_le32(&pctl->scfg, 1);
289 static void phy_cfg(const struct chan_info *chan, int channel,
290 struct rk3288_sdram_params *sdram_params)
292 struct rk3288_ddr_publ *publ = chan->publ;
293 struct rk3288_msch *msch = chan->msch;
294 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
298 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
301 sizeof(sdram_params->phy_timing));
302 writel(sdram_params->base.noc_timing, &msch->ddrtiming);
303 writel(0x3f, &msch->readlatency);
304 writel(sdram_params->base.noc_activate, &msch->activate);
305 writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT |
306 1 << BUSRDTORD_SHIFT, &msch->devtodev);
307 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
308 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
309 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
310 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
311 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
313 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
314 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
317 switch (sdram_params->base.dramtype) {
319 clrsetbits_le32(&publ->pgcr, 0x1F,
320 0 << PGCR_DFTLMT_SHIFT |
321 0 << PGCR_DFTCMP_SHIFT |
322 1 << PGCR_DQSCFG_SHIFT |
323 0 << PGCR_ITMDMD_SHIFT);
324 /* DDRMODE select LPDDR3 */
325 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
326 DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT);
327 clrsetbits_le32(&publ->dxccr,
328 DQSNRES_MASK << DQSNRES_SHIFT |
329 DQSRES_MASK << DQSRES_SHIFT,
330 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT);
331 tmp = readl(&publ->dtpr[1]);
332 tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) -
333 ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK);
334 clrsetbits_le32(&publ->dsgcr,
335 DQSGE_MASK << DQSGE_SHIFT |
336 DQSGX_MASK << DQSGX_SHIFT,
337 tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT);
340 clrbits_le32(&publ->pgcr, 0x1f);
341 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
342 DDRMD_DDR3 << DDRMD_SHIFT);
345 if (sdram_params->base.odt) {
346 /*dynamic RTT enable */
347 for (i = 0; i < 4; i++)
348 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
350 /*dynamic RTT disable */
351 for (i = 0; i < 4; i++)
352 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
356 static void phy_init(struct rk3288_ddr_publ *publ)
358 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
359 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
361 while ((readl(&publ->pgsr) &
362 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
363 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
367 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
370 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
372 while (readl(&pctl->mcmd) & START_CMD)
376 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
377 u32 rank, u32 cmd, u32 ma, u32 op)
379 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
380 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
383 static void memory_init(struct rk3288_ddr_publ *publ,
386 setbits_le32(&publ->pir,
387 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
388 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
389 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
391 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
392 != (PGSR_IDONE | PGSR_DLDONE))
396 static void move_to_config_state(struct rk3288_ddr_publ *publ,
397 struct rk3288_ddr_pctl *pctl)
402 state = readl(&pctl->stat) & PCTL_STAT_MSK;
406 writel(WAKEUP_STATE, &pctl->sctl);
407 while ((readl(&pctl->stat) & PCTL_STAT_MSK)
411 while ((readl(&publ->pgsr) & PGSR_DLDONE)
415 * if at low power state,need wakeup first,
416 * and then enter the config
422 writel(CFG_STATE, &pctl->sctl);
423 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
434 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
435 u32 n, struct rk3288_grf *grf)
437 struct rk3288_ddr_pctl *pctl = chan->pctl;
438 struct rk3288_ddr_publ *publ = chan->publ;
439 struct rk3288_msch *msch = chan->msch;
442 setbits_le32(&pctl->ppcfg, 1);
443 rk_setreg(&grf->soc_con0, 1 << (8 + channel));
444 setbits_le32(&msch->ddrtiming, 1 << 31);
445 /* Data Byte disable*/
446 clrbits_le32(&publ->datx8[2].dxgcr, 1);
447 clrbits_le32(&publ->datx8[3].dxgcr, 1);
449 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
450 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
452 clrbits_le32(&pctl->ppcfg, 1);
453 rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
454 clrbits_le32(&msch->ddrtiming, 1 << 31);
455 /* Data Byte enable*/
456 setbits_le32(&publ->datx8[2].dxgcr, 1);
457 setbits_le32(&publ->datx8[3].dxgcr, 1);
460 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
461 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
463 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
464 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
466 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
467 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
469 setbits_le32(&pctl->dfistcfg0, 1 << 2);
472 static int data_training(const struct chan_info *chan, int channel,
473 struct rk3288_sdram_params *sdram_params)
479 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
480 struct rk3288_ddr_publ *publ = chan->publ;
481 struct rk3288_ddr_pctl *pctl = chan->pctl;
483 /* disable auto refresh */
484 writel(0, &pctl->trefi);
486 if (sdram_params->base.dramtype != LPDDR3)
487 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
488 rank = sdram_params->ch[channel].rank | 1;
489 for (j = 0; j < ARRAY_SIZE(step); j++) {
491 * trigger QSTRN and RVTRN
492 * clear DTDONE status
494 setbits_le32(&publ->pir, PIR_CLRSR);
497 setbits_le32(&publ->pir,
498 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
501 /* wait echo byte DTDONE */
502 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
505 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
508 if (!(readl(&pctl->ppcfg) & 1)) {
509 while ((readl(&publ->datx8[2].dxgsr[0])
512 while ((readl(&publ->datx8[3].dxgsr[0])
516 if (readl(&publ->pgsr) &
517 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
522 /* send some auto refresh to complement the lost while DTT */
523 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
524 send_command(pctl, rank, REF_CMD, 0);
526 if (sdram_params->base.dramtype != LPDDR3)
527 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
529 /* resume auto refresh */
530 writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
535 static void move_to_access_state(const struct chan_info *chan)
537 struct rk3288_ddr_publ *publ = chan->publ;
538 struct rk3288_ddr_pctl *pctl = chan->pctl;
542 state = readl(&pctl->stat) & PCTL_STAT_MSK;
546 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
550 writel(WAKEUP_STATE, &pctl->sctl);
551 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
554 while ((readl(&publ->pgsr) & PGSR_DLDONE)
559 writel(CFG_STATE, &pctl->sctl);
560 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
563 writel(GO_STATE, &pctl->sctl);
564 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
575 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
576 struct rk3288_sdram_params *sdram_params)
578 struct rk3288_ddr_publ *publ = chan->publ;
580 if (sdram_params->ch[chnum].bk == 3)
581 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
584 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
586 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
589 static void dram_all_config(const struct dram_info *dram,
590 struct rk3288_sdram_params *sdram_params)
595 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
596 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
597 for (chan = 0; chan < sdram_params->num_channels; chan++) {
598 const struct rk3288_sdram_channel *info =
599 &sdram_params->ch[chan];
601 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
602 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
603 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
604 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
605 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
606 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
607 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
608 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
609 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
611 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
613 writel(sys_reg, &dram->pmu->sys_reg[2]);
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
617 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
618 struct rk3288_sdram_params *sdram_params)
621 int need_trainig = 0;
622 const struct chan_info *chan = &dram->chan[channel];
623 struct rk3288_ddr_publ *publ = chan->publ;
625 if (data_training(chan, channel, sdram_params) < 0) {
626 reg = readl(&publ->datx8[0].dxgsr[0]);
627 /* Check the result for rank 0 */
628 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
629 debug("data training fail!\n");
631 } else if ((channel == 1) &&
632 (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
633 sdram_params->num_channels = 1;
636 /* Check the result for rank 1 */
637 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
638 sdram_params->ch[channel].rank = 1;
639 clrsetbits_le32(&publ->pgcr, 0xF << 18,
640 sdram_params->ch[channel].rank << 18);
643 reg = readl(&publ->datx8[2].dxgsr[0]);
644 if (reg & (1 << 4)) {
645 sdram_params->ch[channel].bw = 1;
646 set_bandwidth_ratio(chan, channel,
647 sdram_params->ch[channel].bw,
652 /* Assume the Die bit width are the same with the chip bit width */
653 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
656 (data_training(chan, channel, sdram_params) < 0)) {
657 if (sdram_params->base.dramtype == LPDDR3) {
658 ddr_phy_ctl_reset(dram->cru, channel, 1);
660 ddr_phy_ctl_reset(dram->cru, channel, 0);
663 debug("2nd data training failed!");
670 static int sdram_col_row_detect(struct dram_info *dram, int channel,
671 struct rk3288_sdram_params *sdram_params)
675 const struct chan_info *chan = &dram->chan[channel];
676 struct rk3288_ddr_pctl *pctl = chan->pctl;
677 struct rk3288_ddr_publ *publ = chan->publ;
681 for (col = 11; col >= 9; col--) {
682 writel(0, CONFIG_SYS_SDRAM_BASE);
683 addr = CONFIG_SYS_SDRAM_BASE +
684 (1 << (col + sdram_params->ch[channel].bw - 1));
685 writel(TEST_PATTEN, addr);
686 if ((readl(addr) == TEST_PATTEN) &&
687 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
691 printf("Col detect error\n");
695 sdram_params->ch[channel].col = col;
698 move_to_config_state(publ, pctl);
699 writel(4, &chan->msch->ddrconf);
700 move_to_access_state(chan);
702 for (row = 16; row >= 12; row--) {
703 writel(0, CONFIG_SYS_SDRAM_BASE);
704 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
705 writel(TEST_PATTEN, addr);
706 if ((readl(addr) == TEST_PATTEN) &&
707 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
711 printf("Row detect error\n");
714 sdram_params->ch[channel].cs1_row = row;
715 sdram_params->ch[channel].row_3_4 = 0;
716 debug("chn %d col %d, row %d\n", channel, col, row);
717 sdram_params->ch[channel].cs0_row = row;
724 static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
726 int i, tmp, size, ret = 0;
728 tmp = sdram_params->ch[0].col - 9;
729 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
730 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
731 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
732 for (i = 0; i < size; i++)
733 if (tmp == ddrconf_table[i])
736 printf("niu config not found\n");
739 sdram_params->base.ddrconfig = i;
745 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
749 long cap = sdram_params->num_channels * (1u <<
750 (sdram_params->ch[0].cs0_row +
751 sdram_params->ch[0].col +
752 (sdram_params->ch[0].rank - 1) +
753 sdram_params->ch[0].bw +
771 printf("could not find correct stride, cap error!\n");
775 sdram_params->base.stride = stride;
780 static int sdram_init(struct dram_info *dram,
781 struct rk3288_sdram_params *sdram_params)
787 debug("%s start\n", __func__);
788 if ((sdram_params->base.dramtype == DDR3 &&
789 sdram_params->base.ddr_freq > 800000000) ||
790 (sdram_params->base.dramtype == LPDDR3 &&
791 sdram_params->base.ddr_freq > 533000000)) {
792 debug("SDRAM frequency is too high!");
796 debug("ddr clk dpll\n");
797 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
798 debug("ret=%d\n", ret);
800 debug("Could not set DDR clock\n");
804 for (channel = 0; channel < 2; channel++) {
805 const struct chan_info *chan = &dram->chan[channel];
806 struct rk3288_ddr_pctl *pctl = chan->pctl;
807 struct rk3288_ddr_publ *publ = chan->publ;
809 /* map all the 4GB space to the current channel */
811 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
813 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
814 phy_pctrl_reset(dram->cru, publ, channel);
815 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
817 dfi_cfg(pctl, sdram_params->base.dramtype);
819 pctl_cfg(channel, pctl, sdram_params, dram->grf);
821 phy_cfg(chan, channel, sdram_params);
825 writel(POWER_UP_START, &pctl->powctl);
826 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
829 memory_init(publ, sdram_params->base.dramtype);
830 move_to_config_state(publ, pctl);
832 if (sdram_params->base.dramtype == LPDDR3) {
833 send_command(pctl, 3, DESELECT_CMD, 0);
835 send_command(pctl, 3, PREA_CMD, 0);
837 send_command_op(pctl, 3, MRS_CMD, 63, 0xfc);
839 send_command_op(pctl, 3, MRS_CMD, 1,
840 sdram_params->phy_timing.mr[1]);
842 send_command_op(pctl, 3, MRS_CMD, 2,
843 sdram_params->phy_timing.mr[2]);
845 send_command_op(pctl, 3, MRS_CMD, 3,
846 sdram_params->phy_timing.mr[3]);
850 /* Using 32bit bus width for detect */
851 sdram_params->ch[channel].bw = 2;
852 set_bandwidth_ratio(chan, channel,
853 sdram_params->ch[channel].bw, dram->grf);
855 * set cs, using n=3 for detect
860 sdram_params->ch[channel].rank = 2,
861 clrsetbits_le32(&publ->pgcr, 0xF << 18,
862 (sdram_params->ch[channel].rank | 1) << 18);
864 /* DS=40ohm,ODT=155ohm */
865 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
866 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
867 0x19 << PD_OUTPUT_SHIFT;
868 writel(zqcr, &publ->zq1cr[0]);
869 writel(zqcr, &publ->zq0cr[0]);
871 if (sdram_params->base.dramtype == LPDDR3) {
872 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
874 send_command_op(pctl,
875 sdram_params->ch[channel].rank | 1,
877 sdram_params->base.odt ? 3 : 0);
879 writel(0, &pctl->mrrcfg0);
880 send_command_op(pctl, 1, MRR_CMD, 8, 0);
882 if ((readl(&pctl->mrrstat0) & 0x3) != 3) {
889 /* Detect the rank and bit-width with data-training */
890 sdram_rank_bw_detect(dram, channel, sdram_params);
892 if (sdram_params->base.dramtype == LPDDR3) {
894 writel(0, &pctl->mrrcfg0);
895 for (i = 0; i < 17; i++)
896 send_command_op(pctl, 1, MRR_CMD, i, 0);
898 writel(15, &chan->msch->ddrconf);
899 move_to_access_state(chan);
900 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
901 sdram_params->ch[channel].bk = 3;
902 /* Detect Col and Row number*/
903 ret = sdram_col_row_detect(dram, channel, sdram_params);
907 /* Find NIU DDR configuration */
908 ret = sdram_get_niu_config(sdram_params);
911 /* Find stride setting */
912 ret = sdram_get_stride(sdram_params);
916 dram_all_config(dram, sdram_params);
917 debug("%s done\n", __func__);
921 printf("DRAM init failed!\n");
925 # ifdef CONFIG_ROCKCHIP_FAST_SPL
926 static int veyron_init(struct dram_info *priv)
928 struct udevice *pmic;
931 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
935 /* Slowly raise to max CPU voltage to prevent overshoot */
936 ret = rk8xx_spl_configure_buck(pmic, 1, 1200000);
939 udelay(175);/* Must wait for voltage to stabilize, 2mV/us */
940 ret = rk8xx_spl_configure_buck(pmic, 1, 1400000);
943 udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
945 rk3288_clk_configure_cpu(priv->cru, priv->grf);
951 static int setup_sdram(struct udevice *dev)
953 struct dram_info *priv = dev_get_priv(dev);
954 struct rk3288_sdram_params *params = dev_get_platdata(dev);
956 # ifdef CONFIG_ROCKCHIP_FAST_SPL
957 if (priv->is_veyron) {
960 ret = veyron_init(priv);
966 return sdram_init(priv, params);
969 static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
971 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
972 struct rk3288_sdram_params *params = dev_get_platdata(dev);
975 /* Rk3288 supports dual-channel, set default channel num to 2 */
976 params->num_channels = 2;
977 ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
978 (u32 *)¶ms->pctl_timing,
979 sizeof(params->pctl_timing) / sizeof(u32));
981 debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
984 ret = dev_read_u32_array(dev, "rockchip,phy-timing",
985 (u32 *)¶ms->phy_timing,
986 sizeof(params->phy_timing) / sizeof(u32));
988 debug("%s: Cannot read rockchip,phy-timing\n", __func__);
991 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
992 (u32 *)¶ms->base,
993 sizeof(params->base) / sizeof(u32));
995 debug("%s: Cannot read rockchip,sdram-params\n", __func__);
998 #ifdef CONFIG_ROCKCHIP_FAST_SPL
999 struct dram_info *priv = dev_get_priv(dev);
1001 priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
1003 ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
1010 #endif /* CONFIG_SPL_BUILD */
1012 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1013 static int conv_of_platdata(struct udevice *dev)
1015 struct rk3288_sdram_params *plat = dev_get_platdata(dev);
1016 struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
1019 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
1020 sizeof(plat->pctl_timing));
1021 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
1022 sizeof(plat->phy_timing));
1023 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
1024 /* Rk3288 supports dual-channel, set default channel num to 2 */
1025 plat->num_channels = 2;
1026 ret = regmap_init_mem_platdata(dev, of_plat->reg,
1027 ARRAY_SIZE(of_plat->reg) / 2,
1036 static int rk3288_dmc_probe(struct udevice *dev)
1038 #ifdef CONFIG_SPL_BUILD
1039 struct rk3288_sdram_params *plat = dev_get_platdata(dev);
1040 struct udevice *dev_clk;
1044 struct dram_info *priv = dev_get_priv(dev);
1046 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
1047 #ifdef CONFIG_SPL_BUILD
1048 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1049 ret = conv_of_platdata(dev);
1053 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
1055 return PTR_ERR(map);
1056 priv->chan[0].msch = regmap_get_range(map, 0);
1057 priv->chan[1].msch = (struct rk3288_msch *)
1058 (regmap_get_range(map, 0) + 0x80);
1060 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1061 priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
1063 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1064 priv->chan[0].publ = regmap_get_range(plat->map, 1);
1065 priv->chan[1].pctl = regmap_get_range(plat->map, 2);
1066 priv->chan[1].publ = regmap_get_range(plat->map, 3);
1068 ret = rockchip_get_clk(&dev_clk);
1071 priv->ddr_clk.id = CLK_DDR;
1072 ret = clk_request(dev_clk, &priv->ddr_clk);
1076 priv->cru = rockchip_get_cru();
1077 if (IS_ERR(priv->cru))
1078 return PTR_ERR(priv->cru);
1079 ret = setup_sdram(dev);
1083 priv->info.base = CONFIG_SYS_SDRAM_BASE;
1084 priv->info.size = rockchip_sdram_size(
1085 (phys_addr_t)&priv->pmu->sys_reg[2]);
1091 static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info)
1093 struct dram_info *priv = dev_get_priv(dev);
1100 static struct ram_ops rk3288_dmc_ops = {
1101 .get_info = rk3288_dmc_get_info,
1104 static const struct udevice_id rk3288_dmc_ids[] = {
1105 { .compatible = "rockchip,rk3288-dmc" },
1109 U_BOOT_DRIVER(dmc_rk3288) = {
1110 .name = "rockchip_rk3288_dmc",
1112 .of_match = rk3288_dmc_ids,
1113 .ops = &rk3288_dmc_ops,
1114 #ifdef CONFIG_SPL_BUILD
1115 .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
1117 .probe = rk3288_dmc_probe,
1118 .priv_auto_alloc_size = sizeof(struct dram_info),
1119 #ifdef CONFIG_SPL_BUILD
1120 .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),