drivers/ram/rockchip/sdram_debug.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  * (C) Copyright 2019 Amarula Solutions.
   5  * Author: Jagan Teki <jagan@amarulasolutions.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <asm/arch-rockchip/sdram_common.h>
  11
  12 void sdram_print_dram_type(unsigned char dramtype)
  13 {
  14         switch (dramtype) {
  15         case DDR3:
  16                 printascii("DDR3");
  17                 break;
  18         case DDR4:
  19                 printascii("DDR4");
  20                 break;
  21         case LPDDR2:
  22                 printascii("LPDDR2");
  23                 break;
  24         case LPDDR3:
  25                 printascii("LPDDR3");
  26                 break;
  27         case LPDDR4:
  28                 printascii("LPDDR4");
  29                 break;
  30         default:
  31                 printascii("Unknown Device");
  32                 break;
  33         }
  34 }
  35
  36 /**
  37  * cs  = 0, cs0
  38  * cs  = 1, cs1
  39  * cs => 2, cs0+cs1
  40  * note: it didn't consider about row_3_4
  41  */
  42 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
  43 {
  44         u32 bg;
  45         u64 cap[2];
  46
  47         if (dram_type == DDR4)
  48                 /* DDR4 8bit dram BG = 2(4bank groups),
  49                  * 16bit dram BG = 1 (2 bank groups)
  50                  */
  51                 bg = (cap_info->dbw == 0) ? 2 : 1;
  52         else
  53                 bg = 0;
  54
  55         cap[0] = 1llu << (cap_info->bw + cap_info->col +
  56                  bg + cap_info->bk + cap_info->cs0_row);
  57
  58         if (cap_info->rank == 2)
  59                 cap[1] = 1llu << (cap_info->bw + cap_info->col +
  60                          bg + cap_info->bk + cap_info->cs1_row);
  61         else
  62                 cap[1] = 0;
  63
  64         if (cs == 0)
  65                 return cap[0];
  66         else if (cs == 1)
  67                 return cap[1];
  68         else
  69                 return (cap[0] + cap[1]);
  70 }
  71
  72 void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
  73                           struct sdram_base_params *base)
  74 {
  75         u32 bg, cap;
  76
  77         bg = (cap_info->dbw == 0) ? 2 : 1;
  78
  79         sdram_print_dram_type(base->dramtype);
  80
  81         printascii(", ");
  82         printdec(base->ddr_freq);
  83         printascii("MHz\n");
  84
  85         printascii("BW=");
  86         printdec(8 << cap_info->bw);
  87
  88         printascii(" Col=");
  89         printdec(cap_info->col);
  90
  91         printascii(" Bk=");
  92         printdec(0x1 << cap_info->bk);
  93         if (base->dramtype == DDR4) {
  94                 printascii(" BG=");
  95                 printdec(1 << bg);
  96         }
  97
  98         printascii(" CS0 Row=");
  99         printdec(cap_info->cs0_row);
 100         if (cap_info->rank > 1) {
 101                 printascii(" CS1 Row=");
 102                 printdec(cap_info->cs1_row);
 103         }
 104
 105         printascii(" CS=");
 106         printdec(cap_info->rank);
 107
 108         printascii(" Die BW=");
 109         printdec(8 << cap_info->dbw);
 110
 111         cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
 112         if (cap_info->row_3_4)
 113                 cap = cap * 3 / 4;
 114
 115         printascii(" Size=");
 116         printdec(cap >> 20);
 117         printascii("MB\n");
 118 }
 119
 120 void sdram_print_stride(unsigned int stride)
 121 {
 122         switch (stride) {
 123         case 0xc:
 124                 printf("128B stride\n");
 125                 break;
 126         case 5:
 127         case 9:
 128         case 0xd:
 129         case 0x11:
 130         case 0x19:
 131                 printf("256B stride\n");
 132                 break;
 133         case 0xa:
 134         case 0xe:
 135         case 0x12:
 136                 printf("512B stride\n");
 137                 break;
 138         case 0xf:
 139                 printf("4K stride\n");
 140                 break;
 141         case 0x1f:
 142                 printf("32MB + 256B stride\n");
 143                 break;
 144         default:
 145                 printf("no stride\n");
 146         }
 147 }