1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
7 #include <debug_uart.h>
10 #include <asm/arch-rockchip/sdram.h>
11 #include <asm/arch-rockchip/sdram_common.h>
13 #ifdef CONFIG_RAM_ROCKCHIP_DEBUG
14 void sdram_print_dram_type(unsigned char dramtype)
33 printascii("Unknown Device");
38 void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
39 struct sdram_base_params *base)
44 bg = (cap_info->dbw == 0) ? 2 : 1;
46 sdram_print_dram_type(base->dramtype);
49 printdec(base->ddr_freq);
53 printdec(8 << cap_info->bw);
55 printdec(cap_info->col);
57 printdec(0x1 << cap_info->bk);
58 if (base->dramtype == DDR4) {
62 printascii(" CS0 Row=");
63 printdec(cap_info->cs0_row);
64 if (cap_info->cs0_high16bit_row !=
67 printdec(cap_info->cs0_high16bit_row);
69 if (cap_info->rank > 1) {
70 printascii(" CS1 Row=");
71 printdec(cap_info->cs1_row);
72 if (cap_info->cs1_high16bit_row !=
75 printdec(cap_info->cs1_high16bit_row);
79 printdec(cap_info->rank);
80 printascii(" Die BW=");
81 printdec(8 << cap_info->dbw);
83 cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
84 if (cap_info->row_3_4)
92 void sdram_print_stride(unsigned int stride)
96 printf("128B stride\n");
103 printf("256B stride\n");
108 printf("512B stride\n");
111 printf("4K stride\n");
114 printf("32MB + 256B stride\n");
117 printf("no stride\n");
121 inline void sdram_print_dram_type(unsigned char dramtype)
125 inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
126 struct sdram_base_params *base)
130 inline void sdram_print_stride(unsigned int stride)
139 * note: it didn't consider about row_3_4
141 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
146 if (dram_type == DDR4)
147 /* DDR4 8bit dram BG = 2(4bank groups),
148 * 16bit dram BG = 1 (2 bank groups)
150 bg = (cap_info->dbw == 0) ? 2 : 1;
153 cap[0] = 1llu << (cap_info->bw + cap_info->col +
154 bg + cap_info->bk + cap_info->cs0_row);
156 if (cap_info->rank == 2)
157 cap[1] = 1llu << (cap_info->bw + cap_info->col +
158 bg + cap_info->bk + cap_info->cs1_row);
167 return (cap[0] + cap[1]);
171 void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n)
175 for (i = 0; i < n / sizeof(u32); i++) {
182 void sdram_org_config(struct sdram_cap_info *cap_info,
183 struct sdram_base_params *base,
184 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel)
186 *p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype);
187 *p_os_reg2 |= SYS_REG_ENC_NUM_CH(base->num_channels);
189 *p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel);
190 *p_os_reg2 |= SYS_REG_ENC_CHINFO(channel);
191 *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel);
192 *p_os_reg2 |= SYS_REG_ENC_COL(cap_info->col, channel);
193 *p_os_reg2 |= SYS_REG_ENC_BK(cap_info->bk, channel);
194 *p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel);
195 *p_os_reg2 |= SYS_REG_ENC_DBW(cap_info->dbw, channel);
197 SYS_REG_ENC_CS0_ROW(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel);
198 if (cap_info->cs1_row)
199 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, *p_os_reg2,
200 *p_os_reg3, channel);
201 *p_os_reg3 |= SYS_REG_ENC_CS1_COL(cap_info->col, channel);
202 *p_os_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
205 int sdram_detect_bw(struct sdram_cap_info *cap_info)
210 int sdram_detect_cs(struct sdram_cap_info *cap_info)
215 int sdram_detect_col(struct sdram_cap_info *cap_info,
218 void __iomem *test_addr;
220 u32 bw = cap_info->bw;
222 for (col = coltmp; col >= 9; col -= 1) {
223 writel(0, CONFIG_SYS_SDRAM_BASE);
224 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
225 (1ul << (col + bw - 1ul)));
226 writel(PATTERN, test_addr);
227 if ((readl(test_addr) == PATTERN) &&
228 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
232 printascii("col error\n");
241 int sdram_detect_bank(struct sdram_cap_info *cap_info,
242 u32 coltmp, u32 bktmp)
244 void __iomem *test_addr;
246 u32 bw = cap_info->bw;
248 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
249 (1ul << (coltmp + bktmp + bw - 1ul)));
250 writel(0, CONFIG_SYS_SDRAM_BASE);
251 writel(PATTERN, test_addr);
252 if ((readl(test_addr) == PATTERN) &&
253 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
263 /* detect bg for ddr4 */
264 int sdram_detect_bg(struct sdram_cap_info *cap_info,
267 void __iomem *test_addr;
269 u32 bw = cap_info->bw;
271 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
272 (1ul << (coltmp + bw + 1ul)));
273 writel(0, CONFIG_SYS_SDRAM_BASE);
274 writel(PATTERN, test_addr);
275 if ((readl(test_addr) == PATTERN) &&
276 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
286 /* detect dbw for ddr3,lpddr2,lpddr3,lpddr4 */
287 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
289 u32 row, col, bk, bw, cs_cap, cs;
290 u32 die_bw_0 = 0, die_bw_1 = 0;
292 if (dram_type == DDR3 || dram_type == LPDDR4) {
294 } else if (dram_type == LPDDR3 || dram_type == LPDDR2) {
295 row = cap_info->cs0_row;
300 cs_cap = (1 << (row + col + bk + bw - 20));
302 if (cs_cap <= 0x2000000) /* 256Mb */
303 die_bw_0 = (col < 9) ? 2 : 1;
304 else if (cs_cap <= 0x10000000) /* 2Gb */
305 die_bw_0 = (col < 10) ? 2 : 1;
306 else if (cs_cap <= 0x40000000) /* 8Gb */
307 die_bw_0 = (col < 11) ? 2 : 1;
309 die_bw_0 = (col < 12) ? 2 : 1;
311 row = cap_info->cs1_row;
312 cs_cap = (1 << (row + col + bk + bw - 20));
313 if (cs_cap <= 0x2000000) /* 256Mb */
314 die_bw_0 = (col < 9) ? 2 : 1;
315 else if (cs_cap <= 0x10000000) /* 2Gb */
316 die_bw_0 = (col < 10) ? 2 : 1;
317 else if (cs_cap <= 0x40000000) /* 8Gb */
318 die_bw_0 = (col < 11) ? 2 : 1;
320 die_bw_0 = (col < 12) ? 2 : 1;
326 cap_info->dbw = (die_bw_0 > die_bw_1) ? die_bw_0 : die_bw_1;
332 int sdram_detect_row(struct sdram_cap_info *cap_info,
333 u32 coltmp, u32 bktmp, u32 rowtmp)
336 u32 bw = cap_info->bw;
337 void __iomem *test_addr;
339 for (row = rowtmp; row > 12; row--) {
340 writel(0, CONFIG_SYS_SDRAM_BASE);
341 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
342 (1ul << (row + bktmp + coltmp + bw - 1ul)));
343 writel(PATTERN, test_addr);
344 if ((readl(test_addr) == PATTERN) &&
345 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
349 printascii("row error");
353 cap_info->cs0_row = row;
358 int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
359 u32 coltmp, u32 bktmp)
362 u32 bw = cap_info->bw;
363 u32 row = cap_info->cs0_row;
364 void __iomem *test_addr, *test_addr1;
366 test_addr = CONFIG_SYS_SDRAM_BASE;
367 test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
368 (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
370 writel(0, test_addr);
371 writel(PATTERN, test_addr1);
372 if ((readl(test_addr) == 0) && (readl(test_addr1) == PATTERN))
377 cap_info->row_3_4 = row_3_4;
382 int sdram_detect_high_row(struct sdram_cap_info *cap_info)
384 cap_info->cs0_high16bit_row = cap_info->cs0_row;
385 cap_info->cs1_high16bit_row = cap_info->cs1_row;
390 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type)
392 void __iomem *test_addr;
393 u32 row = 0, bktmp, coltmp, bw;
397 if (cap_info->rank == 2) {
398 cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type);
400 if (dram_type == DDR4) {
401 if (cap_info->dbw == 0)
402 bktmp = cap_info->bk + 2;
404 bktmp = cap_info->bk + 1;
406 bktmp = cap_info->bk;
409 coltmp = cap_info->col;
412 * because px30 support axi split,min bandwidth
413 * is 8bit. if cs0 is 32bit, cs1 may 32bit or 16bit
414 * so we check low 16bit data when detect cs1 row.
415 * if cs0 is 16bit/8bit, we check low 8bit data.
423 for (row = cap_info->cs0_row; row > 12; row--) {
424 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
426 (1ul << (row + bktmp + coltmp + bw - 1ul)));
427 writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
428 writel(PATTERN, test_addr);
430 if (((readl(test_addr) & byte_mask) ==
431 (PATTERN & byte_mask)) &&
432 ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
439 cap_info->cs1_row = row;