drivers/ram/k3-j721e/k3-j721e-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' J721E DDRSS driver
   4  *
   5  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <hang.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <power-domain.h>
  15 #include <wait_bit.h>
  16 #include <dm/device_compat.h>
  17
  18 #include "lpddr4_obj_if.h"
  19 #include "lpddr4_if.h"
  20 #include "lpddr4_structs_if.h"
  21 #include "lpddr4_ctl_regs.h"
  22
  23 #define SRAM_MAX 512
  24
  25 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS       0x80
  26 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS       0xc0
  27
  28 struct j721e_ddrss_desc {
  29         struct udevice *dev;
  30         void __iomem *ddrss_ss_cfg;
  31         void __iomem *ddrss_ctrl_mmr;
  32         struct power_domain ddrcfg_pwrdmn;
  33         struct power_domain ddrdata_pwrdmn;
  34         struct clk ddr_clk;
  35         struct clk osc_clk;
  36         u32 ddr_freq1;
  37         u32 ddr_freq2;
  38         u32 ddr_fhs_cnt;
  39 };
  40
  41 static LPDDR4_OBJ *driverdt;
  42 static lpddr4_config config;
  43 static lpddr4_privatedata pd;
  44
  45 static struct j721e_ddrss_desc *ddrss;
  46
  47 #define TH_MACRO_EXP(fld, str) (fld##str)
  48
  49 #define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
  50 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
  51 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
  52 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
  53 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
  54
  55 #define str(s) #s
  56 #define xstr(s) str(s)
  57
  58 #define  CTL_SHIFT 11
  59 #define  PHY_SHIFT 11
  60 #define  PI_SHIFT 10
  61
  62 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
  63         char *i, *pstr= xstr(REG); offset = 0;\
  64         for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
  65                 offset = offset * 10 + (*i - '0'); }\
  66         } while (0)
  67
  68 static void j721e_lpddr4_ack_freq_upd_req(void)
  69 {
  70         unsigned int req_type, counter;
  71
  72         debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
  73
  74         for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
  75                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
  76                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
  77                                       true, 10000, false)) {
  78                         printf("Timeout during frequency handshake\n");
  79                         hang();
  80                 }
  81
  82                 req_type = readl(ddrss->ddrss_ctrl_mmr +
  83                                  CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
  84
  85                 debug("%s: received freq change req: req type = %d, req no. = %d \n",
  86                       __func__, req_type, counter);
  87
  88                 if (req_type == 1)
  89                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
  90                 else if (req_type == 2)
  91                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
  92                 else if (req_type == 0)
  93                         /* Put DDR pll in bypass mode */
  94                         clk_set_rate(&ddrss->ddr_clk,
  95                                      clk_get_rate(&ddrss->osc_clk));
  96                 else
  97                         printf("%s: Invalid freq request type\n", __func__);
  98
  99                 writel(0x1, ddrss->ddrss_ctrl_mmr +
 100                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 101                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 102                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
 103                                       false, 10, false)) {
 104                         printf("Timeout during frequency handshake\n");
 105                         hang();
 106                 }
 107                 writel(0x0, ddrss->ddrss_ctrl_mmr +
 108                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 109         }
 110 }
 111
 112 static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
 113                                       lpddr4_infotype infotype)
 114 {
 115         if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
 116                 j721e_lpddr4_ack_freq_upd_req();
 117         }
 118 }
 119
 120 static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
 121 {
 122         int ret;
 123
 124         debug("%s(ddrss=%p)\n", __func__, ddrss);
 125
 126         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 127         if (ret) {
 128                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 129                 return ret;
 130         }
 131
 132         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 133         if (ret) {
 134                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 135                 return ret;
 136         }
 137
 138         return 0;
 139 }
 140
 141 static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
 142 {
 143         struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
 144         phys_addr_t reg;
 145         int ret;
 146
 147         debug("%s(dev=%p)\n", __func__, dev);
 148
 149         reg = dev_read_addr_name(dev, "cfg");
 150         if (reg == FDT_ADDR_T_NONE) {
 151                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 152                 return -EINVAL;
 153         }
 154         ddrss->ddrss_ss_cfg = (void *)reg;
 155
 156         reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
 157         if (reg == FDT_ADDR_T_NONE) {
 158                 dev_err(dev, "No reg property for CTRL MMR\n");
 159                 return -EINVAL;
 160         }
 161         ddrss->ddrss_ctrl_mmr = (void *)reg;
 162
 163         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 164         if (ret) {
 165                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 166                 return ret;
 167         }
 168
 169         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 170         if (ret) {
 171                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 172                 return ret;
 173         }
 174
 175         ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
 176         if (ret)
 177                 dev_err(dev, "clk get failed%d\n", ret);
 178
 179         ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
 180         if (ret)
 181                 dev_err(dev, "clk get failed for osc clk %d\n", ret);
 182
 183         ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
 184         if (ret)
 185                 dev_err(dev, "ddr freq1 not populated %d\n", ret);
 186
 187         ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
 188         if (ret)
 189                 dev_err(dev, "ddr freq2 not populated %d\n", ret);
 190
 191         ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
 192         if (ret)
 193                 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 194
 195         /* Put DDR pll in bypass mode */
 196         ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
 197         if (ret)
 198                 dev_err(dev, "ddr clk bypass failed\n");
 199
 200         return ret;
 201 }
 202
 203 void j721e_lpddr4_probe(void)
 204 {
 205         uint32_t status = 0U;
 206         uint16_t configsize = 0U;
 207
 208         status = driverdt->probe(&config, &configsize);
 209
 210         if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 211             || (configsize > SRAM_MAX)) {
 212                 printf("LPDDR4_Probe: FAIL\n");
 213                 hang();
 214         } else {
 215                 debug("LPDDR4_Probe: PASS\n");
 216         }
 217 }
 218
 219 void j721e_lpddr4_init(void)
 220 {
 221         uint32_t status = 0U;
 222
 223         if ((sizeof(pd) != sizeof(lpddr4_privatedata))
 224             || (sizeof(pd) > SRAM_MAX)) {
 225                 printf("LPDDR4_Init: FAIL\n");
 226                 hang();
 227         }
 228
 229         config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
 230         config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
 231
 232         status = driverdt->init(&pd, &config);
 233
 234         if ((status > 0U) ||
 235             (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
 236             (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
 237             (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
 238                 printf("LPDDR4_Init: FAIL\n");
 239                 hang();
 240         } else {
 241                 debug("LPDDR4_Init: PASS\n");
 242         }
 243 }
 244
 245 void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
 246 {
 247         int ret, i;
 248
 249         ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
 250                                  (u32 *) reginit_data->denalictlreg,
 251                                  LPDDR4_CTL_REG_COUNT);
 252         if (ret)
 253                 printf("Error reading ctrl data\n");
 254
 255         for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
 256                 reginit_data->updatectlreg[i] = true;
 257
 258         ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
 259                                  (u32 *) reginit_data->denaliphyindepreg,
 260                                  LPDDR4_PHY_INDEP_REG_COUNT);
 261         if (ret)
 262                 printf("Error reading PI data\n");
 263
 264         for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
 265                 reginit_data->updatephyindepreg[i] = true;
 266
 267         ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
 268                                  (u32 *) reginit_data->denaliphyreg,
 269                                  LPDDR4_PHY_REG_COUNT);
 270         if (ret)
 271                 printf("Error reading PHY data\n");
 272
 273         for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
 274                 reginit_data->updatephyreg[i] = true;
 275 }
 276
 277 void j721e_lpddr4_hardware_reg_init(void)
 278 {
 279         uint32_t status = 0U;
 280         lpddr4_reginitdata reginitdata;
 281
 282         populate_data_array_from_dt(&reginitdata);
 283
 284         status = driverdt->writectlconfig(&pd, &reginitdata);
 285         if (!status) {
 286                 status = driverdt->writephyindepconfig(&pd, &reginitdata);
 287         }
 288         if (!status) {
 289                 status = driverdt->writephyconfig(&pd, &reginitdata);
 290         }
 291         if (status) {
 292                 printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
 293                 hang();
 294         }
 295
 296         return;
 297 }
 298
 299 void j721e_lpddr4_start(void)
 300 {
 301         uint32_t status = 0U;
 302         uint32_t regval = 0U;
 303         uint32_t offset = 0U;
 304
 305         TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 306
 307         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 308         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
 309                 printf("LPDDR4_StartTest: FAIL\n");
 310                 hang();
 311         }
 312
 313         status = driverdt->start(&pd);
 314         if (status > 0U) {
 315                 printf("LPDDR4_StartTest: FAIL\n");
 316                 hang();
 317         }
 318
 319         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 320         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
 321                 printf("LPDDR4_Start: FAIL\n");
 322                 hang();
 323         } else {
 324                 debug("LPDDR4_Start: PASS\n");
 325         }
 326 }
 327
 328 static int j721e_ddrss_probe(struct udevice *dev)
 329 {
 330         int ret;
 331         ddrss = dev_get_priv(dev);
 332
 333         debug("%s(dev=%p)\n", __func__, dev);
 334
 335         ret = j721e_ddrss_ofdata_to_priv(dev);
 336         if (ret)
 337                 return ret;
 338
 339         ddrss->dev = dev;
 340         ret = j721e_ddrss_power_on(ddrss);
 341         if (ret)
 342                 return ret;
 343
 344         driverdt = lpddr4_getinstance();
 345         j721e_lpddr4_probe();
 346         j721e_lpddr4_init();
 347         j721e_lpddr4_hardware_reg_init();
 348         j721e_lpddr4_start();
 349
 350         return ret;
 351 }
 352
 353 static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 354 {
 355         return 0;
 356 }
 357
 358 static struct ram_ops j721e_ddrss_ops = {
 359         .get_info = j721e_ddrss_get_info,
 360 };
 361
 362 static const struct udevice_id j721e_ddrss_ids[] = {
 363         {.compatible = "ti,j721e-ddrss"},
 364         {}
 365 };
 366
 367 U_BOOT_DRIVER(j721e_ddrss) = {
 368         .name = "j721e_ddrss",
 369         .id = UCLASS_RAM,
 370         .of_match = j721e_ddrss_ids,
 371         .ops = &j721e_ddrss_ops,
 372         .probe = j721e_ddrss_probe,
 373         .priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
 374 };