drivers/ram/k3-ddrss/k3-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' K3 DDRSS driver
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <config.h>
   9 #include <clk.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <dm/device_compat.h>
  13 #include <fdt_support.h>
  14 #include <ram.h>
  15 #include <hang.h>
  16 #include <log.h>
  17 #include <asm/io.h>
  18 #include <power-domain.h>
  19 #include <wait_bit.h>
  20 #include <power/regulator.h>
  21
  22 #include "lpddr4_obj_if.h"
  23 #include "lpddr4_if.h"
  24 #include "lpddr4_structs_if.h"
  25 #include "lpddr4_ctl_regs.h"
  26
  27 #define SRAM_MAX 512
  28
  29 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS       0x80
  30 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS       0xc0
  31
  32 #define DDRSS_V2A_CTL_REG                       0x0020
  33 #define DDRSS_ECC_CTRL_REG                      0x0120
  34
  35 #define DDRSS_ECC_CTRL_REG_ECC_EN               BIT(0)
  36 #define DDRSS_ECC_CTRL_REG_RMW_EN               BIT(1)
  37 #define DDRSS_ECC_CTRL_REG_ECC_CK               BIT(2)
  38 #define DDRSS_ECC_CTRL_REG_WR_ALLOC             BIT(4)
  39
  40 #define DDRSS_ECC_R0_STR_ADDR_REG               0x0130
  41 #define DDRSS_ECC_R0_END_ADDR_REG               0x0134
  42 #define DDRSS_ECC_R1_STR_ADDR_REG               0x0138
  43 #define DDRSS_ECC_R1_END_ADDR_REG               0x013c
  44 #define DDRSS_ECC_R2_STR_ADDR_REG               0x0140
  45 #define DDRSS_ECC_R2_END_ADDR_REG               0x0144
  46 #define DDRSS_ECC_1B_ERR_CNT_REG                0x0150
  47
  48 #define SINGLE_DDR_SUBSYSTEM    0x1
  49 #define MULTI_DDR_SUBSYSTEM     0x2
  50
  51 #define MULTI_DDR_CFG0  0x00114100
  52 #define MULTI_DDR_CFG1  0x00114104
  53 #define DDR_CFG_LOAD    0x00114110
  54
  55 enum intrlv_gran {
  56         GRAN_128B,
  57         GRAN_512B,
  58         GRAN_2KB,
  59         GRAN_4KB,
  60         GRAN_16KB,
  61         GRAN_32KB,
  62         GRAN_512KB,
  63         GRAN_1GB,
  64         GRAN_1_5GB,
  65         GRAN_2GB,
  66         GRAN_3GB,
  67         GRAN_4GB,
  68         GRAN_6GB,
  69         GRAN_8GB,
  70         GRAN_16GB
  71 };
  72
  73 enum intrlv_size {
  74         SIZE_0,
  75         SIZE_128MB,
  76         SIZE_256MB,
  77         SIZE_512MB,
  78         SIZE_1GB,
  79         SIZE_2GB,
  80         SIZE_3GB,
  81         SIZE_4GB,
  82         SIZE_6GB,
  83         SIZE_8GB,
  84         SIZE_12GB,
  85         SIZE_16GB,
  86         SIZE_32GB
  87 };
  88
  89 struct k3_ddrss_data {
  90         u32 flags;
  91 };
  92
  93 enum ecc_enable {
  94         DISABLE_ALL = 0,
  95         ENABLE_0,
  96         ENABLE_1,
  97         ENABLE_ALL
  98 };
  99
 100 enum emif_config {
 101         INTERLEAVE_ALL = 0,
 102         SEPR0,
 103         SEPR1
 104 };
 105
 106 enum emif_active {
 107         EMIF_0 = 1,
 108         EMIF_1,
 109         EMIF_ALL
 110 };
 111
 112 struct k3_msmc {
 113         enum intrlv_gran gran;
 114         enum intrlv_size size;
 115         enum ecc_enable enable;
 116         enum emif_config config;
 117         enum emif_active active;
 118 };
 119
 120 #define K3_DDRSS_MAX_ECC_REGIONS                3
 121
 122 struct k3_ddrss_ecc_region {
 123         u32 start;
 124         u32 range;
 125 };
 126
 127 struct k3_ddrss_desc {
 128         struct udevice *dev;
 129         void __iomem *ddrss_ss_cfg;
 130         void __iomem *ddrss_ctrl_mmr;
 131         void __iomem *ddrss_ctl_cfg;
 132         struct power_domain ddrcfg_pwrdmn;
 133         struct power_domain ddrdata_pwrdmn;
 134         struct clk ddr_clk;
 135         struct clk osc_clk;
 136         u32 ddr_freq0;
 137         u32 ddr_freq1;
 138         u32 ddr_freq2;
 139         u32 ddr_fhs_cnt;
 140         u32 dram_class;
 141         struct udevice *vtt_supply;
 142         u32 instance;
 143         lpddr4_obj *driverdt;
 144         lpddr4_config config;
 145         lpddr4_privatedata pd;
 146         struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
 147         u64 ecc_reserved_space;
 148         bool ti_ecc_enabled;
 149 };
 150
 151 struct reginitdata {
 152         u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
 153         u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
 154         u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
 155         u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
 156         u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
 157         u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
 158 };
 159
 160 #define TH_MACRO_EXP(fld, str) (fld##str)
 161
 162 #define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
 163 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
 164 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
 165 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
 166 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
 167
 168 #define str(s) #s
 169 #define xstr(s) str(s)
 170
 171 #define CTL_SHIFT 11
 172 #define PHY_SHIFT 11
 173 #define PI_SHIFT 10
 174
 175 #define DENALI_CTL_0_DRAM_CLASS_DDR4            0xA
 176 #define DENALI_CTL_0_DRAM_CLASS_LPDDR4          0xB
 177
 178 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
 179         char *i, *pstr = xstr(REG); offset = 0;\
 180         for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
 181                 offset = offset * 10 + (*i - '0'); } \
 182         } while (0)
 183
 184 static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
 185 {
 186         u32 status = 0U;
 187         u32 offset = 0U;
 188         u32 regval = 0U;
 189         u32 dram_class = 0U;
 190         struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
 191
 192         TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
 193         status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
 194         if (status > 0U) {
 195                 printf("%s: Failed to read DRAM_CLASS\n", __func__);
 196                 hang();
 197         }
 198
 199         dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
 200                 TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
 201         return dram_class;
 202 }
 203
 204 static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
 205 {
 206         unsigned int req_type, counter;
 207
 208         for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
 209                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 210                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
 211                                       true, 10000, false)) {
 212                         printf("Timeout during frequency handshake\n");
 213                         hang();
 214                 }
 215
 216                 req_type = readl(ddrss->ddrss_ctrl_mmr +
 217                                  CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
 218
 219                 debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
 220                       __func__, req_type, counter, ddrss->instance);
 221
 222                 if (req_type == 1)
 223                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 224                 else if (req_type == 2)
 225                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
 226                 else if (req_type == 0)
 227                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
 228                 else
 229                         printf("%s: Invalid freq request type\n", __func__);
 230
 231                 writel(0x1, ddrss->ddrss_ctrl_mmr +
 232                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
 233                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 234                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
 235                                       false, 10, false)) {
 236                         printf("Timeout during frequency handshake\n");
 237                         hang();
 238                 }
 239                 writel(0x0, ddrss->ddrss_ctrl_mmr +
 240                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
 241         }
 242 }
 243
 244 static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
 245 {
 246         struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
 247
 248         debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
 249
 250         switch (ddrss->dram_class) {
 251         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 252                 break;
 253         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 254                 k3_lpddr4_freq_update(ddrss);
 255                 break;
 256         default:
 257                 printf("Unrecognized dram_class cannot update frequency!\n");
 258         }
 259 }
 260
 261 static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
 262 {
 263         int ret;
 264         lpddr4_privatedata *pd = &ddrss->pd;
 265
 266         ddrss->dram_class = k3_lpddr4_read_ddr_type(pd);
 267
 268         switch (ddrss->dram_class) {
 269         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 270                 /* Set to ddr_freq1 from DT for DDR4 */
 271                 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 272                 break;
 273         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 274                 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
 275                 break;
 276         default:
 277                 ret = -EINVAL;
 278                 printf("Unrecognized dram_class cannot init frequency!\n");
 279         }
 280
 281         if (ret < 0)
 282                 dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
 283         else
 284                 ret = 0;
 285
 286         return ret;
 287 }
 288
 289 static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
 290                                    lpddr4_infotype infotype)
 291 {
 292         if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
 293                 k3_lpddr4_ack_freq_upd_req(pd);
 294 }
 295
 296 static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
 297 {
 298         int ret;
 299
 300         debug("%s(ddrss=%p)\n", __func__, ddrss);
 301
 302         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 303         if (ret) {
 304                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 305                 return ret;
 306         }
 307
 308         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 309         if (ret) {
 310                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 311                 return ret;
 312         }
 313
 314         ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
 315                                           &ddrss->vtt_supply);
 316         if (ret) {
 317                 dev_dbg(ddrss->dev, "vtt-supply not found.\n");
 318         } else {
 319                 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
 320                 if (ret)
 321                         return ret;
 322                 dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
 323                         regulator_get_value(ddrss->vtt_supply));
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 330 {
 331         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 332         struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
 333         void *reg;
 334         int ret;
 335
 336         debug("%s(dev=%p)\n", __func__, dev);
 337
 338         reg = dev_read_addr_name_ptr(dev, "cfg");
 339         if (!reg) {
 340                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 341                 return -EINVAL;
 342         }
 343         ddrss->ddrss_ctl_cfg = reg;
 344
 345         reg = dev_read_addr_name_ptr(dev, "ctrl_mmr_lp4");
 346         if (!reg) {
 347                 dev_err(dev, "No reg property for CTRL MMR\n");
 348                 return -EINVAL;
 349         }
 350         ddrss->ddrss_ctrl_mmr = reg;
 351
 352         reg = dev_read_addr_name_ptr(dev, "ss_cfg");
 353         if (!reg)
 354                 dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
 355         ddrss->ddrss_ss_cfg = reg;
 356
 357         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 358         if (ret) {
 359                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 360                 return ret;
 361         }
 362
 363         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 364         if (ret) {
 365                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 366                 return ret;
 367         }
 368
 369         ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
 370         if (ret)
 371                 dev_err(dev, "clk get failed%d\n", ret);
 372
 373         ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
 374         if (ret)
 375                 dev_err(dev, "clk get failed for osc clk %d\n", ret);
 376
 377         /* Reading instance number for multi ddr subystems */
 378         if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
 379                 ret = dev_read_u32(dev, "instance", &ddrss->instance);
 380                 if (ret) {
 381                         dev_err(dev, "missing instance property");
 382                         return -EINVAL;
 383                 }
 384         } else {
 385                 ddrss->instance = 0;
 386         }
 387
 388         ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0);
 389         if (ret) {
 390                 ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk);
 391                 dev_dbg(dev,
 392                         "ddr freq0 not populated, using bypass frequency.\n");
 393         }
 394
 395         ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
 396         if (ret)
 397                 dev_err(dev, "ddr freq1 not populated %d\n", ret);
 398
 399         ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
 400         if (ret)
 401                 dev_err(dev, "ddr freq2 not populated %d\n", ret);
 402
 403         ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
 404         if (ret)
 405                 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 406
 407         ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
 408
 409         return ret;
 410 }
 411
 412 void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
 413 {
 414         u32 status = 0U;
 415         u16 configsize = 0U;
 416         lpddr4_config *config = &ddrss->config;
 417
 418         status = ddrss->driverdt->probe(config, &configsize);
 419
 420         if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 421             || (configsize > SRAM_MAX)) {
 422                 printf("%s: FAIL\n", __func__);
 423                 hang();
 424         } else {
 425                 debug("%s: PASS\n", __func__);
 426         }
 427 }
 428
 429 void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
 430 {
 431         u32 status = 0U;
 432         lpddr4_config *config = &ddrss->config;
 433         lpddr4_obj *driverdt = ddrss->driverdt;
 434         lpddr4_privatedata *pd = &ddrss->pd;
 435
 436         if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
 437                 printf("%s: FAIL\n", __func__);
 438                 hang();
 439         }
 440
 441         config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg;
 442         config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
 443
 444         status = driverdt->init(pd, config);
 445
 446         /* linking ddr instance to lpddr4  */
 447         pd->ddr_instance = (void *)ddrss;
 448
 449         if ((status > 0U) ||
 450             (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
 451             (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
 452             (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
 453                 printf("%s: FAIL\n", __func__);
 454                 hang();
 455         } else {
 456                 debug("%s: PASS\n", __func__);
 457         }
 458 }
 459
 460 void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
 461                                  struct reginitdata *reginit_data)
 462 {
 463         int ret, i;
 464
 465         ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
 466                                  (u32 *)reginit_data->ctl_regs,
 467                                  LPDDR4_INTR_CTL_REG_COUNT);
 468         if (ret)
 469                 printf("Error reading ctrl data %d\n", ret);
 470
 471         for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
 472                 reginit_data->ctl_regs_offs[i] = i;
 473
 474         ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
 475                                  (u32 *)reginit_data->pi_regs,
 476                                  LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 477         if (ret)
 478                 printf("Error reading PI data\n");
 479
 480         for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
 481                 reginit_data->pi_regs_offs[i] = i;
 482
 483         ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
 484                                  (u32 *)reginit_data->phy_regs,
 485                                  LPDDR4_INTR_PHY_REG_COUNT);
 486         if (ret)
 487                 printf("Error reading PHY data %d\n", ret);
 488
 489         for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
 490                 reginit_data->phy_regs_offs[i] = i;
 491 }
 492
 493 void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
 494 {
 495         u32 status = 0U;
 496         struct reginitdata reginitdata;
 497         lpddr4_obj *driverdt = ddrss->driverdt;
 498         lpddr4_privatedata *pd = &ddrss->pd;
 499
 500         populate_data_array_from_dt(ddrss, &reginitdata);
 501
 502         status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
 503                                           reginitdata.ctl_regs_offs,
 504                                           LPDDR4_INTR_CTL_REG_COUNT);
 505         if (!status)
 506                 status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
 507                                                        reginitdata.pi_regs_offs,
 508                                                        LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 509         if (!status)
 510                 status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
 511                                                   reginitdata.phy_regs_offs,
 512                                                   LPDDR4_INTR_PHY_REG_COUNT);
 513         if (status) {
 514                 printf("%s: FAIL\n", __func__);
 515                 hang();
 516         }
 517 }
 518
 519 void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
 520 {
 521         u32 status = 0U;
 522         u32 regval = 0U;
 523         u32 offset = 0U;
 524         lpddr4_obj *driverdt = ddrss->driverdt;
 525         lpddr4_privatedata *pd = &ddrss->pd;
 526
 527         TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 528
 529         status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
 530         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
 531                 printf("%s: Pre start FAIL\n", __func__);
 532                 hang();
 533         }
 534
 535         status = driverdt->start(pd);
 536         if (status > 0U) {
 537                 printf("%s: FAIL\n", __func__);
 538                 hang();
 539         }
 540
 541         status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
 542         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
 543                 printf("%s: Post start FAIL\n", __func__);
 544                 hang();
 545         } else {
 546                 debug("%s: Post start PASS\n", __func__);
 547         }
 548 }
 549
 550 static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
 551 {
 552         writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
 553         writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
 554 }
 555
 556 static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
 557 {
 558         int i;
 559
 560         printf("ECC is enabled, priming DDR which will take several seconds.\n");
 561
 562         for (i = 0; i < (size / 4); i++)
 563                 addr[i] = word;
 564 }
 565
 566 static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
 567 {
 568         fdtdec_setup_mem_size_base_lowest();
 569
 570         ddrss->ecc_reserved_space = gd->ram_size;
 571         do_div(ddrss->ecc_reserved_space, 9);
 572
 573         /* Round to clean number */
 574         ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
 575 }
 576
 577 static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
 578 {
 579         u32 ecc_region_start = ddrss->ecc_regions[0].start;
 580         u32 ecc_range = ddrss->ecc_regions[0].range;
 581         u32 base = (u32)ddrss->ddrss_ss_cfg;
 582         u32 val;
 583
 584         /* Only Program region 0 which covers full ddr space */
 585         k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
 586
 587         /* Enable ECC, RMW, WR_ALLOC */
 588         writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
 589                DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
 590
 591         /* Preload ECC Mem region with 0's */
 592         k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
 593                                         0x00000000);
 594
 595         /* Clear Error Count Register */
 596         writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
 597
 598         /* Enable ECC Check */
 599         val = readl(base + DDRSS_ECC_CTRL_REG);
 600         val |= DDRSS_ECC_CTRL_REG_ECC_CK;
 601         writel(val, base + DDRSS_ECC_CTRL_REG);
 602 }
 603
 604 static int k3_ddrss_probe(struct udevice *dev)
 605 {
 606         int ret;
 607         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 608
 609         debug("%s(dev=%p)\n", __func__, dev);
 610
 611         ret = k3_ddrss_ofdata_to_priv(dev);
 612         if (ret)
 613                 return ret;
 614
 615         ddrss->dev = dev;
 616         ret = k3_ddrss_power_on(ddrss);
 617         if (ret)
 618                 return ret;
 619
 620 #ifdef CONFIG_K3_AM64_DDRSS
 621         /* AM64x supports only up to 2 GB SDRAM */
 622         writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
 623         writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
 624 #endif
 625
 626         ddrss->driverdt = lpddr4_getinstance();
 627
 628         k3_lpddr4_probe(ddrss);
 629         k3_lpddr4_init(ddrss);
 630         k3_lpddr4_hardware_reg_init(ddrss);
 631
 632         ret = k3_ddrss_init_freq(ddrss);
 633         if (ret)
 634                 return ret;
 635
 636         k3_lpddr4_start(ddrss);
 637
 638         if (ddrss->ti_ecc_enabled) {
 639                 if (!ddrss->ddrss_ss_cfg) {
 640                         printf("%s: ss_cfg is required if ecc is enabled but not provided.",
 641                                __func__);
 642                         return -EINVAL;
 643                 }
 644
 645                 k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
 646
 647                 /* Always configure one region that covers full DDR space */
 648                 ddrss->ecc_regions[0].start = gd->ram_base;
 649                 ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
 650                 k3_ddrss_lpddr4_ecc_init(ddrss);
 651         }
 652
 653         return ret;
 654 }
 655
 656 int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
 657 {
 658         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 659         u64 start[CONFIG_NR_DRAM_BANKS];
 660         u64 size[CONFIG_NR_DRAM_BANKS];
 661         int bank;
 662
 663         if (ddrss->ecc_reserved_space == 0)
 664                 return 0;
 665
 666         for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
 667                 if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
 668                         ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
 669                         bd->bi_dram[bank].size = 0;
 670                 } else {
 671                         bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
 672                         break;
 673                 }
 674         }
 675
 676         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 677                 start[bank] =  bd->bi_dram[bank].start;
 678                 size[bank] = bd->bi_dram[bank].size;
 679         }
 680
 681         return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
 682 }
 683
 684 static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 685 {
 686         return 0;
 687 }
 688
 689 static struct ram_ops k3_ddrss_ops = {
 690         .get_info = k3_ddrss_get_info,
 691 };
 692
 693 static const struct k3_ddrss_data k3_data = {
 694         .flags = SINGLE_DDR_SUBSYSTEM,
 695 };
 696
 697 static const struct k3_ddrss_data j721s2_data = {
 698         .flags = MULTI_DDR_SUBSYSTEM,
 699 };
 700
 701 static const struct udevice_id k3_ddrss_ids[] = {
 702         {.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, },
 703         {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
 704         {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
 705         {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
 706         {}
 707 };
 708
 709 U_BOOT_DRIVER(k3_ddrss) = {
 710         .name                   = "k3_ddrss",
 711         .id                     = UCLASS_RAM,
 712         .of_match               = k3_ddrss_ids,
 713         .ops                    = &k3_ddrss_ops,
 714         .probe                  = k3_ddrss_probe,
 715         .priv_auto              = sizeof(struct k3_ddrss_desc),
 716 };
 717
 718 static int k3_msmc_set_config(struct k3_msmc *msmc)
 719 {
 720         u32 ddr_cfg0 = 0;
 721         u32 ddr_cfg1 = 0;
 722
 723         ddr_cfg0 |= msmc->gran << 24;
 724         ddr_cfg0 |= msmc->size << 16;
 725         /* heartbeat_per, bit[4:0] setting to 3 is advisable */
 726         ddr_cfg0 |= 3;
 727
 728         /* Program MULTI_DDR_CFG0 */
 729         writel(ddr_cfg0, MULTI_DDR_CFG0);
 730
 731         ddr_cfg1 |= msmc->enable << 16;
 732         ddr_cfg1 |= msmc->config << 8;
 733         ddr_cfg1 |= msmc->active;
 734
 735         /* Program MULTI_DDR_CFG1 */
 736         writel(ddr_cfg1, MULTI_DDR_CFG1);
 737
 738         /* Program DDR_CFG_LOAD */
 739         writel(0x60000000, DDR_CFG_LOAD);
 740
 741         return 0;
 742 }
 743
 744 static int k3_msmc_probe(struct udevice *dev)
 745 {
 746         struct k3_msmc *msmc = dev_get_priv(dev);
 747         int ret = 0;
 748
 749         /* Read the granular size from DT */
 750         ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
 751         if (ret) {
 752                 dev_err(dev, "missing intrlv-gran property");
 753                 return -EINVAL;
 754         }
 755
 756         /* Read the interleave region from DT */
 757         ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
 758         if (ret) {
 759                 dev_err(dev, "missing intrlv-size property");
 760                 return -EINVAL;
 761         }
 762
 763         /* Read ECC enable config */
 764         ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
 765         if (ret) {
 766                 dev_err(dev, "missing ecc-enable property");
 767                 return -EINVAL;
 768         }
 769
 770         /* Read EMIF configuration */
 771         ret = dev_read_u32(dev, "emif-config", &msmc->config);
 772         if (ret) {
 773                 dev_err(dev, "missing emif-config property");
 774                 return -EINVAL;
 775         }
 776
 777         /* Read EMIF active */
 778         ret = dev_read_u32(dev, "emif-active", &msmc->active);
 779         if (ret) {
 780                 dev_err(dev, "missing emif-active property");
 781                 return -EINVAL;
 782         }
 783
 784         ret = k3_msmc_set_config(msmc);
 785         if (ret) {
 786                 dev_err(dev, "error setting msmc config");
 787                 return -EINVAL;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static const struct udevice_id k3_msmc_ids[] = {
 794         { .compatible = "ti,j721s2-msmc"},
 795         {}
 796 };
 797
 798 U_BOOT_DRIVER(k3_msmc) = {
 799         .name = "k3_msmc",
 800         .of_match = k3_msmc_ids,
 801         .id = UCLASS_MISC,
 802         .probe = k3_msmc_probe,
 803         .priv_auto = sizeof(struct k3_msmc),
 804         .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
 805 };