drivers/ram/k3-ddrss/k3-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' K3 DDRSS driver
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/device_compat.h>
  12 #include <ram.h>
  13 #include <hang.h>
  14 #include <log.h>
  15 #include <asm/io.h>
  16 #include <power-domain.h>
  17 #include <wait_bit.h>
  18 #include <power/regulator.h>
  19
  20 #include "lpddr4_obj_if.h"
  21 #include "lpddr4_if.h"
  22 #include "lpddr4_structs_if.h"
  23 #include "lpddr4_ctl_regs.h"
  24
  25 #define SRAM_MAX 512
  26
  27 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS       0x80
  28 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS       0xc0
  29
  30 #define DDRSS_V2A_R1_MAT_REG                    0x0020
  31 #define DDRSS_ECC_CTRL_REG                      0x0120
  32
  33 #define SINGLE_DDR_SUBSYSTEM    0x1
  34 #define MULTI_DDR_SUBSYSTEM     0x2
  35
  36 struct k3_ddrss_desc {
  37         struct udevice *dev;
  38         void __iomem *ddrss_ss_cfg;
  39         void __iomem *ddrss_ctrl_mmr;
  40         struct power_domain ddrcfg_pwrdmn;
  41         struct power_domain ddrdata_pwrdmn;
  42         struct clk ddr_clk;
  43         struct clk osc_clk;
  44         u32 ddr_freq1;
  45         u32 ddr_freq2;
  46         u32 ddr_fhs_cnt;
  47         struct udevice *vtt_supply;
  48         u32 instance;
  49         lpddr4_obj *driverdt;
  50         lpddr4_config config;
  51         lpddr4_privatedata pd;
  52 };
  53
  54 struct reginitdata {
  55         u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
  56         u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
  57         u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
  58         u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
  59         u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
  60         u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
  61 };
  62
  63 #define TH_MACRO_EXP(fld, str) (fld##str)
  64
  65 #define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
  66 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
  67 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
  68 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
  69 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
  70
  71 #define str(s) #s
  72 #define xstr(s) str(s)
  73
  74 #define CTL_SHIFT 11
  75 #define PHY_SHIFT 11
  76 #define PI_SHIFT 10
  77
  78 #define DENALI_CTL_0_DRAM_CLASS_DDR4            0xA
  79 #define DENALI_CTL_0_DRAM_CLASS_LPDDR4          0xB
  80
  81 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
  82         char *i, *pstr = xstr(REG); offset = 0;\
  83         for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
  84                 offset = offset * 10 + (*i - '0'); } \
  85         } while (0)
  86
  87 static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
  88 {
  89         u32 status = 0U;
  90         u32 offset = 0U;
  91         u32 regval = 0U;
  92         u32 dram_class = 0U;
  93         struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
  94
  95         TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
  96         status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
  97         if (status > 0U) {
  98                 printf("%s: Failed to read DRAM_CLASS\n", __func__);
  99                 hang();
 100         }
 101
 102         dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
 103                 TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
 104         return dram_class;
 105 }
 106
 107 static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
 108 {
 109         unsigned int req_type, counter;
 110
 111         for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
 112                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 113                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
 114                                       true, 10000, false)) {
 115                         printf("Timeout during frequency handshake\n");
 116                         hang();
 117                 }
 118
 119                 req_type = readl(ddrss->ddrss_ctrl_mmr +
 120                                  CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
 121
 122                 debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
 123                       __func__, req_type, counter, ddrss->instance);
 124
 125                 if (req_type == 1)
 126                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 127                 else if (req_type == 2)
 128                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
 129                 else if (req_type == 0)
 130                         /* Put DDR pll in bypass mode */
 131                         clk_set_rate(&ddrss->ddr_clk,
 132                                      clk_get_rate(&ddrss->osc_clk));
 133                 else
 134                         printf("%s: Invalid freq request type\n", __func__);
 135
 136                 writel(0x1, ddrss->ddrss_ctrl_mmr +
 137                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
 138                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 139                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
 140                                       false, 10, false)) {
 141                         printf("Timeout during frequency handshake\n");
 142                         hang();
 143                 }
 144                 writel(0x0, ddrss->ddrss_ctrl_mmr +
 145                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
 146         }
 147 }
 148
 149 static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
 150 {
 151         u32 dram_class;
 152         struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
 153
 154         debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
 155
 156         dram_class = k3_lpddr4_read_ddr_type(pd);
 157
 158         switch (dram_class) {
 159         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 160                 break;
 161         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 162                 k3_lpddr4_freq_update(ddrss);
 163                 break;
 164         default:
 165                 printf("Unrecognized dram_class cannot update frequency!\n");
 166         }
 167 }
 168
 169 static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
 170 {
 171         u32 dram_class;
 172         int ret;
 173         lpddr4_privatedata *pd = &ddrss->pd;
 174
 175         dram_class = k3_lpddr4_read_ddr_type(pd);
 176
 177         switch (dram_class) {
 178         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 179                 /* Set to ddr_freq1 from DT for DDR4 */
 180                 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 181                 break;
 182         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 183                 /* Set to bypass frequency for LPDDR4*/
 184                 ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
 185                 break;
 186         default:
 187                 ret = -EINVAL;
 188                 printf("Unrecognized dram_class cannot init frequency!\n");
 189         }
 190
 191         if (ret < 0)
 192                 dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
 193         else
 194                 ret = 0;
 195
 196         return ret;
 197 }
 198
 199 static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
 200                                    lpddr4_infotype infotype)
 201 {
 202         if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
 203                 k3_lpddr4_ack_freq_upd_req(pd);
 204 }
 205
 206 static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
 207 {
 208         int ret;
 209
 210         debug("%s(ddrss=%p)\n", __func__, ddrss);
 211
 212         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 213         if (ret) {
 214                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 215                 return ret;
 216         }
 217
 218         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 219         if (ret) {
 220                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 221                 return ret;
 222         }
 223
 224         ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
 225                                           &ddrss->vtt_supply);
 226         if (ret) {
 227                 dev_dbg(ddrss->dev, "vtt-supply not found.\n");
 228         } else {
 229                 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
 230                 if (ret)
 231                         return ret;
 232                 dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
 233                         regulator_get_value(ddrss->vtt_supply));
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 240 {
 241         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 242         struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
 243         phys_addr_t reg;
 244         int ret;
 245
 246         debug("%s(dev=%p)\n", __func__, dev);
 247
 248         reg = dev_read_addr_name(dev, "cfg");
 249         if (reg == FDT_ADDR_T_NONE) {
 250                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 251                 return -EINVAL;
 252         }
 253         ddrss->ddrss_ss_cfg = (void *)reg;
 254
 255         reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
 256         if (reg == FDT_ADDR_T_NONE) {
 257                 dev_err(dev, "No reg property for CTRL MMR\n");
 258                 return -EINVAL;
 259         }
 260         ddrss->ddrss_ctrl_mmr = (void *)reg;
 261
 262         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 263         if (ret) {
 264                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 265                 return ret;
 266         }
 267
 268         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 269         if (ret) {
 270                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 271                 return ret;
 272         }
 273
 274         ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
 275         if (ret)
 276                 dev_err(dev, "clk get failed%d\n", ret);
 277
 278         ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
 279         if (ret)
 280                 dev_err(dev, "clk get failed for osc clk %d\n", ret);
 281
 282         /* Reading instance number for multi ddr subystems */
 283         if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
 284                 ret = dev_read_u32(dev, "instance", &ddrss->instance);
 285                 if (ret) {
 286                         dev_err(dev, "missing instance property");
 287                         return -EINVAL;
 288                 }
 289         } else {
 290                 ddrss->instance = 0;
 291         }
 292
 293         ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
 294         if (ret)
 295                 dev_err(dev, "ddr freq1 not populated %d\n", ret);
 296
 297         ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
 298         if (ret)
 299                 dev_err(dev, "ddr freq2 not populated %d\n", ret);
 300
 301         ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
 302         if (ret)
 303                 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 304
 305         return ret;
 306 }
 307
 308 void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
 309 {
 310         u32 status = 0U;
 311         u16 configsize = 0U;
 312         lpddr4_config *config = &ddrss->config;
 313
 314         status = ddrss->driverdt->probe(config, &configsize);
 315
 316         if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 317             || (configsize > SRAM_MAX)) {
 318                 printf("%s: FAIL\n", __func__);
 319                 hang();
 320         } else {
 321                 debug("%s: PASS\n", __func__);
 322         }
 323 }
 324
 325 void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
 326 {
 327         u32 status = 0U;
 328         lpddr4_config *config = &ddrss->config;
 329         lpddr4_obj *driverdt = ddrss->driverdt;
 330         lpddr4_privatedata *pd = &ddrss->pd;
 331
 332         if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
 333                 printf("%s: FAIL\n", __func__);
 334                 hang();
 335         }
 336
 337         config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
 338         config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
 339
 340         status = driverdt->init(pd, config);
 341
 342         /* linking ddr instance to lpddr4  */
 343         pd->ddr_instance = (void *)ddrss;
 344
 345         if ((status > 0U) ||
 346             (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
 347             (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
 348             (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
 349                 printf("%s: FAIL\n", __func__);
 350                 hang();
 351         } else {
 352                 debug("%s: PASS\n", __func__);
 353         }
 354 }
 355
 356 void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
 357                                  struct reginitdata *reginit_data)
 358 {
 359         int ret, i;
 360
 361         ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
 362                                  (u32 *)reginit_data->ctl_regs,
 363                                  LPDDR4_INTR_CTL_REG_COUNT);
 364         if (ret)
 365                 printf("Error reading ctrl data %d\n", ret);
 366
 367         for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
 368                 reginit_data->ctl_regs_offs[i] = i;
 369
 370         ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
 371                                  (u32 *)reginit_data->pi_regs,
 372                                  LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 373         if (ret)
 374                 printf("Error reading PI data\n");
 375
 376         for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
 377                 reginit_data->pi_regs_offs[i] = i;
 378
 379         ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
 380                                  (u32 *)reginit_data->phy_regs,
 381                                  LPDDR4_INTR_PHY_REG_COUNT);
 382         if (ret)
 383                 printf("Error reading PHY data %d\n", ret);
 384
 385         for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
 386                 reginit_data->phy_regs_offs[i] = i;
 387 }
 388
 389 void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
 390 {
 391         u32 status = 0U;
 392         struct reginitdata reginitdata;
 393         lpddr4_obj *driverdt = ddrss->driverdt;
 394         lpddr4_privatedata *pd = &ddrss->pd;
 395
 396         populate_data_array_from_dt(ddrss, &reginitdata);
 397
 398         status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
 399                                           reginitdata.ctl_regs_offs,
 400                                           LPDDR4_INTR_CTL_REG_COUNT);
 401         if (!status)
 402                 status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
 403                                                        reginitdata.pi_regs_offs,
 404                                                        LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 405         if (!status)
 406                 status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
 407                                                   reginitdata.phy_regs_offs,
 408                                                   LPDDR4_INTR_PHY_REG_COUNT);
 409         if (status) {
 410                 printf("%s: FAIL\n", __func__);
 411                 hang();
 412         }
 413 }
 414
 415 void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
 416 {
 417         u32 status = 0U;
 418         u32 regval = 0U;
 419         u32 offset = 0U;
 420         lpddr4_obj *driverdt = ddrss->driverdt;
 421         lpddr4_privatedata *pd = &ddrss->pd;
 422
 423         TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 424
 425         status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
 426         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
 427                 printf("%s: Pre start FAIL\n", __func__);
 428                 hang();
 429         }
 430
 431         status = driverdt->start(pd);
 432         if (status > 0U) {
 433                 printf("%s: FAIL\n", __func__);
 434                 hang();
 435         }
 436
 437         status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
 438         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
 439                 printf("%s: Post start FAIL\n", __func__);
 440                 hang();
 441         } else {
 442                 debug("%s: Post start PASS\n", __func__);
 443         }
 444 }
 445
 446 static int k3_ddrss_probe(struct udevice *dev)
 447 {
 448         int ret;
 449         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 450
 451         debug("%s(dev=%p)\n", __func__, dev);
 452
 453         ret = k3_ddrss_ofdata_to_priv(dev);
 454         if (ret)
 455                 return ret;
 456
 457         ddrss->dev = dev;
 458         ret = k3_ddrss_power_on(ddrss);
 459         if (ret)
 460                 return ret;
 461
 462 #ifdef CONFIG_K3_AM64_DDRSS
 463
 464         writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
 465         writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
 466 #endif
 467
 468         ddrss->driverdt = lpddr4_getinstance();
 469
 470         k3_lpddr4_probe(ddrss);
 471         k3_lpddr4_init(ddrss);
 472         k3_lpddr4_hardware_reg_init(ddrss);
 473
 474         ret = k3_ddrss_init_freq(ddrss);
 475         if (ret)
 476                 return ret;
 477
 478         k3_lpddr4_start(ddrss);
 479
 480         return ret;
 481 }
 482
 483 static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 484 {
 485         return 0;
 486 }
 487
 488 static struct ram_ops k3_ddrss_ops = {
 489         .get_info = k3_ddrss_get_info,
 490 };
 491
 492 static const struct k3_ddrss_data k3_data = {
 493         .flags = SINGLE_DDR_SUBSYSTEM,
 494 };
 495
 496 static const struct k3_ddrss_data j721s2_data = {
 497         .flags = MULTI_DDR_SUBSYSTEM,
 498 };
 499
 500 static const struct udevice_id k3_ddrss_ids[] = {
 501         {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
 502         {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
 503         {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
 504         {}
 505 };
 506
 507 U_BOOT_DRIVER(k3_ddrss) = {
 508         .name                   = "k3_ddrss",
 509         .id                     = UCLASS_RAM,
 510         .of_match               = k3_ddrss_ids,
 511         .ops                    = &k3_ddrss_ops,
 512         .probe                  = k3_ddrss_probe,
 513         .priv_auto              = sizeof(struct k3_ddrss_desc),
 514 };