drivers/ram/k3-am654-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' AM654 DDRSS driver
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <asm/io.h>
  15 #include <power-domain.h>
  16 #include <dm/device_compat.h>
  17 #include <power/regulator.h>
  18 #include "k3-am654-ddrss.h"
  19
  20 void sdelay(unsigned long loops);
  21 u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
  22                   u32 bound);
  23
  24 #define LDELAY 10000
  25
  26 /* DDRSS PHY configuration register fixed values */
  27 #define DDRSS_DDRPHY_RANKIDR_RANK0      0
  28
  29 /**
  30  * struct am654_ddrss_desc - Description of ddrss integration.
  31  * @dev:                DDRSS device pointer
  32  * @ddrss_ss_cfg:       DDRSS wrapper logic region base address
  33  * @ddrss_ctl_cfg:      DDRSS controller region base address
  34  * @ddrss_phy_cfg:      DDRSS PHY region base address
  35  * @ddrss_clk:          DDRSS clock description
  36  * @vtt_supply:         VTT Supply regulator
  37  * @ddrss_pwrdmn:       DDRSS power domain description
  38  * @params:             SDRAM configuration parameters
  39  */
  40 struct am654_ddrss_desc {
  41         struct udevice *dev;
  42         void __iomem *ddrss_ss_cfg;
  43         void __iomem *ddrss_ctl_cfg;
  44         void __iomem *ddrss_phy_cfg;
  45         struct clk ddrss_clk;
  46         struct udevice *vtt_supply;
  47         struct power_domain ddrcfg_pwrdmn;
  48         struct power_domain ddrdata_pwrdmn;
  49         struct ddrss_params params;
  50 };
  51
  52 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
  53 {
  54         return readl(addr + offset);
  55 }
  56
  57 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
  58                                 u32 data)
  59 {
  60         debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
  61         writel(data, addr + offset);
  62 }
  63
  64 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
  65 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
  66
  67 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
  68 {
  69         return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
  70 }
  71
  72 /**
  73  * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
  74  *
  75  * After detecting the DDR type this function will pause until the
  76  * initialization is complete. Each DDR type has mask of multiple bits.
  77  * The size of the field depends on the DDR Type. If the initialization
  78  * does not complete and error will be returned and will cause the boot to halt.
  79  *
  80  */
  81 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
  82 {
  83         u32 val, mask;
  84
  85         val = am654_ddrss_get_type(ddrss);
  86
  87         switch (val) {
  88         case DDR_TYPE_LPDDR4:
  89         case DDR_TYPE_DDR4:
  90                 mask = DDR4_STAT_MODE_MASK;
  91                 break;
  92         case DDR_TYPE_DDR3:
  93                 mask = DDR3_STAT_MODE_MASK;
  94                 break;
  95         default:
  96                 printf("Unsupported DDR type 0x%x\n", val);
  97                 return -EINVAL;
  98         }
  99
 100         if (!wait_on_value(mask, DDR_MODE_NORMAL,
 101                            ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
 102                 return -ETIMEDOUT;
 103
 104         return 0;
 105 }
 106
 107 /**
 108  * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
 109  * @dev:                corresponding ddrss device
 110  */
 111 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
 112 {
 113         struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
 114         struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
 115         struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
 116         struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
 117         struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
 118         u32 val;
 119
 120         debug("%s: DDR controller register configuration started\n", __func__);
 121
 122         ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
 123         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
 124         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
 125
 126         ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
 127         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
 128         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
 129         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
 130
 131         ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
 132         ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
 133         ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
 134         ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
 135         ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
 136         ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
 137         ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
 138
 139         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
 140         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
 141         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
 142         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
 143         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
 144         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
 145         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
 146         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
 147         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
 148         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
 149         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
 150         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
 151         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
 152         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
 153
 154         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
 155         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
 156
 157         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
 158         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
 159         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
 160         ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
 161
 162         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
 163         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
 164         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
 165         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
 166         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
 167         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
 168         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
 169         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
 170         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
 171         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
 172         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
 173         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
 174
 175         ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
 176         ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
 177
 178         /* Disable refreshes */
 179         val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
 180         val |= 0x01;
 181         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
 182
 183         debug("%s: DDR controller configuration completed\n", __func__);
 184 }
 185
 186 #define ddrss_phy_writel(off, val)                                      \
 187         do {                                                            \
 188                 ddrss_writel(ddrss->ddrss_phy_cfg, off, val);           \
 189                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 190         } while (0)
 191
 192 #define ddrss_phy_readl(off)                                            \
 193         ({                                                              \
 194                 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off);       \
 195                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 196                 val;                                                    \
 197         })
 198
 199 /**
 200  * am654_ddrss_phy_configuration() - Configure PHY specific registers
 201  * @ddrss:              corresponding ddrss device
 202  */
 203 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
 204 {
 205         struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
 206         struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
 207         struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
 208         struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
 209         struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
 210
 211         debug("%s: DDR phy register configuration started\n", __func__);
 212
 213         ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
 214         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
 215         ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
 216         ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
 217         ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
 218
 219         ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
 220         ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
 221         ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
 222         ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
 223         ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
 224
 225         ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
 226
 227         ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
 228         ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
 229
 230         ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
 231
 232         ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
 233         ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
 234         ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
 235         ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
 236         ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
 237         ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
 238         ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
 239
 240         ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
 241         ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
 242         ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
 243
 244         ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
 245         ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
 246         ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
 247         ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
 248         ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
 249         ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
 250         ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
 251         ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
 252         ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
 253         ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
 254         ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
 255         ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
 256
 257         ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
 258
 259         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
 260         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
 261         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
 262
 263         ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
 264         ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
 265
 266         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
 267         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
 268         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
 269         ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
 270
 271         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, cfg->ddrphy_dx2gcr0);
 272         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR1, cfg->ddrphy_dx2gcr1);
 273         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR2, cfg->ddrphy_dx2gcr2);
 274         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR3, cfg->ddrphy_dx2gcr3);
 275
 276         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, cfg->ddrphy_dx3gcr0);
 277         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR1, cfg->ddrphy_dx3gcr1);
 278         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR2, cfg->ddrphy_dx3gcr2);
 279         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR3, cfg->ddrphy_dx3gcr3);
 280
 281         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
 282         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
 283         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
 284         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
 285
 286         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
 287         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
 288         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
 289         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
 290
 291         ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
 292         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
 293         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
 294         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
 295         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
 296
 297         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
 298
 299         ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
 300         ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
 301         ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
 302         ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
 303         ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
 304
 305         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
 306         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
 307         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
 308
 309         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
 310         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
 311         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
 312
 313         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
 314         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
 315         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
 316
 317         debug("%s: DDR phy register configuration completed\n", __func__);
 318 }
 319
 320 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
 321                                       u32 init_value, u32 sts_mask,
 322                                       u32 err_mask)
 323 {
 324         int ret;
 325
 326         ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
 327
 328         sdelay(5);      /* Delay at least 10 clock cycles */
 329
 330         if (!wait_on_value(sts_mask, sts_mask,
 331                            ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
 332                 return -ETIMEDOUT;
 333
 334         sdelay(16);     /* Delay at least 32 clock cycles */
 335
 336         ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
 337         debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
 338         if (ret & err_mask)
 339                 return -EINVAL;
 340
 341         return 0;
 342 }
 343
 344 int write_leveling(struct am654_ddrss_desc *ddrss)
 345 {
 346         int ret;
 347
 348         debug("%s: Write leveling started\n", __func__);
 349
 350         ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
 351                                          PGSR0_WLERR_MASK);
 352         if (ret) {
 353                 if (ret == -ETIMEDOUT)
 354                         printf("%s: ERROR: Write leveling timedout\n",
 355                                __func__);
 356                 else
 357                         printf("%s:ERROR: Write leveling failed\n", __func__);
 358                 return ret;
 359         }
 360
 361         debug("%s: Write leveling completed\n", __func__);
 362         return 0;
 363 }
 364
 365 int read_dqs_training(struct am654_ddrss_desc *ddrss)
 366 {
 367         int ret;
 368
 369         debug("%s: Read DQS training started\n", __func__);
 370
 371         ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
 372                                          PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
 373         if (ret) {
 374                 if (ret == -ETIMEDOUT)
 375                         printf("%s: ERROR: Read DQS timedout\n", __func__);
 376                 else
 377                         printf("%s:ERROR: Read DQS Gate training failed\n",
 378                                __func__);
 379                 return ret;
 380         }
 381
 382         debug("%s: Read DQS training completed\n", __func__);
 383         return 0;
 384 }
 385
 386 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
 387 {
 388         int ret;
 389
 390         debug("%s: DQS2DQ training started\n", __func__);
 391
 392         ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
 393                                          PGSR0_DQS2DQDONE_MASK,
 394                                          PGSR0_DQS2DQERR_MASK);
 395         if (ret) {
 396                 if (ret == -ETIMEDOUT)
 397                         printf("%s: ERROR: DQS2DQ training timedout\n",
 398                                __func__);
 399                 else
 400                         printf("%s:ERROR: DQS2DQ training failed\n",
 401                                __func__);
 402                 return ret;
 403         }
 404
 405         debug("%s: DQS2DQ training completed\n", __func__);
 406         return 0;
 407 }
 408
 409 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
 410 {
 411         int ret;
 412
 413         debug("%s: Write Leveling adjustment\n", __func__);
 414         ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
 415                                          PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
 416         if (ret) {
 417                 if (ret == -ETIMEDOUT)
 418                         printf("%s:ERROR: Write Leveling adjustment timedout\n",
 419                                __func__);
 420                 else
 421                         printf("%s: ERROR: Write Leveling adjustment failed\n",
 422                                __func__);
 423                 return ret;
 424         }
 425         return 0;
 426 }
 427
 428 int rest_training(struct am654_ddrss_desc *ddrss)
 429 {
 430         int ret;
 431
 432         debug("%s: Rest of the training started\n", __func__);
 433
 434         debug("%s: Read Deskew adjustment\n", __func__);
 435         ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
 436                                          PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
 437         if (ret) {
 438                 if (ret == -ETIMEDOUT)
 439                         printf("%s: ERROR: Read Deskew timedout\n", __func__);
 440                 else
 441                         printf("%s: ERROR: Read Deskew failed\n", __func__);
 442                 return ret;
 443         }
 444
 445         debug("%s: Write Deskew adjustment\n", __func__);
 446         ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
 447                                          PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
 448         if (ret) {
 449                 if (ret == -ETIMEDOUT)
 450                         printf("%s: ERROR: Write Deskew timedout\n", __func__);
 451                 else
 452                         printf("%s: ERROR: Write Deskew failed\n", __func__);
 453                 return ret;
 454         }
 455
 456         debug("%s: Read Eye training\n", __func__);
 457         ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
 458                                          PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
 459         if (ret) {
 460                 if (ret == -ETIMEDOUT)
 461                         printf("%s: ERROR: Read Eye training timedout\n",
 462                                __func__);
 463                 else
 464                         printf("%s: ERROR: Read Eye training failed\n",
 465                                __func__);
 466                 return ret;
 467         }
 468
 469         debug("%s: Write Eye training\n", __func__);
 470         ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
 471                                          PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
 472         if (ret) {
 473                 if (ret == -ETIMEDOUT)
 474                         printf("%s: ERROR: Write Eye training timedout\n",
 475                                __func__);
 476                 else
 477                         printf("%s: ERROR: Write Eye training failed\n",
 478                                __func__);
 479                 return ret;
 480         }
 481         return 0;
 482 }
 483
 484 int VREF_training(struct am654_ddrss_desc *ddrss)
 485 {
 486         int ret;
 487         debug("%s: VREF training\n", __func__);
 488         ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
 489                                          PGSR0_VERR_MASK);
 490         if (ret) {
 491                 if (ret == -ETIMEDOUT)
 492                         printf("%s: ERROR: VREF training timedout\n", __func__);
 493                 else
 494                         printf("%s: ERROR: VREF training failed\n", __func__);
 495                 return ret;
 496         }
 497         return 0;
 498 }
 499
 500 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
 501 {
 502         u32 val;
 503
 504         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
 505         val &= ~0xFF;
 506         val |= 0xF7;
 507         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
 508
 509         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
 510         val &= ~0xFF;
 511         val |= 0xF7;
 512         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
 513
 514         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
 515         val &= ~0xFF;
 516         val |= 0xF7;
 517         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
 518
 519         sdelay(16);
 520         return 0;
 521 }
 522
 523 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
 524 {
 525         u32 val;
 526
 527         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
 528         val &= ~0xFF;
 529         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
 530
 531         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
 532         val &= ~0xFF;
 533         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
 534
 535         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
 536         val &= ~0xFF;
 537         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
 538
 539         sdelay(16);
 540         return 0;
 541 }
 542
 543 int cleanup_training(struct am654_ddrss_desc *ddrss)
 544 {
 545         u32 val;
 546         u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
 547
 548         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 549         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
 550         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
 551         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
 552         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
 553
 554         rddly = dgsl0;
 555         if (dgsl1 < rddly)
 556                 rddly = dgsl1;
 557         if (dgsl2 < rddly)
 558                 rddly = dgsl2;
 559         if (dgsl3 < rddly)
 560                 rddly = dgsl3;
 561
 562         rddly += 5;
 563
 564         /* Update rddly based on dgsl values */
 565         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
 566         val |= (rddly << 20);
 567         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
 568
 569         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
 570         val |= (rddly << 20);
 571         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
 572
 573         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
 574         val |= (rddly << 20);
 575         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
 576
 577         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
 578         val |= (rddly << 20);
 579         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
 580
 581         /*
 582          * Add system latency derived from training back into rd2wr and wr2rd
 583          * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
 584          * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
 585          */
 586
 587         /* Select rank 0 */
 588         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 589
 590         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
 591         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
 592         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
 593         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
 594
 595         /* Find maximum value across all bytes */
 596         rd2wr_wr2rd = dgsl0;
 597         if (dgsl1 > rd2wr_wr2rd)
 598                 rd2wr_wr2rd = dgsl1;
 599         if (dgsl2 > rd2wr_wr2rd)
 600                 rd2wr_wr2rd = dgsl2;
 601         if (dgsl3 > rd2wr_wr2rd)
 602                 rd2wr_wr2rd = dgsl3;
 603
 604         rd2wr_wr2rd >>= 1;
 605
 606         /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
 607         /* Clear VSWCTL.sw_done */
 608         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 609                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
 610         /* Adjust rd2wr */
 611         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 612                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 613                          (rd2wr_wr2rd << 8));
 614         /* Adjust wr2rd */
 615         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 616                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 617                          rd2wr_wr2rd);
 618         /* Set VSWCTL.sw_done */
 619         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 620                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
 621         /* Wait until settings are applied */
 622         while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
 623                 /* Do nothing */
 624         };
 625
 626         debug("%s: Rest of the training completed\n", __func__);
 627         return 0;
 628 }
 629
 630 /**
 631  * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
 632  *                      device attached to ddrss.
 633  * @dev:                corresponding ddrss device
 634  *
 635  * Does all the initialization sequence that is required to get attached
 636  * ddr in a working state. After this point, ddr should be accessible.
 637  * Return: 0 if all went ok, else corresponding error message.
 638  */
 639 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
 640 {
 641         int ret;
 642         u32 val;
 643         struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
 644
 645         debug("Starting DDR initialization...\n");
 646
 647         debug("%s(ddrss=%p)\n", __func__, ddrss);
 648
 649         ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
 650                      reg->ddrss_v2h_ctl_reg);
 651
 652         am654_ddrss_ctrl_configuration(ddrss);
 653
 654         /* Release the reset to the controller */
 655         clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
 656                      SS_CTL_REG_CTL_ARST_MASK);
 657
 658         am654_ddrss_phy_configuration(ddrss);
 659
 660         debug("Starting DDR training...\n");
 661         ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
 662         if (ret) {
 663                 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
 664                 return ret;
 665         }
 666
 667         ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 668                                          PGSR0_DRAM_INIT_MASK, 0);
 669         if (ret) {
 670                 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
 671                 return ret;
 672         }
 673
 674         ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 675         if (ret) {
 676                 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 677                        __func__);
 678                 return ret;
 679         }
 680
 681         val = am654_ddrss_get_type(ddrss);
 682
 683         switch (val) {
 684         case DDR_TYPE_LPDDR4:
 685
 686                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 687                                                  PGSR0_DRAM_INIT_MASK, 0);
 688                 if (ret) {
 689                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 690                                 ret);
 691                         return ret;
 692                 }
 693
 694                 /* must perform DRAM_INIT twice for LPDDR4 */
 695                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 696                                                  PGSR0_DRAM_INIT_MASK, 0);
 697                 if (ret) {
 698                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 699                                 ret);
 700                         return ret;
 701                 }
 702
 703                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 704                 if (ret) {
 705                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 706                                __func__);
 707                         return ret;
 708                 }
 709
 710                 ret = write_leveling(ddrss);
 711                 if (ret)
 712                         return ret;
 713
 714                 ret = enable_dqs_pd(ddrss);
 715                 if (ret)
 716                         return ret;
 717
 718                 ret = read_dqs_training(ddrss);
 719                 if (ret)
 720                         return ret;
 721
 722                 ret = disable_dqs_pd(ddrss);
 723                 if (ret)
 724                         return ret;
 725
 726                 ret = dqs2dq_training(ddrss);
 727                 if (ret)
 728                         return ret;
 729
 730                 ret = write_leveling_adjustment(ddrss);
 731                 if (ret)
 732                         return ret;
 733
 734                 ret = rest_training(ddrss);
 735                 if (ret)
 736                         return ret;
 737
 738                 ret = VREF_training(ddrss);
 739                 if (ret)
 740                         return ret;
 741
 742                 debug("LPDDR4 training complete\n");
 743                 break;
 744
 745         case DDR_TYPE_DDR4:
 746
 747                 debug("Starting DDR4 training\n");
 748
 749                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 750                                                  PGSR0_DRAM_INIT_MASK, 0);
 751                 if (ret) {
 752                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 753                                 ret);
 754                         return ret;
 755                 }
 756
 757                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 758                 if (ret) {
 759                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 760                                __func__);
 761                         return ret;
 762                 }
 763
 764                 ret = write_leveling(ddrss);
 765                 if (ret)
 766                         return ret;
 767
 768                 ret = read_dqs_training(ddrss);
 769                 if (ret)
 770                         return ret;
 771
 772                 ret = write_leveling_adjustment(ddrss);
 773                 if (ret)
 774                         return ret;
 775
 776                 ret = rest_training(ddrss);
 777                 if (ret)
 778                         return ret;
 779
 780                 ret = VREF_training(ddrss);
 781                 if (ret)
 782                         return ret;
 783                 debug("DDR4 training complete\n");
 784                 break;
 785
 786         case DDR_TYPE_DDR3:
 787
 788                 debug("Starting DDR3 training\n");
 789
 790                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 791                                                  PGSR0_DRAM_INIT_MASK, 0);
 792                 if (ret) {
 793                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 794                                 ret);
 795                         return ret;
 796                 }
 797
 798                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 799                 if (ret) {
 800                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 801                                __func__);
 802                         return ret;
 803                 }
 804
 805                 ret = write_leveling(ddrss);
 806                 if (ret)
 807                         return ret;
 808
 809                 ret = enable_dqs_pd(ddrss);
 810                 if (ret)
 811                         return ret;
 812
 813                 ret = read_dqs_training(ddrss);
 814                 if (ret)
 815                         return ret;
 816
 817                 ret = disable_dqs_pd(ddrss);
 818                 if (ret)
 819                         return ret;
 820
 821                 ret = write_leveling_adjustment(ddrss);
 822                 if (ret)
 823                         return ret;
 824
 825                 ret = rest_training(ddrss);
 826                 if (ret)
 827                         return ret;
 828
 829                 debug("DDR3 training complete\n");
 830                 break;
 831         default:
 832                 printf("%s: ERROR: Unsupported DDR type\n", __func__);
 833                 return -EINVAL;
 834         }
 835
 836         ret = cleanup_training(ddrss);
 837         if (ret)
 838                 return ret;
 839
 840         /* Enabling refreshes after training is done */
 841         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
 842                          ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
 843
 844         /* Disable PUBMODE after training is done */
 845         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
 846                          ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
 847
 848         debug("Completed DDR training\n");
 849
 850         return 0;
 851 }
 852
 853 /**
 854  * am654_ddrss_power_on() - Enable power and clocks for ddrss
 855  * @dev:        corresponding ddrss device
 856  *
 857  * Tries to enable all the corresponding clocks to the ddrss and sets it
 858  * to the right frequency and then power on the ddrss.
 859  * Return: 0 if all went ok, else corresponding error message.
 860  */
 861 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
 862 {
 863         int ret;
 864
 865         debug("%s(ddrss=%p)\n", __func__, ddrss);
 866
 867         ret = clk_enable(&ddrss->ddrss_clk);
 868         if (ret) {
 869                 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
 870                 return ret;
 871         }
 872
 873         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 874         if (ret) {
 875                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 876                 return ret;
 877         }
 878
 879         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 880         if (ret) {
 881                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 882                 return ret;
 883         }
 884
 885         /* VTT enable */
 886 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 887         device_get_supply_regulator(ddrss->dev, "vtt-supply",
 888                                     &ddrss->vtt_supply);
 889         ret = regulator_set_value(ddrss->vtt_supply, 3300000);
 890         if (ret == 0)
 891                 debug("VTT regulator enabled\n");
 892 #endif
 893
 894         return 0;
 895 }
 896
 897 /**
 898  * am654_ddrss_ofdata_to_priv() - generate private data from device tree
 899  * @dev:        corresponding ddrss device
 900  *
 901  * Return: 0 if all went ok, else corresponding error message.
 902  */
 903 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
 904 {
 905         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
 906         phys_addr_t reg;
 907         int ret;
 908
 909         debug("%s(dev=%p)\n", __func__, dev);
 910
 911         ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
 912         if (ret) {
 913                 dev_err(dev, "clk_get failed: %d\n", ret);
 914                 return ret;
 915         }
 916
 917         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 918         if (ret) {
 919                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 920                 return ret;
 921         }
 922
 923         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 924         if (ret) {
 925                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 926                 return ret;
 927         }
 928
 929         reg = devfdt_get_addr_name(dev, "ss");
 930         if (reg == FDT_ADDR_T_NONE) {
 931                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 932                 return -EINVAL;
 933         }
 934         ddrss->ddrss_ss_cfg = (void *)reg;
 935
 936         reg = devfdt_get_addr_name(dev, "ctl");
 937         if (reg == FDT_ADDR_T_NONE) {
 938                 dev_err(dev, "No reg property for Controller region\n");
 939                 return -EINVAL;
 940         }
 941         ddrss->ddrss_ctl_cfg = (void *)reg;
 942
 943         reg = devfdt_get_addr_name(dev, "phy");
 944         if (reg == FDT_ADDR_T_NONE) {
 945                 dev_err(dev, "No reg property for PHY region\n");
 946                 return -EINVAL;
 947         }
 948         ddrss->ddrss_phy_cfg = (void *)reg;
 949
 950         ret = dev_read_u32_array(dev, "ti,ss-reg",
 951                                  (u32 *)&ddrss->params.ss_reg,
 952                                  sizeof(ddrss->params.ss_reg) / sizeof(u32));
 953         if (ret) {
 954                 dev_err(dev, "Cannot read ti,ss-reg params\n");
 955                 return ret;
 956         }
 957
 958         ret = dev_read_u32_array(dev, "ti,ctl-reg",
 959                                  (u32 *)&ddrss->params.ctl_reg,
 960                                  sizeof(ddrss->params.ctl_reg) / sizeof(u32));
 961         if (ret) {
 962                 dev_err(dev, "Cannot read ti,ctl-reg params\n");
 963                 return ret;
 964         }
 965
 966         ret = dev_read_u32_array(dev, "ti,ctl-crc",
 967                                  (u32 *)&ddrss->params.ctl_crc,
 968                                  sizeof(ddrss->params.ctl_crc) / sizeof(u32));
 969         if (ret) {
 970                 dev_err(dev, "Cannot read ti,ctl-crc params\n");
 971                 return ret;
 972         }
 973
 974         ret = dev_read_u32_array(dev, "ti,ctl-ecc",
 975                                  (u32 *)&ddrss->params.ctl_ecc,
 976                                  sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
 977         if (ret) {
 978                 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
 979                 return ret;
 980         }
 981
 982         ret = dev_read_u32_array(dev, "ti,ctl-map",
 983                                  (u32 *)&ddrss->params.ctl_map,
 984                                  sizeof(ddrss->params.ctl_map) / sizeof(u32));
 985         if (ret) {
 986                 dev_err(dev, "Cannot read ti,ctl-map params\n");
 987                 return ret;
 988         }
 989
 990         ret = dev_read_u32_array(dev, "ti,ctl-pwr",
 991                                  (u32 *)&ddrss->params.ctl_pwr,
 992                                  sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
 993         if (ret) {
 994                 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
 995                 return ret;
 996         }
 997
 998         ret = dev_read_u32_array(dev, "ti,ctl-timing",
 999                                  (u32 *)&ddrss->params.ctl_timing,
1000                                  sizeof(ddrss->params.ctl_timing) /
1001                                  sizeof(u32));
1002         if (ret) {
1003                 dev_err(dev, "Cannot read ti,ctl-timing params\n");
1004                 return ret;
1005         }
1006
1007         ret = dev_read_u32_array(dev, "ti,phy-cfg",
1008                                  (u32 *)&ddrss->params.phy_cfg,
1009                                  sizeof(ddrss->params.phy_cfg) / sizeof(u32));
1010         if (ret) {
1011                 dev_err(dev, "Cannot read ti,phy-cfg params\n");
1012                 return ret;
1013         }
1014
1015         ret = dev_read_u32_array(dev, "ti,phy-ctl",
1016                                  (u32 *)&ddrss->params.phy_ctrl,
1017                                  sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
1018         if (ret) {
1019                 dev_err(dev, "Cannot read ti,phy-ctl params\n");
1020                 return ret;
1021         }
1022
1023         ret = dev_read_u32_array(dev, "ti,phy-ioctl",
1024                                  (u32 *)&ddrss->params.phy_ioctl,
1025                                  sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
1026         if (ret) {
1027                 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
1028                 return ret;
1029         }
1030
1031         ret = dev_read_u32_array(dev, "ti,phy-timing",
1032                                  (u32 *)&ddrss->params.phy_timing,
1033                                  sizeof(ddrss->params.phy_timing) /
1034                                  sizeof(u32));
1035         if (ret) {
1036                 dev_err(dev, "Cannot read ti,phy-timing params\n");
1037                 return ret;
1038         }
1039
1040         ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
1041                                  sizeof(ddrss->params.phy_zq) / sizeof(u32));
1042         if (ret) {
1043                 dev_err(dev, "Cannot read ti,phy-zq params\n");
1044                 return ret;
1045         }
1046
1047         return ret;
1048 }
1049
1050 /**
1051  * am654_ddrss_probe() - Basic probe
1052  * @dev:        corresponding ddrss device
1053  *
1054  * Return: 0 if all went ok, else corresponding error message
1055  */
1056 static int am654_ddrss_probe(struct udevice *dev)
1057 {
1058         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1059         int ret;
1060
1061         debug("%s(dev=%p)\n", __func__, dev);
1062
1063         ret = am654_ddrss_ofdata_to_priv(dev);
1064         if (ret)
1065                 return ret;
1066
1067         ddrss->dev = dev;
1068         ret = am654_ddrss_power_on(ddrss);
1069         if (ret)
1070                 return ret;
1071
1072         ret = am654_ddrss_init(ddrss);
1073
1074         return ret;
1075 }
1076
1077 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1078 {
1079         return 0;
1080 }
1081
1082 static struct ram_ops am654_ddrss_ops = {
1083         .get_info = am654_ddrss_get_info,
1084 };
1085
1086 static const struct udevice_id am654_ddrss_ids[] = {
1087         { .compatible = "ti,am654-ddrss" },
1088         { }
1089 };
1090
1091 U_BOOT_DRIVER(am654_ddrss) = {
1092         .name = "am654_ddrss",
1093         .id = UCLASS_RAM,
1094         .of_match = am654_ddrss_ids,
1095         .ops = &am654_ddrss_ops,
1096         .probe = am654_ddrss_probe,
1097         .priv_auto      = sizeof(struct am654_ddrss_desc),
1098 };