1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments' AM654 DDRSS driver
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
15 #include <power-domain.h>
16 #include <asm/arch/sys_proto.h>
17 #include <dm/device_compat.h>
18 #include <power/regulator.h>
19 #include "k3-am654-ddrss.h"
23 /* DDRSS PHY configuration register fixed values */
24 #define DDRSS_DDRPHY_RANKIDR_RANK0 0
27 * struct am654_ddrss_desc - Description of ddrss integration.
28 * @dev: DDRSS device pointer
29 * @ddrss_ss_cfg: DDRSS wrapper logic region base address
30 * @ddrss_ctl_cfg: DDRSS controller region base address
31 * @ddrss_phy_cfg: DDRSS PHY region base address
32 * @ddrss_clk: DDRSS clock description
33 * @vtt_supply: VTT Supply regulator
34 * @ddrss_pwrdmn: DDRSS power domain description
35 * @params: SDRAM configuration parameters
37 struct am654_ddrss_desc {
39 void __iomem *ddrss_ss_cfg;
40 void __iomem *ddrss_ctl_cfg;
41 void __iomem *ddrss_phy_cfg;
43 struct udevice *vtt_supply;
44 struct power_domain ddrcfg_pwrdmn;
45 struct power_domain ddrdata_pwrdmn;
46 struct ddrss_params params;
49 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
51 return readl(addr + offset);
54 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
57 debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
58 writel(data, addr + offset);
61 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
62 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
64 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
66 return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
70 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
72 * After detecting the DDR type this function will pause until the
73 * initialization is complete. Each DDR type has mask of multiple bits.
74 * The size of the field depends on the DDR Type. If the initialization
75 * does not complete and error will be returned and will cause the boot to halt.
78 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
82 val = am654_ddrss_get_type(ddrss);
87 mask = DDR4_STAT_MODE_MASK;
90 mask = DDR3_STAT_MODE_MASK;
93 printf("Unsupported DDR type 0x%x\n", val);
97 if (!wait_on_value(mask, DDR_MODE_NORMAL,
98 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
105 * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
106 * @dev: corresponding ddrss device
108 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
110 struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
111 struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
112 struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
113 struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
114 struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
117 debug("%s: DDR controller register configuration started\n", __func__);
119 ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
120 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
121 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
123 ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
124 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
125 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
126 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
128 ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
129 ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
130 ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
131 ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
132 ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
133 ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
134 ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
136 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
137 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
138 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
139 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
140 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
141 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
142 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
143 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
144 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
145 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
146 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
147 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
148 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
149 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
151 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
152 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
154 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
155 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
156 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
157 ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
159 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
160 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
161 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
162 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
163 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
164 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
165 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
166 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
167 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
168 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
169 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
170 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
172 ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
173 ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
175 /* Disable refreshes */
176 val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
178 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
180 debug("%s: DDR controller configuration completed\n", __func__);
183 #define ddrss_phy_writel(off, val) \
185 ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
186 sdelay(10); /* Delay at least 20 clock cycles */ \
189 #define ddrss_phy_readl(off) \
191 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
192 sdelay(10); /* Delay at least 20 clock cycles */ \
197 * am654_ddrss_phy_configuration() - Configure PHY specific registers
198 * @ddrss: corresponding ddrss device
200 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
202 struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
203 struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
204 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
205 struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
206 struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
208 debug("%s: DDR phy register configuration started\n", __func__);
210 ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
211 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
212 ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
213 ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
214 ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
216 ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
217 ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
218 ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
219 ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
220 ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
222 ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
224 ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
225 ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
227 ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
229 ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
230 ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
231 ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
232 ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
233 ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
234 ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
235 ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
237 ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
238 ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
239 ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
241 ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
242 ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
243 ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
244 ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
245 ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
246 ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
247 ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
248 ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
249 ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
250 ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
251 ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
252 ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
254 ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
256 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
257 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
258 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
260 ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
261 ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
263 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
264 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
265 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
266 ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
268 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, cfg->ddrphy_dx2gcr0);
269 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR1, cfg->ddrphy_dx2gcr1);
270 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR2, cfg->ddrphy_dx2gcr2);
271 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR3, cfg->ddrphy_dx2gcr3);
273 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, cfg->ddrphy_dx3gcr0);
274 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR1, cfg->ddrphy_dx3gcr1);
275 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR2, cfg->ddrphy_dx3gcr2);
276 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR3, cfg->ddrphy_dx3gcr3);
278 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
279 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
280 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
281 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
283 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
284 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
285 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
286 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
288 ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
289 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
290 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
291 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
292 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
294 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
296 ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
297 ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
298 ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
299 ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
300 ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
302 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
303 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
304 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
306 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
307 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
308 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
310 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
311 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
312 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
314 debug("%s: DDR phy register configuration completed\n", __func__);
317 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
318 u32 init_value, u32 sts_mask,
323 ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
325 sdelay(5); /* Delay at least 10 clock cycles */
327 if (!wait_on_value(sts_mask, sts_mask,
328 ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
331 sdelay(16); /* Delay at least 32 clock cycles */
333 ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
334 debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
341 int write_leveling(struct am654_ddrss_desc *ddrss)
345 debug("%s: Write leveling started\n", __func__);
347 ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
350 if (ret == -ETIMEDOUT)
351 printf("%s: ERROR: Write leveling timedout\n",
354 printf("%s:ERROR: Write leveling failed\n", __func__);
358 debug("%s: Write leveling completed\n", __func__);
362 int read_dqs_training(struct am654_ddrss_desc *ddrss)
366 debug("%s: Read DQS training started\n", __func__);
368 ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
369 PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
371 if (ret == -ETIMEDOUT)
372 printf("%s: ERROR: Read DQS timedout\n", __func__);
374 printf("%s:ERROR: Read DQS Gate training failed\n",
379 debug("%s: Read DQS training completed\n", __func__);
383 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
387 debug("%s: DQS2DQ training started\n", __func__);
389 ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
390 PGSR0_DQS2DQDONE_MASK,
391 PGSR0_DQS2DQERR_MASK);
393 if (ret == -ETIMEDOUT)
394 printf("%s: ERROR: DQS2DQ training timedout\n",
397 printf("%s:ERROR: DQS2DQ training failed\n",
402 debug("%s: DQS2DQ training completed\n", __func__);
406 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
410 debug("%s: Write Leveling adjustment\n", __func__);
411 ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
412 PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
414 if (ret == -ETIMEDOUT)
415 printf("%s:ERROR: Write Leveling adjustment timedout\n",
418 printf("%s: ERROR: Write Leveling adjustment failed\n",
425 int rest_training(struct am654_ddrss_desc *ddrss)
429 debug("%s: Rest of the training started\n", __func__);
431 debug("%s: Read Deskew adjustment\n", __func__);
432 ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
433 PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
435 if (ret == -ETIMEDOUT)
436 printf("%s: ERROR: Read Deskew timedout\n", __func__);
438 printf("%s: ERROR: Read Deskew failed\n", __func__);
442 debug("%s: Write Deskew adjustment\n", __func__);
443 ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
444 PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
446 if (ret == -ETIMEDOUT)
447 printf("%s: ERROR: Write Deskew timedout\n", __func__);
449 printf("%s: ERROR: Write Deskew failed\n", __func__);
453 debug("%s: Read Eye training\n", __func__);
454 ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
455 PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
457 if (ret == -ETIMEDOUT)
458 printf("%s: ERROR: Read Eye training timedout\n",
461 printf("%s: ERROR: Read Eye training failed\n",
466 debug("%s: Write Eye training\n", __func__);
467 ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
468 PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
470 if (ret == -ETIMEDOUT)
471 printf("%s: ERROR: Write Eye training timedout\n",
474 printf("%s: ERROR: Write Eye training failed\n",
481 int VREF_training(struct am654_ddrss_desc *ddrss)
484 debug("%s: VREF training\n", __func__);
485 ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
488 if (ret == -ETIMEDOUT)
489 printf("%s: ERROR: VREF training timedout\n", __func__);
491 printf("%s: ERROR: VREF training failed\n", __func__);
497 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
501 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
504 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
506 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
509 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
511 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
514 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
520 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
524 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
526 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
528 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
530 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
532 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
534 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
540 int cleanup_training(struct am654_ddrss_desc *ddrss)
543 u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
545 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
546 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
547 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
548 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
549 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
561 /* Update rddly based on dgsl values */
562 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
563 val |= (rddly << 20);
564 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
566 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
567 val |= (rddly << 20);
568 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
570 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
571 val |= (rddly << 20);
572 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
574 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
575 val |= (rddly << 20);
576 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
579 * Add system latency derived from training back into rd2wr and wr2rd
580 * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
581 * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
585 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
587 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
588 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
589 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
590 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
592 /* Find maximum value across all bytes */
594 if (dgsl1 > rd2wr_wr2rd)
596 if (dgsl2 > rd2wr_wr2rd)
598 if (dgsl3 > rd2wr_wr2rd)
603 /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
604 /* Clear VSWCTL.sw_done */
605 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
606 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
608 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
609 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
612 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
613 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
615 /* Set VSWCTL.sw_done */
616 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
617 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
618 /* Wait until settings are applied */
619 while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
623 debug("%s: Rest of the training completed\n", __func__);
628 * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
629 * device attached to ddrss.
630 * @dev: corresponding ddrss device
632 * Does all the initialization sequence that is required to get attached
633 * ddr in a working state. After this point, ddr should be accessible.
634 * Return: 0 if all went ok, else corresponding error message.
636 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
640 struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
642 debug("Starting DDR initialization...\n");
644 debug("%s(ddrss=%p)\n", __func__, ddrss);
646 ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
647 reg->ddrss_v2h_ctl_reg);
649 am654_ddrss_ctrl_configuration(ddrss);
651 /* Release the reset to the controller */
652 clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
653 SS_CTL_REG_CTL_ARST_MASK);
655 am654_ddrss_phy_configuration(ddrss);
657 debug("Starting DDR training...\n");
658 ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
660 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
664 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
665 PGSR0_DRAM_INIT_MASK, 0);
667 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
671 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
673 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
678 val = am654_ddrss_get_type(ddrss);
681 case DDR_TYPE_LPDDR4:
683 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
684 PGSR0_DRAM_INIT_MASK, 0);
686 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
691 /* must perform DRAM_INIT twice for LPDDR4 */
692 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
693 PGSR0_DRAM_INIT_MASK, 0);
695 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
700 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
702 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
707 ret = write_leveling(ddrss);
711 ret = enable_dqs_pd(ddrss);
715 ret = read_dqs_training(ddrss);
719 ret = disable_dqs_pd(ddrss);
723 ret = dqs2dq_training(ddrss);
727 ret = write_leveling_adjustment(ddrss);
731 ret = rest_training(ddrss);
735 ret = VREF_training(ddrss);
739 debug("LPDDR4 training complete\n");
744 debug("Starting DDR4 training\n");
746 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
747 PGSR0_DRAM_INIT_MASK, 0);
749 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
754 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
756 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
761 ret = write_leveling(ddrss);
765 ret = read_dqs_training(ddrss);
769 ret = write_leveling_adjustment(ddrss);
773 ret = rest_training(ddrss);
777 ret = VREF_training(ddrss);
780 debug("DDR4 training complete\n");
785 debug("Starting DDR3 training\n");
787 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
788 PGSR0_DRAM_INIT_MASK, 0);
790 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
795 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
797 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
802 ret = write_leveling(ddrss);
806 ret = enable_dqs_pd(ddrss);
810 ret = read_dqs_training(ddrss);
814 ret = disable_dqs_pd(ddrss);
818 ret = write_leveling_adjustment(ddrss);
822 ret = rest_training(ddrss);
826 debug("DDR3 training complete\n");
829 printf("%s: ERROR: Unsupported DDR type\n", __func__);
833 ret = cleanup_training(ddrss);
837 /* Enabling refreshes after training is done */
838 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
839 ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
841 /* Disable PUBMODE after training is done */
842 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
843 ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
845 debug("Completed DDR training\n");
851 * am654_ddrss_power_on() - Enable power and clocks for ddrss
852 * @dev: corresponding ddrss device
854 * Tries to enable all the corresponding clocks to the ddrss and sets it
855 * to the right frequency and then power on the ddrss.
856 * Return: 0 if all went ok, else corresponding error message.
858 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
862 debug("%s(ddrss=%p)\n", __func__, ddrss);
864 ret = clk_enable(&ddrss->ddrss_clk);
866 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
870 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
872 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
876 ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
878 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
883 #if CONFIG_IS_ENABLED(DM_REGULATOR)
884 device_get_supply_regulator(ddrss->dev, "vtt-supply",
886 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
888 debug("VTT regulator enabled\n");
895 * am654_ddrss_ofdata_to_priv() - generate private data from device tree
896 * @dev: corresponding ddrss device
898 * Return: 0 if all went ok, else corresponding error message.
900 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
902 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
906 debug("%s(dev=%p)\n", __func__, dev);
908 ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
910 dev_err(dev, "clk_get failed: %d\n", ret);
914 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
916 dev_err(dev, "power_domain_get() failed: %d\n", ret);
920 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
922 dev_err(dev, "power_domain_get() failed: %d\n", ret);
926 reg = devfdt_get_addr_name(dev, "ss");
927 if (reg == FDT_ADDR_T_NONE) {
928 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
931 ddrss->ddrss_ss_cfg = (void *)reg;
933 reg = devfdt_get_addr_name(dev, "ctl");
934 if (reg == FDT_ADDR_T_NONE) {
935 dev_err(dev, "No reg property for Controller region\n");
938 ddrss->ddrss_ctl_cfg = (void *)reg;
940 reg = devfdt_get_addr_name(dev, "phy");
941 if (reg == FDT_ADDR_T_NONE) {
942 dev_err(dev, "No reg property for PHY region\n");
945 ddrss->ddrss_phy_cfg = (void *)reg;
947 ret = dev_read_u32_array(dev, "ti,ss-reg",
948 (u32 *)&ddrss->params.ss_reg,
949 sizeof(ddrss->params.ss_reg) / sizeof(u32));
951 dev_err(dev, "Cannot read ti,ss-reg params\n");
955 ret = dev_read_u32_array(dev, "ti,ctl-reg",
956 (u32 *)&ddrss->params.ctl_reg,
957 sizeof(ddrss->params.ctl_reg) / sizeof(u32));
959 dev_err(dev, "Cannot read ti,ctl-reg params\n");
963 ret = dev_read_u32_array(dev, "ti,ctl-crc",
964 (u32 *)&ddrss->params.ctl_crc,
965 sizeof(ddrss->params.ctl_crc) / sizeof(u32));
967 dev_err(dev, "Cannot read ti,ctl-crc params\n");
971 ret = dev_read_u32_array(dev, "ti,ctl-ecc",
972 (u32 *)&ddrss->params.ctl_ecc,
973 sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
975 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
979 ret = dev_read_u32_array(dev, "ti,ctl-map",
980 (u32 *)&ddrss->params.ctl_map,
981 sizeof(ddrss->params.ctl_map) / sizeof(u32));
983 dev_err(dev, "Cannot read ti,ctl-map params\n");
987 ret = dev_read_u32_array(dev, "ti,ctl-pwr",
988 (u32 *)&ddrss->params.ctl_pwr,
989 sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
991 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
995 ret = dev_read_u32_array(dev, "ti,ctl-timing",
996 (u32 *)&ddrss->params.ctl_timing,
997 sizeof(ddrss->params.ctl_timing) /
1000 dev_err(dev, "Cannot read ti,ctl-timing params\n");
1004 ret = dev_read_u32_array(dev, "ti,phy-cfg",
1005 (u32 *)&ddrss->params.phy_cfg,
1006 sizeof(ddrss->params.phy_cfg) / sizeof(u32));
1008 dev_err(dev, "Cannot read ti,phy-cfg params\n");
1012 ret = dev_read_u32_array(dev, "ti,phy-ctl",
1013 (u32 *)&ddrss->params.phy_ctrl,
1014 sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
1016 dev_err(dev, "Cannot read ti,phy-ctl params\n");
1020 ret = dev_read_u32_array(dev, "ti,phy-ioctl",
1021 (u32 *)&ddrss->params.phy_ioctl,
1022 sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
1024 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
1028 ret = dev_read_u32_array(dev, "ti,phy-timing",
1029 (u32 *)&ddrss->params.phy_timing,
1030 sizeof(ddrss->params.phy_timing) /
1033 dev_err(dev, "Cannot read ti,phy-timing params\n");
1037 ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
1038 sizeof(ddrss->params.phy_zq) / sizeof(u32));
1040 dev_err(dev, "Cannot read ti,phy-zq params\n");
1048 * am654_ddrss_probe() - Basic probe
1049 * @dev: corresponding ddrss device
1051 * Return: 0 if all went ok, else corresponding error message
1053 static int am654_ddrss_probe(struct udevice *dev)
1055 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1058 debug("%s(dev=%p)\n", __func__, dev);
1060 ret = am654_ddrss_ofdata_to_priv(dev);
1065 ret = am654_ddrss_power_on(ddrss);
1069 ret = am654_ddrss_init(ddrss);
1074 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1079 static struct ram_ops am654_ddrss_ops = {
1080 .get_info = am654_ddrss_get_info,
1083 static const struct udevice_id am654_ddrss_ids[] = {
1084 { .compatible = "ti,am654-ddrss" },
1088 U_BOOT_DRIVER(am654_ddrss) = {
1089 .name = "am654_ddrss",
1091 .of_match = am654_ddrss_ids,
1092 .ops = &am654_ddrss_ops,
1093 .probe = am654_ddrss_probe,
1094 .priv_auto = sizeof(struct am654_ddrss_desc),