drivers/ram/k3-am654-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' AM654 DDRSS driver
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <power-domain.h>
  15 #include <dm.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <power/regulator.h>
  18 #include "k3-am654-ddrss.h"
  19
  20 #define LDELAY 10000
  21
  22 /* DDRSS PHY configuration register fixed values */
  23 #define DDRSS_DDRPHY_RANKIDR_RANK0      0
  24
  25 /**
  26  * struct am654_ddrss_desc - Description of ddrss integration.
  27  * @dev:                DDRSS device pointer
  28  * @ddrss_ss_cfg:       DDRSS wrapper logic region base address
  29  * @ddrss_ctl_cfg:      DDRSS controller region base address
  30  * @ddrss_phy_cfg:      DDRSS PHY region base address
  31  * @ddrss_clk:          DDRSS clock description
  32  * @vtt_supply:         VTT Supply regulator
  33  * @ddrss_pwrdmn:       DDRSS power domain description
  34  * @params:             SDRAM configuration parameters
  35  */
  36 struct am654_ddrss_desc {
  37         struct udevice *dev;
  38         void __iomem *ddrss_ss_cfg;
  39         void __iomem *ddrss_ctl_cfg;
  40         void __iomem *ddrss_phy_cfg;
  41         struct clk ddrss_clk;
  42         struct udevice *vtt_supply;
  43         struct power_domain ddrcfg_pwrdmn;
  44         struct power_domain ddrdata_pwrdmn;
  45         struct ddrss_params params;
  46 };
  47
  48 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
  49 {
  50         return readl(addr + offset);
  51 }
  52
  53 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
  54                                 u32 data)
  55 {
  56         debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
  57         writel(data, addr + offset);
  58 }
  59
  60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
  61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
  62
  63 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
  64 {
  65         return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
  66 }
  67
  68 /**
  69  * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
  70  *
  71  * After detecting the DDR type this function will pause until the
  72  * initialization is complete. Each DDR type has mask of multiple bits.
  73  * The size of the field depends on the DDR Type. If the initialization
  74  * does not complete and error will be returned and will cause the boot to halt.
  75  *
  76  */
  77 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
  78 {
  79         u32 val, mask;
  80
  81         val = am654_ddrss_get_type(ddrss);
  82
  83         switch (val) {
  84         case DDR_TYPE_LPDDR4:
  85         case DDR_TYPE_DDR4:
  86                 mask = DDR4_STAT_MODE_MASK;
  87                 break;
  88         case DDR_TYPE_DDR3:
  89                 mask = DDR3_STAT_MODE_MASK;
  90                 break;
  91         default:
  92                 printf("Unsupported DDR type 0x%x\n", val);
  93                 return -EINVAL;
  94         }
  95
  96         if (!wait_on_value(mask, DDR_MODE_NORMAL,
  97                            ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
  98                 return -ETIMEDOUT;
  99
 100         return 0;
 101 }
 102
 103 /**
 104  * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
 105  * @dev:                corresponding ddrss device
 106  */
 107 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
 108 {
 109         struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
 110         struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
 111         struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
 112         struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
 113         struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
 114         u32 val;
 115
 116         debug("%s: DDR controller register configuration started\n", __func__);
 117
 118         ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
 119         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
 120         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
 121
 122         ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
 123         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
 124         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
 125         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
 126
 127         ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
 128         ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
 129         ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
 130         ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
 131         ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
 132         ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
 133         ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
 134
 135         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
 136         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
 137         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
 138         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
 139         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
 140         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
 141         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
 142         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
 143         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
 144         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
 145         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
 146         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
 147         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
 148         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
 149
 150         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
 151         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
 152
 153         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
 154         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
 155         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
 156         ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
 157
 158         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
 159         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
 160         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
 161         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
 162         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
 163         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
 164         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
 165         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
 166         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
 167         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
 168         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
 169         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
 170
 171         ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
 172         ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
 173
 174         /* Disable refreshes */
 175         val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
 176         val |= 0x01;
 177         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
 178
 179         debug("%s: DDR controller configuration completed\n", __func__);
 180 }
 181
 182 #define ddrss_phy_writel(off, val)                                      \
 183         do {                                                            \
 184                 ddrss_writel(ddrss->ddrss_phy_cfg, off, val);           \
 185                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 186         } while (0)
 187
 188 #define ddrss_phy_readl(off)                                            \
 189         ({                                                              \
 190                 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off);       \
 191                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 192                 val;                                                    \
 193         })
 194
 195 /**
 196  * am654_ddrss_phy_configuration() - Configure PHY specific registers
 197  * @ddrss:              corresponding ddrss device
 198  */
 199 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
 200 {
 201         struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
 202         struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
 203         struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
 204         struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
 205         struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
 206
 207         debug("%s: DDR phy register configuration started\n", __func__);
 208
 209         ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
 210         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
 211         ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
 212         ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
 213         ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
 214
 215         ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
 216         ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
 217         ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
 218         ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
 219         ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
 220
 221         ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
 222
 223         ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
 224         ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
 225
 226         ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
 227
 228         ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
 229         ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
 230         ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
 231         ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
 232         ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
 233         ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
 234         ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
 235
 236         ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
 237         ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
 238         ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
 239
 240         ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
 241         ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
 242         ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
 243         ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
 244         ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
 245         ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
 246         ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
 247         ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
 248         ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
 249         ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
 250         ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
 251         ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
 252
 253         ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
 254
 255         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
 256         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
 257         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
 258
 259         ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
 260         ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
 261
 262         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
 263         ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
 264
 265         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
 266         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
 267         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
 268         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
 269
 270         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
 271         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
 272         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
 273         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
 274
 275         ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
 276         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
 277         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
 278         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
 279         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
 280
 281         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
 282
 283         ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
 284         ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
 285         ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
 286         ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
 287         ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
 288
 289         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
 290         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
 291         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
 292
 293         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
 294         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
 295         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
 296
 297         debug("%s: DDR phy register configuration completed\n", __func__);
 298 }
 299
 300 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
 301                                       u32 init_value, u32 sts_mask,
 302                                       u32 err_mask)
 303 {
 304         int ret;
 305
 306         ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
 307
 308         sdelay(5);      /* Delay at least 10 clock cycles */
 309
 310         if (!wait_on_value(sts_mask, sts_mask,
 311                            ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
 312                 return -ETIMEDOUT;
 313
 314         sdelay(16);     /* Delay at least 32 clock cycles */
 315
 316         ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
 317         debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
 318         if (ret & err_mask)
 319                 return -EINVAL;
 320
 321         return 0;
 322 }
 323
 324 int write_leveling(struct am654_ddrss_desc *ddrss)
 325 {
 326         int ret;
 327
 328         debug("%s: Write leveling started\n", __func__);
 329
 330         ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
 331                                          PGSR0_WLERR_MASK);
 332         if (ret) {
 333                 if (ret == -ETIMEDOUT)
 334                         printf("%s: ERROR: Write leveling timedout\n",
 335                                __func__);
 336                 else
 337                         printf("%s:ERROR: Write leveling failed\n", __func__);
 338                 return ret;
 339         }
 340
 341         debug("%s: Write leveling completed\n", __func__);
 342         return 0;
 343 }
 344
 345 int read_dqs_training(struct am654_ddrss_desc *ddrss)
 346 {
 347         int ret;
 348
 349         debug("%s: Read DQS training started\n", __func__);
 350
 351         ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
 352                                          PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
 353         if (ret) {
 354                 if (ret == -ETIMEDOUT)
 355                         printf("%s: ERROR: Read DQS timedout\n", __func__);
 356                 else
 357                         printf("%s:ERROR: Read DQS Gate training failed\n",
 358                                __func__);
 359                 return ret;
 360         }
 361
 362         debug("%s: Read DQS training completed\n", __func__);
 363         return 0;
 364 }
 365
 366 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
 367 {
 368         int ret;
 369
 370         debug("%s: DQS2DQ training started\n", __func__);
 371
 372         ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
 373                                          PGSR0_DQS2DQDONE_MASK,
 374                                          PGSR0_DQS2DQERR_MASK);
 375         if (ret) {
 376                 if (ret == -ETIMEDOUT)
 377                         printf("%s: ERROR: DQS2DQ training timedout\n",
 378                                __func__);
 379                 else
 380                         printf("%s:ERROR: DQS2DQ training failed\n",
 381                                __func__);
 382                 return ret;
 383         }
 384
 385         debug("%s: DQS2DQ training completed\n", __func__);
 386         return 0;
 387 }
 388
 389 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
 390 {
 391         int ret;
 392
 393         debug("%s: Write Leveling adjustment\n", __func__);
 394         ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
 395                                          PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
 396         if (ret) {
 397                 if (ret == -ETIMEDOUT)
 398                         printf("%s:ERROR: Write Leveling adjustment timedout\n",
 399                                __func__);
 400                 else
 401                         printf("%s: ERROR: Write Leveling adjustment failed\n",
 402                                __func__);
 403                 return ret;
 404         }
 405         return 0;
 406 }
 407
 408 int rest_training(struct am654_ddrss_desc *ddrss)
 409 {
 410         int ret;
 411
 412         debug("%s: Rest of the training started\n", __func__);
 413
 414         debug("%s: Read Deskew adjustment\n", __func__);
 415         ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
 416                                          PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
 417         if (ret) {
 418                 if (ret == -ETIMEDOUT)
 419                         printf("%s: ERROR: Read Deskew timedout\n", __func__);
 420                 else
 421                         printf("%s: ERROR: Read Deskew failed\n", __func__);
 422                 return ret;
 423         }
 424
 425         debug("%s: Write Deskew adjustment\n", __func__);
 426         ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
 427                                          PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
 428         if (ret) {
 429                 if (ret == -ETIMEDOUT)
 430                         printf("%s: ERROR: Write Deskew timedout\n", __func__);
 431                 else
 432                         printf("%s: ERROR: Write Deskew failed\n", __func__);
 433                 return ret;
 434         }
 435
 436         debug("%s: Read Eye training\n", __func__);
 437         ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
 438                                          PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
 439         if (ret) {
 440                 if (ret == -ETIMEDOUT)
 441                         printf("%s: ERROR: Read Eye training timedout\n",
 442                                __func__);
 443                 else
 444                         printf("%s: ERROR: Read Eye training failed\n",
 445                                __func__);
 446                 return ret;
 447         }
 448
 449         debug("%s: Write Eye training\n", __func__);
 450         ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
 451                                          PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
 452         if (ret) {
 453                 if (ret == -ETIMEDOUT)
 454                         printf("%s: ERROR: Write Eye training timedout\n",
 455                                __func__);
 456                 else
 457                         printf("%s: ERROR: Write Eye training failed\n",
 458                                __func__);
 459                 return ret;
 460         }
 461         return 0;
 462 }
 463
 464 int VREF_training(struct am654_ddrss_desc *ddrss)
 465 {
 466         int ret;
 467         debug("%s: VREF training\n", __func__);
 468         ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
 469                                          PGSR0_VERR_MASK);
 470         if (ret) {
 471                 if (ret == -ETIMEDOUT)
 472                         printf("%s: ERROR: VREF training timedout\n", __func__);
 473                 else
 474                         printf("%s: ERROR: VREF training failed\n", __func__);
 475                 return ret;
 476         }
 477         return 0;
 478 }
 479
 480 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
 481 {
 482         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x012640F7);
 483         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x012640F7);
 484         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x012640F7);
 485         sdelay(16);
 486         return 0;
 487 }
 488
 489 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
 490 {
 491         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x01264000);
 492         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x01264000);
 493         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x01264000);
 494         sdelay(16);
 495         return 0;
 496 }
 497
 498 int cleanup_training(struct am654_ddrss_desc *ddrss)
 499 {
 500         u32 val;
 501         u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
 502
 503         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 504         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
 505         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
 506         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
 507         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
 508
 509         rddly = dgsl0;
 510         if (dgsl1 < rddly)
 511                 rddly = dgsl1;
 512         if (dgsl2 < rddly)
 513                 rddly = dgsl2;
 514         if (dgsl3 < rddly)
 515                 rddly = dgsl3;
 516
 517         rddly += 5;
 518
 519         /* Update rddly based on dgsl values */
 520         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
 521         val |= (rddly << 20);
 522         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
 523
 524         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
 525         val |= (rddly << 20);
 526         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
 527
 528         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
 529         val |= (rddly << 20);
 530         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
 531
 532         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
 533         val |= (rddly << 20);
 534         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
 535
 536         /*
 537          * Add system latency derived from training back into rd2wr and wr2rd
 538          * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
 539          * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
 540          */
 541
 542         /* Select rank 0 */
 543         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 544
 545         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
 546         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
 547         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
 548         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
 549
 550         /* Find maximum value across all bytes */
 551         rd2wr_wr2rd = dgsl0;
 552         if (dgsl1 > rd2wr_wr2rd)
 553                 rd2wr_wr2rd = dgsl1;
 554         if (dgsl2 > rd2wr_wr2rd)
 555                 rd2wr_wr2rd = dgsl2;
 556         if (dgsl3 > rd2wr_wr2rd)
 557                 rd2wr_wr2rd = dgsl3;
 558
 559         rd2wr_wr2rd >>= 1;
 560
 561         /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
 562         /* Clear VSWCTL.sw_done */
 563         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 564                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
 565         /* Adjust rd2wr */
 566         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 567                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 568                          (rd2wr_wr2rd << 8));
 569         /* Adjust wr2rd */
 570         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 571                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 572                          rd2wr_wr2rd);
 573         /* Set VSWCTL.sw_done */
 574         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 575                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
 576         /* Wait until settings are applied */
 577         while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
 578                 /* Do nothing */
 579         };
 580
 581         debug("%s: Rest of the training completed\n", __func__);
 582         return 0;
 583 }
 584
 585 /**
 586  * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
 587  *                      device attached to ddrss.
 588  * @dev:                corresponding ddrss device
 589  *
 590  * Does all the initialization sequence that is required to get attached
 591  * ddr in a working state. After this point, ddr should be accessible.
 592  * Return: 0 if all went ok, else corresponding error message.
 593  */
 594 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
 595 {
 596         int ret;
 597         u32 val;
 598
 599         debug("Starting DDR initialization...\n");
 600
 601         debug("%s(ddrss=%p)\n", __func__, ddrss);
 602
 603         ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
 604
 605         am654_ddrss_ctrl_configuration(ddrss);
 606
 607         /* Release the reset to the controller */
 608         clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
 609                      SS_CTL_REG_CTL_ARST_MASK);
 610
 611         am654_ddrss_phy_configuration(ddrss);
 612
 613         debug("Starting DDR training...\n");
 614         ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
 615         if (ret) {
 616                 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
 617                 return ret;
 618         }
 619
 620         ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 621                                          PGSR0_DRAM_INIT_MASK, 0);
 622         if (ret) {
 623                 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
 624                 return ret;
 625         }
 626
 627         ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 628         if (ret) {
 629                 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 630                        __func__);
 631                 return ret;
 632         }
 633
 634         val = am654_ddrss_get_type(ddrss);
 635
 636         switch (val) {
 637         case DDR_TYPE_LPDDR4:
 638
 639                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 640                                                  PGSR0_DRAM_INIT_MASK, 0);
 641                 if (ret) {
 642                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 643                                 ret);
 644                         return ret;
 645                 }
 646
 647                 /* must perform DRAM_INIT twice for LPDDR4 */
 648                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 649                                                  PGSR0_DRAM_INIT_MASK, 0);
 650                 if (ret) {
 651                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 652                                 ret);
 653                         return ret;
 654                 }
 655
 656                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 657                 if (ret) {
 658                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 659                                __func__);
 660                         return ret;
 661                 }
 662
 663                 ret = write_leveling(ddrss);
 664                 if (ret)
 665                         return ret;
 666
 667                 ret = enable_dqs_pd(ddrss);
 668                 if (ret)
 669                         return ret;
 670
 671                 ret = read_dqs_training(ddrss);
 672                 if (ret)
 673                         return ret;
 674
 675                 ret = disable_dqs_pd(ddrss);
 676                 if (ret)
 677                         return ret;
 678
 679                 ret = dqs2dq_training(ddrss);
 680                 if (ret)
 681                         return ret;
 682
 683                 ret = write_leveling_adjustment(ddrss);
 684                 if (ret)
 685                         return ret;
 686
 687                 ret = rest_training(ddrss);
 688                 if (ret)
 689                         return ret;
 690
 691                 ret = VREF_training(ddrss);
 692                 if (ret)
 693                         return ret;
 694
 695                 debug("LPDDR4 training complete\n");
 696                 break;
 697
 698         case DDR_TYPE_DDR4:
 699
 700                 debug("Starting DDR4 training\n");
 701
 702                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 703                                                  PGSR0_DRAM_INIT_MASK, 0);
 704                 if (ret) {
 705                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 706                                 ret);
 707                         return ret;
 708                 }
 709
 710                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 711                 if (ret) {
 712                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 713                                __func__);
 714                         return ret;
 715                 }
 716
 717                 ret = write_leveling(ddrss);
 718                 if (ret)
 719                         return ret;
 720
 721                 ret = read_dqs_training(ddrss);
 722                 if (ret)
 723                         return ret;
 724
 725                 ret = write_leveling_adjustment(ddrss);
 726                 if (ret)
 727                         return ret;
 728
 729                 ret = rest_training(ddrss);
 730                 if (ret)
 731                         return ret;
 732
 733                 ret = VREF_training(ddrss);
 734                 if (ret)
 735                         return ret;
 736                 debug("DDR4 training complete\n");
 737                 break;
 738
 739         case DDR_TYPE_DDR3:
 740
 741                 debug("Starting DDR3 training\n");
 742
 743                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 744                                                  PGSR0_DRAM_INIT_MASK, 0);
 745                 if (ret) {
 746                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 747                                 ret);
 748                         return ret;
 749                 }
 750
 751                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 752                 if (ret) {
 753                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 754                                __func__);
 755                         return ret;
 756                 }
 757
 758                 ret = write_leveling(ddrss);
 759                 if (ret)
 760                         return ret;
 761
 762                 ret = enable_dqs_pd(ddrss);
 763                 if (ret)
 764                         return ret;
 765
 766                 ret = read_dqs_training(ddrss);
 767                 if (ret)
 768                         return ret;
 769
 770                 ret = disable_dqs_pd(ddrss);
 771                 if (ret)
 772                         return ret;
 773
 774                 ret = write_leveling_adjustment(ddrss);
 775                 if (ret)
 776                         return ret;
 777
 778                 ret = rest_training(ddrss);
 779                 if (ret)
 780                         return ret;
 781
 782                 debug("DDR3 training complete\n");
 783                 break;
 784         default:
 785                 printf("%s: ERROR: Unsupported DDR type\n", __func__);
 786                 return -EINVAL;
 787         }
 788
 789         ret = cleanup_training(ddrss);
 790         if (ret)
 791                 return ret;
 792
 793         /* Enabling refreshes after training is done */
 794         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
 795                          ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
 796
 797         /* Disable PUBMODE after training is done */
 798         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
 799                          ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
 800
 801         debug("Completed DDR training\n");
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * am654_ddrss_power_on() - Enable power and clocks for ddrss
 808  * @dev:        corresponding ddrss device
 809  *
 810  * Tries to enable all the corresponding clocks to the ddrss and sets it
 811  * to the right frequency and then power on the ddrss.
 812  * Return: 0 if all went ok, else corresponding error message.
 813  */
 814 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
 815 {
 816         int ret;
 817
 818         debug("%s(ddrss=%p)\n", __func__, ddrss);
 819
 820         ret = clk_enable(&ddrss->ddrss_clk);
 821         if (ret) {
 822                 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
 823                 return ret;
 824         }
 825
 826         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 827         if (ret) {
 828                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 829                 return ret;
 830         }
 831
 832         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 833         if (ret) {
 834                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 835                 return ret;
 836         }
 837
 838         /* VTT enable */
 839 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 840         device_get_supply_regulator(ddrss->dev, "vtt-supply",
 841                                     &ddrss->vtt_supply);
 842         ret = regulator_set_value(ddrss->vtt_supply, 3300000);
 843         if (ret)
 844                 return ret;
 845         debug("VTT regulator enabled\n");
 846 #endif
 847
 848         return 0;
 849 }
 850
 851 /**
 852  * am654_ddrss_ofdata_to_priv() - generate private data from device tree
 853  * @dev:        corresponding ddrss device
 854  *
 855  * Return: 0 if all went ok, else corresponding error message.
 856  */
 857 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
 858 {
 859         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
 860         phys_addr_t reg;
 861         int ret;
 862
 863         debug("%s(dev=%p)\n", __func__, dev);
 864
 865         ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
 866         if (ret) {
 867                 dev_err(dev, "clk_get failed: %d\n", ret);
 868                 return ret;
 869         }
 870
 871         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 872         if (ret) {
 873                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 874                 return ret;
 875         }
 876
 877         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 878         if (ret) {
 879                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 880                 return ret;
 881         }
 882
 883         reg = devfdt_get_addr_name(dev, "ss");
 884         if (reg == FDT_ADDR_T_NONE) {
 885                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 886                 return -EINVAL;
 887         }
 888         ddrss->ddrss_ss_cfg = (void *)reg;
 889
 890         reg = devfdt_get_addr_name(dev, "ctl");
 891         if (reg == FDT_ADDR_T_NONE) {
 892                 dev_err(dev, "No reg property for Controller region\n");
 893                 return -EINVAL;
 894         }
 895         ddrss->ddrss_ctl_cfg = (void *)reg;
 896
 897         reg = devfdt_get_addr_name(dev, "phy");
 898         if (reg == FDT_ADDR_T_NONE) {
 899                 dev_err(dev, "No reg property for PHY region\n");
 900                 return -EINVAL;
 901         }
 902         ddrss->ddrss_phy_cfg = (void *)reg;
 903
 904         ret = dev_read_u32_array(dev, "ti,ctl-reg",
 905                                  (u32 *)&ddrss->params.ctl_reg,
 906                                  sizeof(ddrss->params.ctl_reg) / sizeof(u32));
 907         if (ret) {
 908                 dev_err(dev, "Cannot read ti,ctl-reg params\n");
 909                 return ret;
 910         }
 911
 912         ret = dev_read_u32_array(dev, "ti,ctl-crc",
 913                                  (u32 *)&ddrss->params.ctl_crc,
 914                                  sizeof(ddrss->params.ctl_crc) / sizeof(u32));
 915         if (ret) {
 916                 dev_err(dev, "Cannot read ti,ctl-crc params\n");
 917                 return ret;
 918         }
 919
 920         ret = dev_read_u32_array(dev, "ti,ctl-ecc",
 921                                  (u32 *)&ddrss->params.ctl_ecc,
 922                                  sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
 923         if (ret) {
 924                 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
 925                 return ret;
 926         }
 927
 928         ret = dev_read_u32_array(dev, "ti,ctl-map",
 929                                  (u32 *)&ddrss->params.ctl_map,
 930                                  sizeof(ddrss->params.ctl_map) / sizeof(u32));
 931         if (ret) {
 932                 dev_err(dev, "Cannot read ti,ctl-map params\n");
 933                 return ret;
 934         }
 935
 936         ret = dev_read_u32_array(dev, "ti,ctl-pwr",
 937                                  (u32 *)&ddrss->params.ctl_pwr,
 938                                  sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
 939         if (ret) {
 940                 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
 941                 return ret;
 942         }
 943
 944         ret = dev_read_u32_array(dev, "ti,ctl-timing",
 945                                  (u32 *)&ddrss->params.ctl_timing,
 946                                  sizeof(ddrss->params.ctl_timing) /
 947                                  sizeof(u32));
 948         if (ret) {
 949                 dev_err(dev, "Cannot read ti,ctl-timing params\n");
 950                 return ret;
 951         }
 952
 953         ret = dev_read_u32_array(dev, "ti,phy-cfg",
 954                                  (u32 *)&ddrss->params.phy_cfg,
 955                                  sizeof(ddrss->params.phy_cfg) / sizeof(u32));
 956         if (ret) {
 957                 dev_err(dev, "Cannot read ti,phy-cfg params\n");
 958                 return ret;
 959         }
 960
 961         ret = dev_read_u32_array(dev, "ti,phy-ctl",
 962                                  (u32 *)&ddrss->params.phy_ctrl,
 963                                  sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
 964         if (ret) {
 965                 dev_err(dev, "Cannot read ti,phy-ctl params\n");
 966                 return ret;
 967         }
 968
 969         ret = dev_read_u32_array(dev, "ti,phy-ioctl",
 970                                  (u32 *)&ddrss->params.phy_ioctl,
 971                                  sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
 972         if (ret) {
 973                 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
 974                 return ret;
 975         }
 976
 977         ret = dev_read_u32_array(dev, "ti,phy-timing",
 978                                  (u32 *)&ddrss->params.phy_timing,
 979                                  sizeof(ddrss->params.phy_timing) /
 980                                  sizeof(u32));
 981         if (ret) {
 982                 dev_err(dev, "Cannot read ti,phy-timing params\n");
 983                 return ret;
 984         }
 985
 986         ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
 987                                  sizeof(ddrss->params.phy_zq) / sizeof(u32));
 988         if (ret) {
 989                 dev_err(dev, "Cannot read ti,phy-zq params\n");
 990                 return ret;
 991         }
 992
 993         return ret;
 994 }
 995
 996 /**
 997  * am654_ddrss_probe() - Basic probe
 998  * @dev:        corresponding ddrss device
 999  *
1000  * Return: 0 if all went ok, else corresponding error message
1001  */
1002 static int am654_ddrss_probe(struct udevice *dev)
1003 {
1004         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1005         int ret;
1006
1007         debug("%s(dev=%p)\n", __func__, dev);
1008
1009         ret = am654_ddrss_ofdata_to_priv(dev);
1010         if (ret)
1011                 return ret;
1012
1013         ddrss->dev = dev;
1014         ret = am654_ddrss_power_on(ddrss);
1015         if (ret)
1016                 return ret;
1017
1018         ret = am654_ddrss_init(ddrss);
1019
1020         return ret;
1021 }
1022
1023 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1024 {
1025         return 0;
1026 }
1027
1028 static struct ram_ops am654_ddrss_ops = {
1029         .get_info = am654_ddrss_get_info,
1030 };
1031
1032 static const struct udevice_id am654_ddrss_ids[] = {
1033         { .compatible = "ti,am654-ddrss" },
1034         { }
1035 };
1036
1037 U_BOOT_DRIVER(am654_ddrss) = {
1038         .name = "am654_ddrss",
1039         .id = UCLASS_RAM,
1040         .of_match = am654_ddrss_ids,
1041         .ops = &am654_ddrss_ops,
1042         .probe = am654_ddrss_probe,
1043         .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
1044 };