1 // SPDX-License-Identifier: GPL-2.0+
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
13 /* SDRAM Command Code */
14 #define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
15 #define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
16 #define SD_CC_IRD 0x8 /* IP command - Read */
17 #define SD_CC_IWR 0x9 /* IP command - Write */
18 #define SD_CC_IMS 0xA /* IP command - Set Mode Register */
19 #define SD_CC_IACT 0xB /* IP command - ACTIVE */
20 #define SD_CC_IAF 0xC /* IP command - Auto Refresh */
21 #define SD_CC_ISF 0xD /* IP Command - Self Refresh */
22 #define SD_CC_IPRE 0xE /* IP command - Precharge */
23 #define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
25 #define SEMC_MCR_MDIS BIT(1)
26 #define SEMC_MCR_DQSMD BIT(2)
28 #define SEMC_INTR_IPCMDERR BIT(1)
29 #define SEMC_INTR_IPCMDDONE BIT(0)
31 #define SEMC_IPCMD_KEY 0xA55A0000
33 struct imxrt_semc_regs {
84 #define SEMC_IOCR_MUX_A8_SHIFT 0
85 #define SEMC_IOCR_MUX_CSX0_SHIFT 3
86 #define SEMC_IOCR_MUX_CSX1_SHIFT 6
87 #define SEMC_IOCR_MUX_CSX2_SHIFT 9
88 #define SEMC_IOCR_MUX_CSX3_SHIFT 12
89 #define SEMC_IOCR_MUX_RDY_SHIFT 15
91 struct imxrt_sdram_mux {
100 #define SEMC_SDRAMCR0_PS_SHIFT 0
101 #define SEMC_SDRAMCR0_BL_SHIFT 4
102 #define SEMC_SDRAMCR0_COL_SHIFT 8
103 #define SEMC_SDRAMCR0_CL_SHIFT 10
105 struct imxrt_sdram_control {
112 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
113 #define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
114 #define SEMC_SDRAMCR1_RFRC_SHIFT 8
115 #define SEMC_SDRAMCR1_WRC_SHIFT 13
116 #define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
117 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
119 #define SEMC_SDRAMCR2_SRRC_SHIFT 0
120 #define SEMC_SDRAMCR2_REF2REF_SHIFT 8
121 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
122 #define SEMC_SDRAMCR2_ITO_SHIFT 24
124 #define SEMC_SDRAMCR3_REN BIT(0)
125 #define SEMC_SDRAMCR3_REBL_SHIFT 1
126 #define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
127 #define SEMC_SDRAMCR3_RT_SHIFT 16
128 #define SEMC_SDRAMCR3_UT_SHIFT 24
130 struct imxrt_sdram_timing {
149 enum imxrt_semc_bank {
157 #define SEMC_BR_VLD_MASK 1
158 #define SEMC_BR_MS_SHIFT 1
161 enum imxrt_semc_bank target_bank;
166 struct imxrt_sdram_params {
167 struct imxrt_semc_regs *base;
169 struct imxrt_sdram_mux *sdram_mux;
170 struct imxrt_sdram_control *sdram_control;
171 struct imxrt_sdram_timing *sdram_timing;
173 struct bank_params bank_params[MAX_SDRAM_BANK];
177 static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
182 if (regs->intr & SEMC_INTR_IPCMDDONE)
184 if (regs->intr & SEMC_INTR_IPCMDERR)
191 static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
192 u32 ipcmd, u32 wd, u32 *rd)
196 if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
197 writel(wd, ®s->iptxdat);
199 /* set slave address for every command as specified on RM */
200 writel(mem_addr, ®s->ipcr0);
202 /* execute command */
203 writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
205 ret = imxrt_sdram_wait_ipcmd_done(regs);
209 if (ipcmd == SD_CC_IRD) {
213 *rd = readl(®s->iprxdat);
219 int imxrt_sdram_init(struct udevice *dev)
221 struct imxrt_sdram_params *params = dev_get_platdata(dev);
222 struct imxrt_sdram_mux *mux = params->sdram_mux;
223 struct imxrt_sdram_control *ctrl = params->sdram_control;
224 struct imxrt_sdram_timing *time = params->sdram_timing;
225 struct imxrt_semc_regs *regs = params->base;
226 struct bank_params *bank_params;
230 /* enable the SEMC controller */
231 clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
232 /* set DQS mode from DQS pad */
233 setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
235 for (i = 0, bank_params = params->bank_params;
236 i < params->no_sdram_banks; bank_params++,
238 writel((bank_params->base_address & 0xfffff000)
239 | bank_params->memory_size << SEMC_BR_MS_SHIFT
241 ®s->br[bank_params->target_bank]);
243 writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
244 | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
245 | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
246 | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
247 | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
248 | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
251 writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
252 | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
253 | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
254 | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
257 writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
258 | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
259 | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
260 | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
261 | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
262 | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
265 writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
266 | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
267 | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
268 | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
271 writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
272 | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
273 | time->rt << SEMC_SDRAMCR3_RT_SHIFT
274 | time->ut << SEMC_SDRAMCR3_UT_SHIFT
278 writel(2, ®s->ipcr1);
280 for (i = 0, bank_params = params->bank_params;
281 i < params->no_sdram_banks; bank_params++,
284 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
286 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
288 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
290 imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
291 ctrl->burst_len | (ctrl->cas_latency << 4),
299 static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
301 struct imxrt_sdram_params *params = dev_get_platdata(dev);
306 (struct imxrt_sdram_mux *)
307 dev_read_u8_array_ptr(dev,
309 sizeof(struct imxrt_sdram_mux));
310 if (!params->sdram_mux) {
311 pr_err("fsl,sdram-mux not found");
315 params->sdram_control =
316 (struct imxrt_sdram_control *)
317 dev_read_u8_array_ptr(dev,
319 sizeof(struct imxrt_sdram_control));
320 if (!params->sdram_control) {
321 pr_err("fsl,sdram-control not found");
325 params->sdram_timing =
326 (struct imxrt_sdram_timing *)
327 dev_read_u8_array_ptr(dev,
329 sizeof(struct imxrt_sdram_timing));
330 if (!params->sdram_timing) {
331 pr_err("fsl,sdram-timing not found");
335 dev_for_each_subnode(bank_node, dev) {
336 struct bank_params *bank_params;
340 /* extract the bank index from DT */
341 bank_name = (char *)ofnode_get_name(bank_node);
342 strsep(&bank_name, "@");
344 pr_err("missing sdram bank index");
348 bank_params = ¶ms->bank_params[bank];
349 strict_strtoul(bank_name, 10,
350 (unsigned long *)&bank_params->target_bank);
351 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
352 pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
353 bank_params->target_bank);
357 ret = ofnode_read_u32(bank_node,
359 &bank_params->memory_size);
361 pr_err("fsl,memory-size not found");
365 ret = ofnode_read_u32(bank_node,
367 &bank_params->base_address);
369 pr_err("fsl,base-address not found");
373 debug("Found bank %s %u\n", bank_name,
374 bank_params->target_bank);
378 params->no_sdram_banks = bank;
379 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
384 static int imxrt_semc_probe(struct udevice *dev)
386 struct imxrt_sdram_params *params = dev_get_platdata(dev);
390 addr = dev_read_addr(dev);
391 if (addr == FDT_ADDR_T_NONE)
394 params->base = (struct imxrt_semc_regs *)addr;
399 ret = clk_get_by_index(dev, 0, &clk);
403 ret = clk_enable(&clk);
406 dev_err(dev, "failed to enable clock\n");
410 ret = imxrt_sdram_init(dev);
417 static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
422 static struct ram_ops imxrt_semc_ops = {
423 .get_info = imxrt_semc_get_info,
426 static const struct udevice_id imxrt_semc_ids[] = {
427 { .compatible = "fsl,imxrt-semc", .data = 0 },
431 U_BOOT_DRIVER(imxrt_semc) = {
432 .name = "imxrt_semc",
434 .of_match = imxrt_semc_ids,
435 .ops = &imxrt_semc_ops,
436 .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
437 .probe = imxrt_semc_probe,
438 .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),