3 config ASPEED_DDR4_DUALX8
4 bool "Enable Dual X8 DDR4 die"
5 depends on DM && OF_CONTROL && ARCH_ASPEED
7 Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
8 controller needs to know if the memory chip mounted on the board is dual
9 x8 die or not. Or it may get the wrong size of the memory space.
14 prompt "DDR4 target date rate"
15 default ASPEED_DDR4_1600
17 config ASPEED_DDR4_400
18 bool "DDR4 targets at 400Mbps"
19 depends on DM && OF_CONTROL && ARCH_ASPEED
21 select DDR4 target data rate at 400M
23 config ASPEED_DDR4_800
24 bool "DDR4 targets at 800Mbps"
25 depends on DM && OF_CONTROL && ARCH_ASPEED
27 select DDR4 target data rate at 800M
29 config ASPEED_DDR4_1333
30 bool "DDR4 targets at 1333Mbps"
31 depends on DM && OF_CONTROL && ARCH_ASPEED
33 select DDR4 target data rate at 1333M
35 config ASPEED_DDR4_1600
36 bool "DDR4 targets at 1600Mbps"
37 depends on DM && OF_CONTROL && ARCH_ASPEED
39 select DDR4 target data rate at 1600M
42 config ASPEED_BYPASS_SELFTEST
43 bool "bypass self test during DRAM initialization"
45 Say Y here to bypass DRAM self test to speed up the boot time
48 bool "aspeed SDRAM error correcting code"
49 depends on DM && OF_CONTROL && ARCH_ASPEED
51 enable SDRAM ECC function
54 config ASPEED_ECC_SIZE
55 int "ECC size: 0=driver auto-caluated"
59 SDRAM size with the error correcting code enabled. The unit is
60 in Megabytes. Noted that only the 8/9 of the configured size
61 can be used by the system. The remaining 1/9 will be used by
62 the ECC engine. If the size is set to 0, the sdram driver will
63 calculate the SDRAM size and set the whole range be ECC enabled.
64 endif # end of ASPEED_ECC
65 endif # end of ASPEED_AST2600
66 endif # end of RAM || SPL_RAM