3 config ASPEED_DDR4_DUALX8
4 bool "Enable Dual X8 DDR4 die"
5 depends on DM && OF_CONTROL && ARCH_ASPEED
8 Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
9 controller needs to know if the memory chip mounted on the board is dual
10 x8 die or not. Or it may get the wrong size of the memory space.
15 prompt "DDR4 target date rate"
16 default ASPEED_DDR4_1600
18 config ASPEED_DDR4_400
19 bool "DDR4 targets at 400Mbps"
20 depends on DM && OF_CONTROL && ARCH_ASPEED
22 select DDR4 target data rate at 400M
24 config ASPEED_DDR4_800
25 bool "DDR4 targets at 800Mbps"
26 depends on DM && OF_CONTROL && ARCH_ASPEED
28 select DDR4 target data rate at 800M
30 config ASPEED_DDR4_1333
31 bool "DDR4 targets at 1333Mbps"
32 depends on DM && OF_CONTROL && ARCH_ASPEED
34 select DDR4 target data rate at 1333M
36 config ASPEED_DDR4_1600
37 bool "DDR4 targets at 1600Mbps"
38 depends on DM && OF_CONTROL && ARCH_ASPEED
40 select DDR4 target data rate at 1600M
43 config ASPEED_BYPASS_SELFTEST
44 bool "bypass self test during DRAM initialization"
47 Say Y here to bypass DRAM self test to speed up the boot time
50 bool "aspeed SDRAM error correcting code"
51 depends on DM && OF_CONTROL && ARCH_ASPEED
54 enable SDRAM ECC function
57 config ASPEED_ECC_SIZE
58 int "ECC size: 0=driver auto-caluated"
62 SDRAM size with the error correcting code enabled. The unit is
63 in Megabytes. Noted that only the 8/9 of the configured size
64 can be used by the system. The remaining 1/9 will be used by
65 the ECC engine. If the size is set to 0, the sdram driver will
66 calculate the SDRAM size and set the whole range be ECC enabled.
67 endif # end of ASPEED_ECC
68 endif # end of ASPEED_AST2600
69 endif # end of RAM || SPL_RAM