drivers/qe/uec.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <net.h>
  11 #include <malloc.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <asm/io.h>
  15 #include <linux/immap_qe.h>
  16 #include "uccf.h"
  17 #include "uec.h"
  18 #include "uec_phy.h"
  19 #include "miiphy.h"
  20 #include <fsl_qe.h>
  21 #include <phy.h>
  22
  23 /* Default UTBIPAR SMI address */
  24 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
  25 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
  26 #endif
  27
  28 static struct uec_inf uec_info[] = {
  29 #ifdef CONFIG_UEC_ETH1
  30         STD_UEC_INFO(1),        /* UEC1 */
  31 #endif
  32 #ifdef CONFIG_UEC_ETH2
  33         STD_UEC_INFO(2),        /* UEC2 */
  34 #endif
  35 #ifdef CONFIG_UEC_ETH3
  36         STD_UEC_INFO(3),        /* UEC3 */
  37 #endif
  38 #ifdef CONFIG_UEC_ETH4
  39         STD_UEC_INFO(4),        /* UEC4 */
  40 #endif
  41 #ifdef CONFIG_UEC_ETH5
  42         STD_UEC_INFO(5),        /* UEC5 */
  43 #endif
  44 #ifdef CONFIG_UEC_ETH6
  45         STD_UEC_INFO(6),        /* UEC6 */
  46 #endif
  47 #ifdef CONFIG_UEC_ETH7
  48         STD_UEC_INFO(7),        /* UEC7 */
  49 #endif
  50 #ifdef CONFIG_UEC_ETH8
  51         STD_UEC_INFO(8),        /* UEC8 */
  52 #endif
  53 };
  54
  55 #define MAXCONTROLLERS  (8)
  56
  57 static struct eth_device *devlist[MAXCONTROLLERS];
  58
  59 static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
  60 {
  61         uec_t           *uec_regs;
  62         u32             maccfg1;
  63
  64         if (!uec) {
  65                 printf("%s: uec not initial\n", __func__);
  66                 return -EINVAL;
  67         }
  68         uec_regs = uec->uec_regs;
  69
  70         maccfg1 = in_be32(&uec_regs->maccfg1);
  71
  72         if (mode & COMM_DIR_TX) {
  73                 maccfg1 |= MACCFG1_ENABLE_TX;
  74                 out_be32(&uec_regs->maccfg1, maccfg1);
  75                 uec->mac_tx_enabled = 1;
  76         }
  77
  78         if (mode & COMM_DIR_RX) {
  79                 maccfg1 |= MACCFG1_ENABLE_RX;
  80                 out_be32(&uec_regs->maccfg1, maccfg1);
  81                 uec->mac_rx_enabled = 1;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
  88 {
  89         uec_t           *uec_regs;
  90         u32             maccfg1;
  91
  92         if (!uec) {
  93                 printf("%s: uec not initial\n", __func__);
  94                 return -EINVAL;
  95         }
  96         uec_regs = uec->uec_regs;
  97
  98         maccfg1 = in_be32(&uec_regs->maccfg1);
  99
 100         if (mode & COMM_DIR_TX) {
 101                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 102                 out_be32(&uec_regs->maccfg1, maccfg1);
 103                 uec->mac_tx_enabled = 0;
 104         }
 105
 106         if (mode & COMM_DIR_RX) {
 107                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 108                 out_be32(&uec_regs->maccfg1, maccfg1);
 109                 uec->mac_rx_enabled = 0;
 110         }
 111
 112         return 0;
 113 }
 114
 115 static int uec_graceful_stop_tx(struct uec_priv *uec)
 116 {
 117         ucc_fast_t              *uf_regs;
 118         u32                     cecr_subblock;
 119         u32                     ucce;
 120
 121         if (!uec || !uec->uccf) {
 122                 printf("%s: No handle passed.\n", __func__);
 123                 return -EINVAL;
 124         }
 125
 126         uf_regs = uec->uccf->uf_regs;
 127
 128         /* Clear the grace stop event */
 129         out_be32(&uf_regs->ucce, UCCE_GRA);
 130
 131         /* Issue host command */
 132         cecr_subblock =
 133                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 134         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 135                      (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 136
 137         /* Wait for command to complete */
 138         do {
 139                 ucce = in_be32(&uf_regs->ucce);
 140         } while (!(ucce & UCCE_GRA));
 141
 142         uec->grace_stopped_tx = 1;
 143
 144         return 0;
 145 }
 146
 147 static int uec_graceful_stop_rx(struct uec_priv *uec)
 148 {
 149         u32             cecr_subblock;
 150         u8              ack;
 151
 152         if (!uec) {
 153                 printf("%s: No handle passed.\n", __func__);
 154                 return -EINVAL;
 155         }
 156
 157         if (!uec->p_rx_glbl_pram) {
 158                 printf("%s: No init rx global parameter\n", __func__);
 159                 return -EINVAL;
 160         }
 161
 162         /* Clear acknowledge bit */
 163         ack = uec->p_rx_glbl_pram->rxgstpack;
 164         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 165         uec->p_rx_glbl_pram->rxgstpack = ack;
 166
 167         /* Keep issuing cmd and checking ack bit until it is asserted */
 168         do {
 169                 /* Issue host command */
 170                 cecr_subblock =
 171                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 172                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 173                              (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 174                 ack = uec->p_rx_glbl_pram->rxgstpack;
 175         } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
 176
 177         uec->grace_stopped_rx = 1;
 178
 179         return 0;
 180 }
 181
 182 static int uec_restart_tx(struct uec_priv *uec)
 183 {
 184         u32             cecr_subblock;
 185
 186         if (!uec || !uec->uec_info) {
 187                 printf("%s: No handle passed.\n", __func__);
 188                 return -EINVAL;
 189         }
 190
 191         cecr_subblock =
 192          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 193         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 194                      (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 195
 196         uec->grace_stopped_tx = 0;
 197
 198         return 0;
 199 }
 200
 201 static int uec_restart_rx(struct uec_priv *uec)
 202 {
 203         u32             cecr_subblock;
 204
 205         if (!uec || !uec->uec_info) {
 206                 printf("%s: No handle passed.\n", __func__);
 207                 return -EINVAL;
 208         }
 209
 210         cecr_subblock =
 211          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 212         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 213                      (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 214
 215         uec->grace_stopped_rx = 0;
 216
 217         return 0;
 218 }
 219
 220 static int uec_open(struct uec_priv *uec, comm_dir_e mode)
 221 {
 222         struct ucc_fast_priv    *uccf;
 223
 224         if (!uec || !uec->uccf) {
 225                 printf("%s: No handle passed.\n", __func__);
 226                 return -EINVAL;
 227         }
 228         uccf = uec->uccf;
 229
 230         /* check if the UCC number is in range. */
 231         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 232                 printf("%s: ucc_num out of range.\n", __func__);
 233                 return -EINVAL;
 234         }
 235
 236         /* Enable MAC */
 237         uec_mac_enable(uec, mode);
 238
 239         /* Enable UCC fast */
 240         ucc_fast_enable(uccf, mode);
 241
 242         /* RISC microcode start */
 243         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
 244                 uec_restart_tx(uec);
 245         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
 246                 uec_restart_rx(uec);
 247
 248         return 0;
 249 }
 250
 251 static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
 252 {
 253         if (!uec || !uec->uccf) {
 254                 printf("%s: No handle passed.\n", __func__);
 255                 return -EINVAL;
 256         }
 257
 258         /* check if the UCC number is in range. */
 259         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 260                 printf("%s: ucc_num out of range.\n", __func__);
 261                 return -EINVAL;
 262         }
 263         /* Stop any transmissions */
 264         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
 265                 uec_graceful_stop_tx(uec);
 266
 267         /* Stop any receptions */
 268         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
 269                 uec_graceful_stop_rx(uec);
 270
 271         /* Disable the UCC fast */
 272         ucc_fast_disable(uec->uccf, mode);
 273
 274         /* Disable the MAC */
 275         uec_mac_disable(uec, mode);
 276
 277         return 0;
 278 }
 279
 280 static int uec_set_mac_duplex(struct uec_priv *uec, int duplex)
 281 {
 282         uec_t           *uec_regs;
 283         u32             maccfg2;
 284
 285         if (!uec) {
 286                 printf("%s: uec not initial\n", __func__);
 287                 return -EINVAL;
 288         }
 289         uec_regs = uec->uec_regs;
 290
 291         if (duplex == DUPLEX_HALF) {
 292                 maccfg2 = in_be32(&uec_regs->maccfg2);
 293                 maccfg2 &= ~MACCFG2_FDX;
 294                 out_be32(&uec_regs->maccfg2, maccfg2);
 295         }
 296
 297         if (duplex == DUPLEX_FULL) {
 298                 maccfg2 = in_be32(&uec_regs->maccfg2);
 299                 maccfg2 |= MACCFG2_FDX;
 300                 out_be32(&uec_regs->maccfg2, maccfg2);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int uec_set_mac_if_mode(struct uec_priv *uec,
 307                                phy_interface_t if_mode, int speed)
 308 {
 309         phy_interface_t         enet_if_mode;
 310         uec_t                   *uec_regs;
 311         u32                     upsmr;
 312         u32                     maccfg2;
 313
 314         if (!uec) {
 315                 printf("%s: uec not initial\n", __func__);
 316                 return -EINVAL;
 317         }
 318
 319         uec_regs = uec->uec_regs;
 320         enet_if_mode = if_mode;
 321
 322         maccfg2 = in_be32(&uec_regs->maccfg2);
 323         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 324
 325         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 326         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 327
 328         switch (speed) {
 329         case SPEED_10:
 330                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 331                 switch (enet_if_mode) {
 332                 case PHY_INTERFACE_MODE_MII:
 333                         break;
 334                 case PHY_INTERFACE_MODE_RGMII:
 335                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 336                         break;
 337                 case PHY_INTERFACE_MODE_RMII:
 338                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 339                         break;
 340                 default:
 341                         return -EINVAL;
 342                 }
 343                 break;
 344         case SPEED_100:
 345                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 346                 switch (enet_if_mode) {
 347                 case PHY_INTERFACE_MODE_MII:
 348                         break;
 349                 case PHY_INTERFACE_MODE_RGMII:
 350                         upsmr |= UPSMR_RPM;
 351                         break;
 352                 case PHY_INTERFACE_MODE_RMII:
 353                         upsmr |= UPSMR_RMM;
 354                         break;
 355                 default:
 356                         return -EINVAL;
 357                 }
 358                 break;
 359         case SPEED_1000:
 360                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 361                 switch (enet_if_mode) {
 362                 case PHY_INTERFACE_MODE_GMII:
 363                         break;
 364                 case PHY_INTERFACE_MODE_TBI:
 365                         upsmr |= UPSMR_TBIM;
 366                         break;
 367                 case PHY_INTERFACE_MODE_RTBI:
 368                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 369                         break;
 370                 case PHY_INTERFACE_MODE_RGMII_RXID:
 371                 case PHY_INTERFACE_MODE_RGMII_TXID:
 372                 case PHY_INTERFACE_MODE_RGMII_ID:
 373                 case PHY_INTERFACE_MODE_RGMII:
 374                         upsmr |= UPSMR_RPM;
 375                         break;
 376                 case PHY_INTERFACE_MODE_SGMII:
 377                         upsmr |= UPSMR_SGMM;
 378                         break;
 379                 default:
 380                         return -EINVAL;
 381                 }
 382                 break;
 383         default:
 384                 return -EINVAL;
 385         }
 386
 387         out_be32(&uec_regs->maccfg2, maccfg2);
 388         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 389
 390         return 0;
 391 }
 392
 393 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 394 {
 395         uint            timeout = 0x1000;
 396         u32             miimcfg = 0;
 397
 398         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 399         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 400         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 401
 402         /* Wait until the bus is free */
 403         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--)
 404                 ;
 405         if (timeout <= 0) {
 406                 printf("%s: The MII Bus is stuck!", __func__);
 407                 return -ETIMEDOUT;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int init_phy(struct eth_device *dev)
 414 {
 415         struct uec_priv         *uec;
 416         uec_mii_t               *umii_regs;
 417         struct uec_mii_info     *mii_info;
 418         struct phy_info         *curphy;
 419         int                     err;
 420
 421         uec = (struct uec_priv *)dev->priv;
 422         umii_regs = uec->uec_mii_regs;
 423
 424         uec->oldlink = 0;
 425         uec->oldspeed = 0;
 426         uec->oldduplex = -1;
 427
 428         mii_info = malloc(sizeof(*mii_info));
 429         if (!mii_info) {
 430                 printf("%s: Could not allocate mii_info", dev->name);
 431                 return -ENOMEM;
 432         }
 433         memset(mii_info, 0, sizeof(*mii_info));
 434
 435         if (uec->uec_info->uf_info.eth_type == GIGA_ETH)
 436                 mii_info->speed = SPEED_1000;
 437         else
 438                 mii_info->speed = SPEED_100;
 439
 440         mii_info->duplex = DUPLEX_FULL;
 441         mii_info->pause = 0;
 442         mii_info->link = 1;
 443
 444         mii_info->advertising = (ADVERTISED_10baseT_Half |
 445                                 ADVERTISED_10baseT_Full |
 446                                 ADVERTISED_100baseT_Half |
 447                                 ADVERTISED_100baseT_Full |
 448                                 ADVERTISED_1000baseT_Full);
 449         mii_info->autoneg = 1;
 450         mii_info->mii_id = uec->uec_info->phy_address;
 451         mii_info->dev = dev;
 452
 453         mii_info->mdio_read = &uec_read_phy_reg;
 454         mii_info->mdio_write = &uec_write_phy_reg;
 455
 456         uec->mii_info = mii_info;
 457
 458         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 459
 460         if (init_mii_management_configuration(umii_regs)) {
 461                 printf("%s: The MII Bus is stuck!", dev->name);
 462                 err = -1;
 463                 goto bus_fail;
 464         }
 465
 466         /* get info for this PHY */
 467         curphy = uec_get_phy_info(uec->mii_info);
 468         if (!curphy) {
 469                 printf("%s: No PHY found", dev->name);
 470                 err = -1;
 471                 goto no_phy;
 472         }
 473
 474         mii_info->phyinfo = curphy;
 475
 476         /* Run the commands which initialize the PHY */
 477         if (curphy->init) {
 478                 err = curphy->init(uec->mii_info);
 479                 if (err)
 480                         goto phy_init_fail;
 481         }
 482
 483         return 0;
 484
 485 phy_init_fail:
 486 no_phy:
 487 bus_fail:
 488         free(mii_info);
 489         return err;
 490 }
 491
 492 static void adjust_link(struct eth_device *dev)
 493 {
 494         struct uec_priv         *uec = (struct uec_priv *)dev->priv;
 495         struct uec_mii_info     *mii_info = uec->mii_info;
 496
 497         if (mii_info->link) {
 498                 /*
 499                  * Now we make sure that we can be in full duplex mode.
 500                  * If not, we operate in half-duplex mode.
 501                  */
 502                 if (mii_info->duplex != uec->oldduplex) {
 503                         if (!(mii_info->duplex)) {
 504                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 505                                 printf("%s: Half Duplex\n", dev->name);
 506                         } else {
 507                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 508                                 printf("%s: Full Duplex\n", dev->name);
 509                         }
 510                         uec->oldduplex = mii_info->duplex;
 511                 }
 512
 513                 if (mii_info->speed != uec->oldspeed) {
 514                         phy_interface_t mode =
 515                                 uec->uec_info->enet_interface_type;
 516                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 517                                 switch (mii_info->speed) {
 518                                 case SPEED_1000:
 519                                         break;
 520                                 case SPEED_100:
 521                                         printf("switching to rgmii 100\n");
 522                                         mode = PHY_INTERFACE_MODE_RGMII;
 523                                         break;
 524                                 case SPEED_10:
 525                                         printf("switching to rgmii 10\n");
 526                                         mode = PHY_INTERFACE_MODE_RGMII;
 527                                         break;
 528                                 default:
 529                                         printf("%s: Ack,Speed(%d)is illegal\n",
 530                                                dev->name, mii_info->speed);
 531                                         break;
 532                                 }
 533                         }
 534
 535                         /* change phy */
 536                         change_phy_interface_mode(dev, mode, mii_info->speed);
 537                         /* change the MAC interface mode */
 538                         uec_set_mac_if_mode(uec, mode, mii_info->speed);
 539
 540                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 541                         uec->oldspeed = mii_info->speed;
 542                 }
 543
 544                 if (!uec->oldlink) {
 545                         printf("%s: Link is up\n", dev->name);
 546                         uec->oldlink = 1;
 547                 }
 548
 549         } else { /* if (mii_info->link) */
 550                 if (uec->oldlink) {
 551                         printf("%s: Link is down\n", dev->name);
 552                         uec->oldlink = 0;
 553                         uec->oldspeed = 0;
 554                         uec->oldduplex = -1;
 555                 }
 556         }
 557 }
 558
 559 static void phy_change(struct eth_device *dev)
 560 {
 561         struct uec_priv *uec = (struct uec_priv *)dev->priv;
 562
 563 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 564         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 565
 566         /* QE9 and QE12 need to be set for enabling QE MII management signals */
 567         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 568         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 569 #endif
 570
 571         /* Update the link, speed, duplex */
 572         uec->mii_info->phyinfo->read_status(uec->mii_info);
 573
 574 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 575         /*
 576          * QE12 is muxed with LBCTL, it needs to be released for enabling
 577          * LBCTL signal for LBC usage.
 578          */
 579         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 580 #endif
 581
 582         /* Adjust the interface according to speed */
 583         adjust_link(dev);
 584 }
 585
 586 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 587
 588 /*
 589  * Find a device index from the devlist by name
 590  *
 591  * Returns:
 592  *  The index where the device is located, -1 on error
 593  */
 594 static int uec_miiphy_find_dev_by_name(const char *devname)
 595 {
 596         int i;
 597
 598         for (i = 0; i < MAXCONTROLLERS; i++) {
 599                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0)
 600                         break;
 601         }
 602
 603         /* If device cannot be found, returns -1 */
 604         if (i == MAXCONTROLLERS) {
 605                 debug("%s: device %s not found in devlist\n", __func__,
 606                       devname);
 607                 i = -1;
 608         }
 609
 610         return i;
 611 }
 612
 613 /*
 614  * Read a MII PHY register.
 615  *
 616  * Returns:
 617  *  0 on success
 618  */
 619 static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
 620 {
 621         unsigned short value = 0;
 622         int devindex = 0;
 623
 624         if (!bus->name) {
 625                 debug("%s: NULL pointer given\n", __func__);
 626         } else {
 627                 devindex = uec_miiphy_find_dev_by_name(bus->name);
 628                 if (devindex >= 0)
 629                         value = uec_read_phy_reg(devlist[devindex], addr, reg);
 630         }
 631         return value;
 632 }
 633
 634 /*
 635  * Write a MII PHY register.
 636  *
 637  * Returns:
 638  *  0 on success
 639  */
 640 static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
 641                             u16 value)
 642 {
 643         int devindex = 0;
 644
 645         if (!bus->name) {
 646                 debug("%s: NULL pointer given\n", __func__);
 647         } else {
 648                 devindex = uec_miiphy_find_dev_by_name(bus->name);
 649                 if (devindex >= 0)
 650                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
 651         }
 652         return 0;
 653 }
 654 #endif
 655
 656 static int uec_set_mac_address(struct uec_priv *uec, u8 *mac_addr)
 657 {
 658         uec_t           *uec_regs;
 659         u32             mac_addr1;
 660         u32             mac_addr2;
 661
 662         if (!uec) {
 663                 printf("%s: uec not initial\n", __func__);
 664                 return -EINVAL;
 665         }
 666
 667         uec_regs = uec->uec_regs;
 668
 669         /*
 670          * if a station address of 0x12345678ABCD, perform a write to
 671          * MACSTNADDR1 of 0xCDAB7856,
 672          * MACSTNADDR2 of 0x34120000
 673          */
 674
 675         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) |
 676                         (mac_addr[3] << 8)  | (mac_addr[2]);
 677         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 678
 679         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 680         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 681
 682         return 0;
 683 }
 684
 685 static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
 686                                    int *threads_num_ret)
 687 {
 688         int     num_threads_numerica;
 689
 690         switch (threads_num) {
 691         case UEC_NUM_OF_THREADS_1:
 692                 num_threads_numerica = 1;
 693                 break;
 694         case UEC_NUM_OF_THREADS_2:
 695                 num_threads_numerica = 2;
 696                 break;
 697         case UEC_NUM_OF_THREADS_4:
 698                 num_threads_numerica = 4;
 699                 break;
 700         case UEC_NUM_OF_THREADS_6:
 701                 num_threads_numerica = 6;
 702                 break;
 703         case UEC_NUM_OF_THREADS_8:
 704                 num_threads_numerica = 8;
 705                 break;
 706         default:
 707                 printf("%s: Bad number of threads value.",
 708                        __func__);
 709                 return -EINVAL;
 710         }
 711
 712         *threads_num_ret = num_threads_numerica;
 713
 714         return 0;
 715 }
 716
 717 static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
 718 {
 719         struct uec_inf  *uec_info;
 720         u32             end_bd;
 721         u8              bmrx = 0;
 722         int             i;
 723
 724         uec_info = uec->uec_info;
 725
 726         /* Alloc global Tx parameter RAM page */
 727         uec->tx_glbl_pram_offset =
 728                 qe_muram_alloc(sizeof(struct uec_tx_global_pram),
 729                                UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 730         uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
 731                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 732
 733         /* Zero the global Tx prameter RAM */
 734         memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
 735
 736         /* Init global Tx parameter RAM */
 737
 738         /* TEMODER, RMON statistics disable, one Tx queue */
 739         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 740
 741         /* SQPTR */
 742         uec->send_q_mem_reg_offset =
 743                 qe_muram_alloc(sizeof(struct uec_send_queue_qd),
 744                                UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 745         uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
 746                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 747         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 748
 749         /* Setup the table with TxBDs ring */
 750         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 751                                          * SIZEOFBD;
 752         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 753                  (u32)(uec->p_tx_bd_ring));
 754         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 755                  end_bd);
 756
 757         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 758         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 759
 760         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 761         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 762
 763         /* TSTATE, global snooping, big endian, the CSB bus selected */
 764         bmrx = BMR_INIT_VALUE;
 765         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 766
 767         /* IPH_Offset */
 768         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
 769                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 770
 771         /* VTAG table */
 772         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
 773                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 774
 775         /* TQPTR */
 776         uec->thread_dat_tx_offset =
 777                 qe_muram_alloc(num_threads_tx *
 778                                sizeof(struct uec_thread_data_tx) +
 779                                32 * (num_threads_tx == 1),
 780                                UEC_THREAD_DATA_ALIGNMENT);
 781
 782         uec->p_thread_data_tx = (struct uec_thread_data_tx *)
 783                                 qe_muram_addr(uec->thread_dat_tx_offset);
 784         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 785 }
 786
 787 static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
 788 {
 789         u8      bmrx = 0;
 790         int     i;
 791         struct uec_82xx_add_filtering_pram      *p_af_pram;
 792
 793         /* Allocate global Rx parameter RAM page */
 794         uec->rx_glbl_pram_offset =
 795                 qe_muram_alloc(sizeof(struct uec_rx_global_pram),
 796                                UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 797         uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
 798                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 799
 800         /* Zero Global Rx parameter RAM */
 801         memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
 802
 803         /* Init global Rx parameter RAM */
 804         /*
 805          * REMODER, Extended feature mode disable, VLAN disable,
 806          * LossLess flow control disable, Receive firmware statisic disable,
 807          * Extended address parsing mode disable, One Rx queues,
 808          * Dynamic maximum/minimum frame length disable, IP checksum check
 809          * disable, IP address alignment disable
 810          */
 811         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 812
 813         /* RQPTR */
 814         uec->thread_dat_rx_offset =
 815                 qe_muram_alloc(num_threads_rx *
 816                                sizeof(struct uec_thread_data_rx),
 817                                UEC_THREAD_DATA_ALIGNMENT);
 818         uec->p_thread_data_rx = (struct uec_thread_data_rx *)
 819                                 qe_muram_addr(uec->thread_dat_rx_offset);
 820         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 821
 822         /* Type_or_Len */
 823         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 824
 825         /* RxRMON base pointer, we don't need it */
 826         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 827
 828         /* IntCoalescingPTR, we don't need it, no interrupt */
 829         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 830
 831         /* RSTATE, global snooping, big endian, the CSB bus selected */
 832         bmrx = BMR_INIT_VALUE;
 833         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 834
 835         /* MRBLR */
 836         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 837
 838         /* RBDQPTR */
 839         uec->rx_bd_qs_tbl_offset =
 840                 qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
 841                                sizeof(struct uec_rx_pref_bds),
 842                                UEC_RX_BD_QUEUES_ALIGNMENT);
 843         uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
 844                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 845
 846         /* Zero it */
 847         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
 848                sizeof(struct uec_rx_pref_bds));
 849         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 850         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 851                  (u32)uec->p_rx_bd_ring);
 852
 853         /* MFLR */
 854         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 855         /* MINFLR */
 856         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 857         /* MAXD1 */
 858         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 859         /* MAXD2 */
 860         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 861         /* ECAM_PTR */
 862         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 863         /* L2QT */
 864         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 865         /* L3QT */
 866         for (i = 0; i < 8; i++)
 867                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 868
 869         /* VLAN_TYPE */
 870         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 871         /* TCI */
 872         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 873
 874         /* Clear PQ2 style address filtering hash table */
 875         p_af_pram = (struct uec_82xx_add_filtering_pram *)
 876                         uec->p_rx_glbl_pram->addressfiltering;
 877
 878         p_af_pram->iaddr_h = 0;
 879         p_af_pram->iaddr_l = 0;
 880         p_af_pram->gaddr_h = 0;
 881         p_af_pram->gaddr_l = 0;
 882 }
 883
 884 static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
 885                                         int thread_tx, int thread_rx)
 886 {
 887         struct uec_init_cmd_pram                *p_init_enet_param;
 888         u32                             init_enet_param_offset;
 889         struct uec_inf                  *uec_info;
 890         struct ucc_fast_inf                     *uf_info;
 891         int                             i;
 892         int                             snum;
 893         u32                             off;
 894         u32                             entry_val;
 895         u32                             command;
 896         u32                             cecr_subblock;
 897
 898         uec_info = uec->uec_info;
 899         uf_info = &uec_info->uf_info;
 900
 901         /* Allocate init enet command parameter */
 902         uec->init_enet_param_offset =
 903                 qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
 904         init_enet_param_offset = uec->init_enet_param_offset;
 905         uec->p_init_enet_param = (struct uec_init_cmd_pram *)
 906                                 qe_muram_addr(uec->init_enet_param_offset);
 907
 908         /* Zero init enet command struct */
 909         memset((void *)uec->p_init_enet_param, 0,
 910                sizeof(struct uec_init_cmd_pram));
 911
 912         /* Init the command struct */
 913         p_init_enet_param = uec->p_init_enet_param;
 914         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 915         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 916         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 917         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 918         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 919         p_init_enet_param->largestexternallookupkeysize = 0;
 920
 921         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 922                                          << ENET_INIT_PARAM_RGF_SHIFT;
 923         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 924                                          << ENET_INIT_PARAM_TGF_SHIFT;
 925
 926         /* Init Rx global parameter pointer */
 927         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 928                                                  (u32)uec_info->risc_rx;
 929
 930         /* Init Rx threads */
 931         for (i = 0; i < (thread_rx + 1); i++) {
 932                 snum = qe_get_snum();
 933                 if (snum < 0) {
 934                         printf("%s can not get snum\n", __func__);
 935                         return -ENOMEM;
 936                 }
 937
 938                 if (i == 0) {
 939                         off = 0;
 940                 } else {
 941                         off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
 942                                              UEC_THREAD_RX_PRAM_ALIGNMENT);
 943                 }
 944
 945                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 946                                  off | (u32)uec_info->risc_rx;
 947                 p_init_enet_param->rxthread[i] = entry_val;
 948         }
 949
 950         /* Init Tx global parameter pointer */
 951         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 952                                          (u32)uec_info->risc_tx;
 953
 954         /* Init Tx threads */
 955         for (i = 0; i < thread_tx; i++) {
 956                 snum = qe_get_snum();
 957                 if (snum  < 0)  {
 958                         printf("%s can not get snum\n", __func__);
 959                         return -ENOMEM;
 960                 }
 961
 962                 off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
 963                                      UEC_THREAD_TX_PRAM_ALIGNMENT);
 964
 965                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 966                                  off | (u32)uec_info->risc_tx;
 967                 p_init_enet_param->txthread[i] = entry_val;
 968         }
 969
 970         __asm__ __volatile__("sync");
 971
 972         /* Issue QE command */
 973         command = QE_INIT_TX_RX;
 974         cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
 975         qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
 976                      init_enet_param_offset);
 977
 978         return 0;
 979 }
 980
 981 static int uec_startup(struct uec_priv *uec)
 982 {
 983         struct uec_inf                  *uec_info;
 984         struct ucc_fast_inf             *uf_info;
 985         struct ucc_fast_priv            *uccf;
 986         ucc_fast_t                      *uf_regs;
 987         uec_t                           *uec_regs;
 988         int                             num_threads_tx;
 989         int                             num_threads_rx;
 990         u32                             utbipar;
 991         u32                             length;
 992         u32                             align;
 993         struct buffer_descriptor        *bd;
 994         u8                              *buf;
 995         int                             i;
 996
 997         if (!uec || !uec->uec_info) {
 998                 printf("%s: uec or uec_info not initial\n", __func__);
 999                 return -EINVAL;
1000         }
1001
1002         uec_info = uec->uec_info;
1003         uf_info = &uec_info->uf_info;
1004
1005         /* Check if Rx BD ring len is illegal */
1006         if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
1007             (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1008                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1009                        __func__);
1010                 return -EINVAL;
1011         }
1012
1013         /* Check if Tx BD ring len is illegal */
1014         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1015                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1016                        __func__);
1017                 return -EINVAL;
1018         }
1019
1020         /* Check if MRBLR is illegal */
1021         if (MAX_RXBUF_LEN == 0 || MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT) {
1022                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1023                        __func__);
1024                 return -EINVAL;
1025         }
1026
1027         /* Both Rx and Tx are stopped */
1028         uec->grace_stopped_rx = 1;
1029         uec->grace_stopped_tx = 1;
1030
1031         /* Init UCC fast */
1032         if (ucc_fast_init(uf_info, &uccf)) {
1033                 printf("%s: failed to init ucc fast\n", __func__);
1034                 return -ENOMEM;
1035         }
1036
1037         /* Save uccf */
1038         uec->uccf = uccf;
1039
1040         /* Convert the Tx threads number */
1041         if (uec_convert_threads_num(uec_info->num_threads_tx,
1042                                     &num_threads_tx)) {
1043                 return -EINVAL;
1044         }
1045
1046         /* Convert the Rx threads number */
1047         if (uec_convert_threads_num(uec_info->num_threads_rx,
1048                                     &num_threads_rx)) {
1049                 return -EINVAL;
1050         }
1051
1052         uf_regs = uccf->uf_regs;
1053
1054         /* UEC register is following UCC fast registers */
1055         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1056
1057         /* Save the UEC register pointer to UEC private struct */
1058         uec->uec_regs = uec_regs;
1059
1060         /* Init UPSMR, enable hardware statistics (UCC) */
1061         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1062
1063         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1064         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1065
1066         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1067         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1068
1069         /* Setup MAC interface mode */
1070         uec_set_mac_if_mode(uec, uec_info->enet_interface_type,
1071                             uec_info->speed);
1072
1073         /* Setup MII management base */
1074 #ifndef CONFIG_eTSEC_MDIO_BUS
1075         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1076 #else
1077         uec->uec_mii_regs = (uec_mii_t *)CONFIG_MIIM_ADDRESS;
1078 #endif
1079
1080         /* Setup MII master clock source */
1081         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1082
1083         /* Setup UTBIPAR */
1084         utbipar = in_be32(&uec_regs->utbipar);
1085         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1086
1087         /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1088          * This frees up the remaining SMI addresses for use.
1089          */
1090         utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1091         out_be32(&uec_regs->utbipar, utbipar);
1092
1093         /* Configure the TBI for SGMII operation */
1094         if (uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII &&
1095             uec->uec_info->speed == SPEED_1000) {
1096                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1097                                   ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1098
1099                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1100                                   ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1101
1102                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1103                                   ENET_TBI_MII_CR, TBICR_SETTINGS);
1104         }
1105
1106         /* Allocate Tx BDs */
1107         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1108                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1109                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1110         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1111                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1112                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1113         }
1114
1115         align = UEC_TX_BD_RING_ALIGNMENT;
1116         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1117         if (uec->tx_bd_ring_offset != 0) {
1118                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1119                                                  & ~(align - 1));
1120         }
1121
1122         /* Zero all of Tx BDs */
1123         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1124
1125         /* Allocate Rx BDs */
1126         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1127         align = UEC_RX_BD_RING_ALIGNMENT;
1128         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1129         if (uec->rx_bd_ring_offset != 0) {
1130                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1131                                                          & ~(align - 1));
1132         }
1133
1134         /* Zero all of Rx BDs */
1135         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1136
1137         /* Allocate Rx buffer */
1138         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1139         align = UEC_RX_DATA_BUF_ALIGNMENT;
1140         uec->rx_buf_offset = (u32)malloc(length + align);
1141         if (uec->rx_buf_offset != 0) {
1142                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1143                                                  & ~(align - 1));
1144         }
1145
1146         /* Zero all of the Rx buffer */
1147         memset((void *)(uec->rx_buf_offset), 0, length + align);
1148
1149         /* Init TxBD ring */
1150         bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
1151         uec->tx_bd = bd;
1152
1153         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1154                 BD_DATA_CLEAR(bd);
1155                 BD_STATUS_SET(bd, 0);
1156                 BD_LENGTH_SET(bd, 0);
1157                 bd++;
1158         }
1159         BD_STATUS_SET((--bd), TX_BD_WRAP);
1160
1161         /* Init RxBD ring */
1162         bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
1163         uec->rx_bd = bd;
1164         buf = uec->p_rx_buf;
1165         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1166                 BD_DATA_SET(bd, buf);
1167                 BD_LENGTH_SET(bd, 0);
1168                 BD_STATUS_SET(bd, RX_BD_EMPTY);
1169                 buf += MAX_RXBUF_LEN;
1170                 bd++;
1171         }
1172         BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
1173
1174         /* Init global Tx parameter RAM */
1175         uec_init_tx_parameter(uec, num_threads_tx);
1176
1177         /* Init global Rx parameter RAM */
1178         uec_init_rx_parameter(uec, num_threads_rx);
1179
1180         /* Init ethernet Tx and Rx parameter command */
1181         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1182                                          num_threads_rx)) {
1183                 printf("%s issue init enet cmd failed\n", __func__);
1184                 return -ENOMEM;
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int uec_init(struct eth_device *dev, struct bd_info *bd)
1191 {
1192         struct uec_priv         *uec;
1193         int                     err, i;
1194         struct phy_info         *curphy;
1195 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1196         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1197 #endif
1198
1199         uec = (struct uec_priv *)dev->priv;
1200
1201         if (!uec->the_first_run) {
1202 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1203                 /*
1204                  * QE9 and QE12 need to be set for enabling QE MII
1205                  * management signals
1206                  */
1207                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1208                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1209 #endif
1210
1211                 err = init_phy(dev);
1212                 if (err) {
1213                         printf("%s: Cannot initialize PHY, aborting.\n",
1214                                dev->name);
1215                         return err;
1216                 }
1217
1218                 curphy = uec->mii_info->phyinfo;
1219
1220                 if (curphy->config_aneg) {
1221                         err = curphy->config_aneg(uec->mii_info);
1222                         if (err) {
1223                                 printf("%s: Can't negotiate PHY\n", dev->name);
1224                                 return err;
1225                         }
1226                 }
1227
1228                 /* Give PHYs up to 5 sec to report a link */
1229                 i = 50;
1230                 do {
1231                         err = curphy->read_status(uec->mii_info);
1232                         if (!(((i-- > 0) && !uec->mii_info->link) || err))
1233                                 break;
1234                         mdelay(100);
1235                 } while (1);
1236
1237 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1238                 /* QE12 needs to be released for enabling LBCTL signal*/
1239                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1240 #endif
1241
1242                 if (err || i <= 0)
1243                         printf("warning: %s: timeout on PHY link\n", dev->name);
1244
1245                 adjust_link(dev);
1246                 uec->the_first_run = 1;
1247         }
1248
1249         /* Set up the MAC address */
1250         if (dev->enetaddr[0] & 0x01) {
1251                 printf("%s: MacAddress is multcast address\n",
1252                        __func__);
1253                 return -1;
1254         }
1255         uec_set_mac_address(uec, dev->enetaddr);
1256
1257         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1258         if (err) {
1259                 printf("%s: cannot enable UEC device\n", dev->name);
1260                 return -1;
1261         }
1262
1263         phy_change(dev);
1264
1265         return uec->mii_info->link ? 0 : -1;
1266 }
1267
1268 static void uec_halt(struct eth_device *dev)
1269 {
1270         struct uec_priv *uec = (struct uec_priv *)dev->priv;
1271
1272         uec_stop(uec, COMM_DIR_RX_AND_TX);
1273 }
1274
1275 static int uec_send(struct eth_device *dev, void *buf, int len)
1276 {
1277         struct uec_priv         *uec;
1278         struct ucc_fast_priv    *uccf;
1279         struct buffer_descriptor        *bd;
1280         u16                     status;
1281         int                     i;
1282         int                     result = 0;
1283
1284         uec = (struct uec_priv *)dev->priv;
1285         uccf = uec->uccf;
1286         bd = uec->tx_bd;
1287
1288         /* Find an empty TxBD */
1289         for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
1290                 if (i > 0x100000) {
1291                         printf("%s: tx buffer not ready\n", dev->name);
1292                         return result;
1293                 }
1294         }
1295
1296         /* Init TxBD */
1297         BD_DATA_SET(bd, buf);
1298         BD_LENGTH_SET(bd, len);
1299         status = BD_STATUS(bd);
1300         status &= BD_WRAP;
1301         status |= (TX_BD_READY | TX_BD_LAST);
1302         BD_STATUS_SET(bd, status);
1303
1304         /* Tell UCC to transmit the buffer */
1305         ucc_fast_transmit_on_demand(uccf);
1306
1307         /* Wait for buffer to be transmitted */
1308         for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
1309                 if (i > 0x100000) {
1310                         printf("%s: tx error\n", dev->name);
1311                         return result;
1312                 }
1313         }
1314
1315         /* Ok, the buffer be transimitted */
1316         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1317         uec->tx_bd = bd;
1318         result = 1;
1319
1320         return result;
1321 }
1322
1323 static int uec_recv(struct eth_device *dev)
1324 {
1325         struct uec_priv         *uec = dev->priv;
1326         struct buffer_descriptor        *bd;
1327         u16                     status;
1328         u16                     len;
1329         u8                      *data;
1330
1331         bd = uec->rx_bd;
1332         status = BD_STATUS(bd);
1333
1334         while (!(status & RX_BD_EMPTY)) {
1335                 if (!(status & RX_BD_ERROR)) {
1336                         data = BD_DATA(bd);
1337                         len = BD_LENGTH(bd);
1338                         net_process_received_packet(data, len);
1339                 } else {
1340                         printf("%s: Rx error\n", dev->name);
1341                 }
1342                 status &= BD_CLEAN;
1343                 BD_LENGTH_SET(bd, 0);
1344                 BD_STATUS_SET(bd, status | RX_BD_EMPTY);
1345                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1346                 status = BD_STATUS(bd);
1347         }
1348         uec->rx_bd = bd;
1349
1350         return 1;
1351 }
1352
1353 int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info)
1354 {
1355         struct eth_device       *dev;
1356         int                     i;
1357         struct uec_priv         *uec;
1358         int                     err;
1359
1360         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1361         if (!dev)
1362                 return 0;
1363         memset(dev, 0, sizeof(struct eth_device));
1364
1365         /* Allocate the UEC private struct */
1366         uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
1367         if (!uec)
1368                 return -ENOMEM;
1369
1370         memset(uec, 0, sizeof(struct uec_priv));
1371
1372         /* Adjust uec_info */
1373 #if (MAX_QE_RISC == 4)
1374         uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1375         uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1376 #endif
1377
1378         devlist[uec_info->uf_info.ucc_num] = dev;
1379
1380         uec->uec_info = uec_info;
1381         uec->dev = dev;
1382
1383         sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1384         dev->iobase = 0;
1385         dev->priv = (void *)uec;
1386         dev->init = uec_init;
1387         dev->halt = uec_halt;
1388         dev->send = uec_send;
1389         dev->recv = uec_recv;
1390
1391         /* Clear the ethnet address */
1392         for (i = 0; i < 6; i++)
1393                 dev->enetaddr[i] = 0;
1394
1395         eth_register(dev);
1396
1397         err = uec_startup(uec);
1398         if (err) {
1399                 printf("%s: Cannot configure net device, aborting.", dev->name);
1400                 return err;
1401         }
1402
1403 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1404         int retval;
1405         struct mii_dev *mdiodev = mdio_alloc();
1406
1407         if (!mdiodev)
1408                 return -ENOMEM;
1409         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1410         mdiodev->read = uec_miiphy_read;
1411         mdiodev->write = uec_miiphy_write;
1412
1413         retval = mdio_register(mdiodev);
1414         if (retval < 0)
1415                 return retval;
1416 #endif
1417
1418         return 1;
1419 }
1420
1421 int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num)
1422 {
1423         int i;
1424
1425         for (i = 0; i < num; i++)
1426                 uec_initialize(bis, &uecs[i]);
1427
1428         return 0;
1429 }
1430
1431 int uec_standard_init(struct bd_info *bis)
1432 {
1433         return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1434 }