2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
34 #ifdef CONFIG_UEC_ETH1
35 static uec_info_t eth1_uec_info = {
37 .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
38 .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
39 .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
40 .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
42 #if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
43 .num_threads_tx = UEC_NUM_OF_THREADS_1,
44 .num_threads_rx = UEC_NUM_OF_THREADS_1,
46 .num_threads_tx = UEC_NUM_OF_THREADS_4,
47 .num_threads_rx = UEC_NUM_OF_THREADS_4,
49 #if (MAX_QE_RISC == 4)
50 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
51 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
53 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
54 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
58 .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
59 .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
62 #ifdef CONFIG_UEC_ETH2
63 static uec_info_t eth2_uec_info = {
65 .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
66 .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
67 .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
68 .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
70 #if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
71 .num_threads_tx = UEC_NUM_OF_THREADS_1,
72 .num_threads_rx = UEC_NUM_OF_THREADS_1,
74 .num_threads_tx = UEC_NUM_OF_THREADS_4,
75 .num_threads_rx = UEC_NUM_OF_THREADS_4,
77 #if (MAX_QE_RISC == 4)
78 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
79 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
81 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
82 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
86 .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
87 .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
90 #ifdef CONFIG_UEC_ETH3
91 static uec_info_t eth3_uec_info = {
93 .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
94 .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
95 .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
96 .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
98 #if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
99 .num_threads_tx = UEC_NUM_OF_THREADS_1,
100 .num_threads_rx = UEC_NUM_OF_THREADS_1,
102 .num_threads_tx = UEC_NUM_OF_THREADS_4,
103 .num_threads_rx = UEC_NUM_OF_THREADS_4,
105 #if (MAX_QE_RISC == 4)
106 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
107 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
109 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
110 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
112 .tx_bd_ring_len = 16,
113 .rx_bd_ring_len = 16,
114 .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
115 .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
118 #ifdef CONFIG_UEC_ETH4
119 static uec_info_t eth4_uec_info = {
121 .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
122 .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
123 .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
124 .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
126 #if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
127 .num_threads_tx = UEC_NUM_OF_THREADS_1,
128 .num_threads_rx = UEC_NUM_OF_THREADS_1,
130 .num_threads_tx = UEC_NUM_OF_THREADS_4,
131 .num_threads_rx = UEC_NUM_OF_THREADS_4,
133 #if (MAX_QE_RISC == 4)
134 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
135 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
137 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
138 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
140 .tx_bd_ring_len = 16,
141 .rx_bd_ring_len = 16,
142 .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
143 .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
146 #ifdef CONFIG_UEC_ETH5
147 static uec_info_t eth5_uec_info = {
149 .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
150 .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
151 .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
152 .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
154 #if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
155 .num_threads_tx = UEC_NUM_OF_THREADS_1,
156 .num_threads_rx = UEC_NUM_OF_THREADS_1,
158 .num_threads_tx = UEC_NUM_OF_THREADS_4,
159 .num_threads_rx = UEC_NUM_OF_THREADS_4,
161 #if (MAX_QE_RISC == 4)
162 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
163 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
165 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
166 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
168 .tx_bd_ring_len = 16,
169 .rx_bd_ring_len = 16,
170 .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
171 .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
174 #ifdef CONFIG_UEC_ETH6
175 static uec_info_t eth6_uec_info = {
177 .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
178 .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
179 .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
180 .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
182 #if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
183 .num_threads_tx = UEC_NUM_OF_THREADS_1,
184 .num_threads_rx = UEC_NUM_OF_THREADS_1,
186 .num_threads_tx = UEC_NUM_OF_THREADS_4,
187 .num_threads_rx = UEC_NUM_OF_THREADS_4,
189 #if (MAX_QE_RISC == 4)
190 .risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS,
191 .risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS,
193 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
194 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
196 .tx_bd_ring_len = 16,
197 .rx_bd_ring_len = 16,
198 .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
199 .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
203 #define MAXCONTROLLERS (6)
205 static struct eth_device *devlist[MAXCONTROLLERS];
207 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
208 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
210 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
216 printf("%s: uec not initial\n", __FUNCTION__);
219 uec_regs = uec->uec_regs;
221 maccfg1 = in_be32(&uec_regs->maccfg1);
223 if (mode & COMM_DIR_TX) {
224 maccfg1 |= MACCFG1_ENABLE_TX;
225 out_be32(&uec_regs->maccfg1, maccfg1);
226 uec->mac_tx_enabled = 1;
229 if (mode & COMM_DIR_RX) {
230 maccfg1 |= MACCFG1_ENABLE_RX;
231 out_be32(&uec_regs->maccfg1, maccfg1);
232 uec->mac_rx_enabled = 1;
238 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
244 printf("%s: uec not initial\n", __FUNCTION__);
247 uec_regs = uec->uec_regs;
249 maccfg1 = in_be32(&uec_regs->maccfg1);
251 if (mode & COMM_DIR_TX) {
252 maccfg1 &= ~MACCFG1_ENABLE_TX;
253 out_be32(&uec_regs->maccfg1, maccfg1);
254 uec->mac_tx_enabled = 0;
257 if (mode & COMM_DIR_RX) {
258 maccfg1 &= ~MACCFG1_ENABLE_RX;
259 out_be32(&uec_regs->maccfg1, maccfg1);
260 uec->mac_rx_enabled = 0;
266 static int uec_graceful_stop_tx(uec_private_t *uec)
272 if (!uec || !uec->uccf) {
273 printf("%s: No handle passed.\n", __FUNCTION__);
277 uf_regs = uec->uccf->uf_regs;
279 /* Clear the grace stop event */
280 out_be32(&uf_regs->ucce, UCCE_GRA);
282 /* Issue host command */
284 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
285 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
286 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
288 /* Wait for command to complete */
290 ucce = in_be32(&uf_regs->ucce);
291 } while (! (ucce & UCCE_GRA));
293 uec->grace_stopped_tx = 1;
298 static int uec_graceful_stop_rx(uec_private_t *uec)
304 printf("%s: No handle passed.\n", __FUNCTION__);
308 if (!uec->p_rx_glbl_pram) {
309 printf("%s: No init rx global parameter\n", __FUNCTION__);
313 /* Clear acknowledge bit */
314 ack = uec->p_rx_glbl_pram->rxgstpack;
315 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
316 uec->p_rx_glbl_pram->rxgstpack = ack;
318 /* Keep issuing cmd and checking ack bit until it is asserted */
320 /* Issue host command */
322 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
323 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
324 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
325 ack = uec->p_rx_glbl_pram->rxgstpack;
326 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
328 uec->grace_stopped_rx = 1;
333 static int uec_restart_tx(uec_private_t *uec)
337 if (!uec || !uec->uec_info) {
338 printf("%s: No handle passed.\n", __FUNCTION__);
343 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
344 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
345 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
347 uec->grace_stopped_tx = 0;
352 static int uec_restart_rx(uec_private_t *uec)
356 if (!uec || !uec->uec_info) {
357 printf("%s: No handle passed.\n", __FUNCTION__);
362 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
363 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
364 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
366 uec->grace_stopped_rx = 0;
371 static int uec_open(uec_private_t *uec, comm_dir_e mode)
373 ucc_fast_private_t *uccf;
375 if (!uec || !uec->uccf) {
376 printf("%s: No handle passed.\n", __FUNCTION__);
381 /* check if the UCC number is in range. */
382 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
383 printf("%s: ucc_num out of range.\n", __FUNCTION__);
388 uec_mac_enable(uec, mode);
390 /* Enable UCC fast */
391 ucc_fast_enable(uccf, mode);
393 /* RISC microcode start */
394 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
397 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
404 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
406 ucc_fast_private_t *uccf;
408 if (!uec || !uec->uccf) {
409 printf("%s: No handle passed.\n", __FUNCTION__);
414 /* check if the UCC number is in range. */
415 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
416 printf("%s: ucc_num out of range.\n", __FUNCTION__);
419 /* Stop any transmissions */
420 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
421 uec_graceful_stop_tx(uec);
423 /* Stop any receptions */
424 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
425 uec_graceful_stop_rx(uec);
428 /* Disable the UCC fast */
429 ucc_fast_disable(uec->uccf, mode);
431 /* Disable the MAC */
432 uec_mac_disable(uec, mode);
437 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
443 printf("%s: uec not initial\n", __FUNCTION__);
446 uec_regs = uec->uec_regs;
448 if (duplex == DUPLEX_HALF) {
449 maccfg2 = in_be32(&uec_regs->maccfg2);
450 maccfg2 &= ~MACCFG2_FDX;
451 out_be32(&uec_regs->maccfg2, maccfg2);
454 if (duplex == DUPLEX_FULL) {
455 maccfg2 = in_be32(&uec_regs->maccfg2);
456 maccfg2 |= MACCFG2_FDX;
457 out_be32(&uec_regs->maccfg2, maccfg2);
463 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
465 enet_interface_e enet_if_mode;
466 uec_info_t *uec_info;
472 printf("%s: uec not initial\n", __FUNCTION__);
476 uec_info = uec->uec_info;
477 uec_regs = uec->uec_regs;
478 enet_if_mode = if_mode;
480 maccfg2 = in_be32(&uec_regs->maccfg2);
481 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
483 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
484 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
486 switch (enet_if_mode) {
489 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
492 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
495 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
499 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
500 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
502 case ENET_1000_RGMII_RXID:
503 case ENET_1000_RGMII_ID:
504 case ENET_1000_RGMII:
505 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
509 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
513 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
514 upsmr |= (UPSMR_RPM | UPSMR_R10M);
517 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
521 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
522 upsmr |= (UPSMR_R10M | UPSMR_RMM);
528 out_be32(&uec_regs->maccfg2, maccfg2);
529 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
534 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
536 uint timeout = 0x1000;
539 miimcfg = in_be32(&uec_mii_regs->miimcfg);
540 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
541 out_be32(&uec_mii_regs->miimcfg, miimcfg);
543 /* Wait until the bus is free */
544 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
546 printf("%s: The MII Bus is stuck!", __FUNCTION__);
553 static int init_phy(struct eth_device *dev)
556 uec_mii_t *umii_regs;
557 struct uec_mii_info *mii_info;
558 struct phy_info *curphy;
561 uec = (uec_private_t *)dev->priv;
562 umii_regs = uec->uec_mii_regs;
568 mii_info = malloc(sizeof(*mii_info));
570 printf("%s: Could not allocate mii_info", dev->name);
573 memset(mii_info, 0, sizeof(*mii_info));
575 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
576 mii_info->speed = SPEED_1000;
578 mii_info->speed = SPEED_100;
581 mii_info->duplex = DUPLEX_FULL;
585 mii_info->advertising = (ADVERTISED_10baseT_Half |
586 ADVERTISED_10baseT_Full |
587 ADVERTISED_100baseT_Half |
588 ADVERTISED_100baseT_Full |
589 ADVERTISED_1000baseT_Full);
590 mii_info->autoneg = 1;
591 mii_info->mii_id = uec->uec_info->phy_address;
594 mii_info->mdio_read = &uec_read_phy_reg;
595 mii_info->mdio_write = &uec_write_phy_reg;
597 uec->mii_info = mii_info;
599 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
601 if (init_mii_management_configuration(umii_regs)) {
602 printf("%s: The MII Bus is stuck!", dev->name);
607 /* get info for this PHY */
608 curphy = uec_get_phy_info(uec->mii_info);
610 printf("%s: No PHY found", dev->name);
615 mii_info->phyinfo = curphy;
617 /* Run the commands which initialize the PHY */
619 err = curphy->init(uec->mii_info);
633 static void adjust_link(struct eth_device *dev)
635 uec_private_t *uec = (uec_private_t *)dev->priv;
637 struct uec_mii_info *mii_info = uec->mii_info;
639 extern void change_phy_interface_mode(struct eth_device *dev,
640 enet_interface_e mode);
641 uec_regs = uec->uec_regs;
643 if (mii_info->link) {
644 /* Now we make sure that we can be in full duplex mode.
645 * If not, we operate in half-duplex mode. */
646 if (mii_info->duplex != uec->oldduplex) {
647 if (!(mii_info->duplex)) {
648 uec_set_mac_duplex(uec, DUPLEX_HALF);
649 printf("%s: Half Duplex\n", dev->name);
651 uec_set_mac_duplex(uec, DUPLEX_FULL);
652 printf("%s: Full Duplex\n", dev->name);
654 uec->oldduplex = mii_info->duplex;
657 if (mii_info->speed != uec->oldspeed) {
658 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
659 switch (mii_info->speed) {
663 printf ("switching to rgmii 100\n");
664 /* change phy to rgmii 100 */
665 change_phy_interface_mode(dev,
667 /* change the MAC interface mode */
668 uec_set_mac_if_mode(uec,ENET_100_RGMII);
671 printf ("switching to rgmii 10\n");
672 /* change phy to rgmii 10 */
673 change_phy_interface_mode(dev,
675 /* change the MAC interface mode */
676 uec_set_mac_if_mode(uec,ENET_10_RGMII);
679 printf("%s: Ack,Speed(%d)is illegal\n",
680 dev->name, mii_info->speed);
685 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
686 uec->oldspeed = mii_info->speed;
690 printf("%s: Link is up\n", dev->name);
694 } else { /* if (mii_info->link) */
696 printf("%s: Link is down\n", dev->name);
704 static void phy_change(struct eth_device *dev)
706 uec_private_t *uec = (uec_private_t *)dev->priv;
708 /* Update the link, speed, duplex */
709 uec->mii_info->phyinfo->read_status(uec->mii_info);
711 /* Adjust the interface according to speed */
715 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
716 && !defined(BITBANGMII)
719 * Find a device index from the devlist by name
722 * The index where the device is located, -1 on error
724 static int uec_miiphy_find_dev_by_name(char *devname)
728 for (i = 0; i < MAXCONTROLLERS; i++) {
729 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
734 /* If device cannot be found, returns -1 */
735 if (i == MAXCONTROLLERS) {
736 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
744 * Read a MII PHY register.
749 static int uec_miiphy_read(char *devname, unsigned char addr,
750 unsigned char reg, unsigned short *value)
754 if (devname == NULL || value == NULL) {
755 debug("%s: NULL pointer given\n", __FUNCTION__);
757 devindex = uec_miiphy_find_dev_by_name(devname);
759 *value = uec_read_phy_reg(devlist[devindex], addr, reg);
766 * Write a MII PHY register.
771 static int uec_miiphy_write(char *devname, unsigned char addr,
772 unsigned char reg, unsigned short value)
776 if (devname == NULL) {
777 debug("%s: NULL pointer given\n", __FUNCTION__);
779 devindex = uec_miiphy_find_dev_by_name(devname);
781 uec_write_phy_reg(devlist[devindex], addr, reg, value);
788 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
795 printf("%s: uec not initial\n", __FUNCTION__);
799 uec_regs = uec->uec_regs;
801 /* if a station address of 0x12345678ABCD, perform a write to
802 MACSTNADDR1 of 0xCDAB7856,
803 MACSTNADDR2 of 0x34120000 */
805 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
806 (mac_addr[3] << 8) | (mac_addr[2]);
807 out_be32(&uec_regs->macstnaddr1, mac_addr1);
809 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
810 out_be32(&uec_regs->macstnaddr2, mac_addr2);
815 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
816 int *threads_num_ret)
818 int num_threads_numerica;
820 switch (threads_num) {
821 case UEC_NUM_OF_THREADS_1:
822 num_threads_numerica = 1;
824 case UEC_NUM_OF_THREADS_2:
825 num_threads_numerica = 2;
827 case UEC_NUM_OF_THREADS_4:
828 num_threads_numerica = 4;
830 case UEC_NUM_OF_THREADS_6:
831 num_threads_numerica = 6;
833 case UEC_NUM_OF_THREADS_8:
834 num_threads_numerica = 8;
837 printf("%s: Bad number of threads value.",
842 *threads_num_ret = num_threads_numerica;
847 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
849 uec_info_t *uec_info;
854 uec_info = uec->uec_info;
856 /* Alloc global Tx parameter RAM page */
857 uec->tx_glbl_pram_offset = qe_muram_alloc(
858 sizeof(uec_tx_global_pram_t),
859 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
860 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
861 qe_muram_addr(uec->tx_glbl_pram_offset);
863 /* Zero the global Tx prameter RAM */
864 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
866 /* Init global Tx parameter RAM */
868 /* TEMODER, RMON statistics disable, one Tx queue */
869 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
872 uec->send_q_mem_reg_offset = qe_muram_alloc(
873 sizeof(uec_send_queue_qd_t),
874 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
875 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
876 qe_muram_addr(uec->send_q_mem_reg_offset);
877 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
879 /* Setup the table with TxBDs ring */
880 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
882 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
883 (u32)(uec->p_tx_bd_ring));
884 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
887 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
888 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
890 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
891 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
893 /* TSTATE, global snooping, big endian, the CSB bus selected */
894 bmrx = BMR_INIT_VALUE;
895 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
898 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
899 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
903 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
904 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
908 uec->thread_dat_tx_offset = qe_muram_alloc(
909 num_threads_tx * sizeof(uec_thread_data_tx_t) +
910 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
912 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
913 qe_muram_addr(uec->thread_dat_tx_offset);
914 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
917 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
921 uec_82xx_address_filtering_pram_t *p_af_pram;
923 /* Allocate global Rx parameter RAM page */
924 uec->rx_glbl_pram_offset = qe_muram_alloc(
925 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
926 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
927 qe_muram_addr(uec->rx_glbl_pram_offset);
929 /* Zero Global Rx parameter RAM */
930 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
932 /* Init global Rx parameter RAM */
933 /* REMODER, Extended feature mode disable, VLAN disable,
934 LossLess flow control disable, Receive firmware statisic disable,
935 Extended address parsing mode disable, One Rx queues,
936 Dynamic maximum/minimum frame length disable, IP checksum check
937 disable, IP address alignment disable
939 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
942 uec->thread_dat_rx_offset = qe_muram_alloc(
943 num_threads_rx * sizeof(uec_thread_data_rx_t),
944 UEC_THREAD_DATA_ALIGNMENT);
945 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
946 qe_muram_addr(uec->thread_dat_rx_offset);
947 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
950 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
952 /* RxRMON base pointer, we don't need it */
953 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
955 /* IntCoalescingPTR, we don't need it, no interrupt */
956 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
958 /* RSTATE, global snooping, big endian, the CSB bus selected */
959 bmrx = BMR_INIT_VALUE;
960 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
963 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
966 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
967 sizeof(uec_rx_bd_queues_entry_t) + \
968 sizeof(uec_rx_prefetched_bds_t),
969 UEC_RX_BD_QUEUES_ALIGNMENT);
970 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
971 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
974 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
975 sizeof(uec_rx_prefetched_bds_t));
976 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
977 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
978 (u32)uec->p_rx_bd_ring);
981 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
983 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
985 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
987 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
989 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
991 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
993 for (i = 0; i < 8; i++) {
994 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
998 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
1000 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
1002 /* Clear PQ2 style address filtering hash table */
1003 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
1004 uec->p_rx_glbl_pram->addressfiltering;
1006 p_af_pram->iaddr_h = 0;
1007 p_af_pram->iaddr_l = 0;
1008 p_af_pram->gaddr_h = 0;
1009 p_af_pram->gaddr_l = 0;
1012 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
1013 int thread_tx, int thread_rx)
1015 uec_init_cmd_pram_t *p_init_enet_param;
1016 u32 init_enet_param_offset;
1017 uec_info_t *uec_info;
1020 u32 init_enet_offset;
1025 uec_info = uec->uec_info;
1027 /* Allocate init enet command parameter */
1028 uec->init_enet_param_offset = qe_muram_alloc(
1029 sizeof(uec_init_cmd_pram_t), 4);
1030 init_enet_param_offset = uec->init_enet_param_offset;
1031 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
1032 qe_muram_addr(uec->init_enet_param_offset);
1034 /* Zero init enet command struct */
1035 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
1037 /* Init the command struct */
1038 p_init_enet_param = uec->p_init_enet_param;
1039 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
1040 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
1041 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
1042 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
1043 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
1044 p_init_enet_param->largestexternallookupkeysize = 0;
1046 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
1047 << ENET_INIT_PARAM_RGF_SHIFT;
1048 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
1049 << ENET_INIT_PARAM_TGF_SHIFT;
1051 /* Init Rx global parameter pointer */
1052 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
1053 (u32)uec_info->risc_rx;
1055 /* Init Rx threads */
1056 for (i = 0; i < (thread_rx + 1); i++) {
1057 if ((snum = qe_get_snum()) < 0) {
1058 printf("%s can not get snum\n", __FUNCTION__);
1063 init_enet_offset = 0;
1065 init_enet_offset = qe_muram_alloc(
1066 sizeof(uec_thread_rx_pram_t),
1067 UEC_THREAD_RX_PRAM_ALIGNMENT);
1070 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1071 init_enet_offset | (u32)uec_info->risc_rx;
1072 p_init_enet_param->rxthread[i] = entry_val;
1075 /* Init Tx global parameter pointer */
1076 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
1077 (u32)uec_info->risc_tx;
1079 /* Init Tx threads */
1080 for (i = 0; i < thread_tx; i++) {
1081 if ((snum = qe_get_snum()) < 0) {
1082 printf("%s can not get snum\n", __FUNCTION__);
1086 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
1087 UEC_THREAD_TX_PRAM_ALIGNMENT);
1089 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1090 init_enet_offset | (u32)uec_info->risc_tx;
1091 p_init_enet_param->txthread[i] = entry_val;
1094 __asm__ __volatile__("sync");
1096 /* Issue QE command */
1097 command = QE_INIT_TX_RX;
1098 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1099 uec->uec_info->uf_info.ucc_num);
1100 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1101 init_enet_param_offset);
1106 static int uec_startup(uec_private_t *uec)
1108 uec_info_t *uec_info;
1109 ucc_fast_info_t *uf_info;
1110 ucc_fast_private_t *uccf;
1111 ucc_fast_t *uf_regs;
1116 enet_interface_e enet_interface;
1123 if (!uec || !uec->uec_info) {
1124 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1128 uec_info = uec->uec_info;
1129 uf_info = &(uec_info->uf_info);
1131 /* Check if Rx BD ring len is illegal */
1132 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1133 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1134 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1139 /* Check if Tx BD ring len is illegal */
1140 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1141 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1146 /* Check if MRBLR is illegal */
1147 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
1148 printf("%s: max rx buffer length must be mutliple of 128.\n",
1153 /* Both Rx and Tx are stopped */
1154 uec->grace_stopped_rx = 1;
1155 uec->grace_stopped_tx = 1;
1158 if (ucc_fast_init(uf_info, &uccf)) {
1159 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1166 /* Convert the Tx threads number */
1167 if (uec_convert_threads_num(uec_info->num_threads_tx,
1172 /* Convert the Rx threads number */
1173 if (uec_convert_threads_num(uec_info->num_threads_rx,
1178 uf_regs = uccf->uf_regs;
1180 /* UEC register is following UCC fast registers */
1181 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1183 /* Save the UEC register pointer to UEC private struct */
1184 uec->uec_regs = uec_regs;
1186 /* Init UPSMR, enable hardware statistics (UCC) */
1187 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1189 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1190 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1192 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1193 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1195 /* Setup MAC interface mode */
1196 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1198 /* Setup MII management base */
1199 #ifndef CONFIG_eTSEC_MDIO_BUS
1200 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1202 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1205 /* Setup MII master clock source */
1206 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1209 utbipar = in_be32(&uec_regs->utbipar);
1210 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1211 enet_interface = uec->uec_info->enet_interface;
1212 if (enet_interface == ENET_1000_TBI ||
1213 enet_interface == ENET_1000_RTBI) {
1214 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1215 << UTBIPAR_PHY_ADDRESS_SHIFT;
1217 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1218 << UTBIPAR_PHY_ADDRESS_SHIFT;
1221 out_be32(&uec_regs->utbipar, utbipar);
1223 /* Allocate Tx BDs */
1224 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1225 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1226 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1227 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1228 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1229 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1232 align = UEC_TX_BD_RING_ALIGNMENT;
1233 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1234 if (uec->tx_bd_ring_offset != 0) {
1235 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1239 /* Zero all of Tx BDs */
1240 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1242 /* Allocate Rx BDs */
1243 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1244 align = UEC_RX_BD_RING_ALIGNMENT;
1245 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1246 if (uec->rx_bd_ring_offset != 0) {
1247 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1251 /* Zero all of Rx BDs */
1252 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1254 /* Allocate Rx buffer */
1255 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1256 align = UEC_RX_DATA_BUF_ALIGNMENT;
1257 uec->rx_buf_offset = (u32)malloc(length + align);
1258 if (uec->rx_buf_offset != 0) {
1259 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1263 /* Zero all of the Rx buffer */
1264 memset((void *)(uec->rx_buf_offset), 0, length + align);
1266 /* Init TxBD ring */
1267 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1270 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1272 BD_STATUS_SET(bd, 0);
1273 BD_LENGTH_SET(bd, 0);
1276 BD_STATUS_SET((--bd), TxBD_WRAP);
1278 /* Init RxBD ring */
1279 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1281 buf = uec->p_rx_buf;
1282 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1283 BD_DATA_SET(bd, buf);
1284 BD_LENGTH_SET(bd, 0);
1285 BD_STATUS_SET(bd, RxBD_EMPTY);
1286 buf += MAX_RXBUF_LEN;
1289 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1291 /* Init global Tx parameter RAM */
1292 uec_init_tx_parameter(uec, num_threads_tx);
1294 /* Init global Rx parameter RAM */
1295 uec_init_rx_parameter(uec, num_threads_rx);
1297 /* Init ethernet Tx and Rx parameter command */
1298 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1300 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1307 static int uec_init(struct eth_device* dev, bd_t *bd)
1311 struct phy_info *curphy;
1313 uec = (uec_private_t *)dev->priv;
1315 if (uec->the_first_run == 0) {
1316 err = init_phy(dev);
1318 printf("%s: Cannot initialize PHY, aborting.\n",
1323 curphy = uec->mii_info->phyinfo;
1325 if (curphy->config_aneg) {
1326 err = curphy->config_aneg(uec->mii_info);
1328 printf("%s: Can't negotiate PHY\n", dev->name);
1333 /* Give PHYs up to 5 sec to report a link */
1336 err = curphy->read_status(uec->mii_info);
1338 } while (((i-- > 0) && !uec->mii_info->link) || err);
1341 printf("warning: %s: timeout on PHY link\n", dev->name);
1343 uec->the_first_run = 1;
1346 /* Set up the MAC address */
1347 if (dev->enetaddr[0] & 0x01) {
1348 printf("%s: MacAddress is multcast address\n",
1352 uec_set_mac_address(uec, dev->enetaddr);
1355 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1357 printf("%s: cannot enable UEC device\n", dev->name);
1363 return (uec->mii_info->link ? 0 : -1);
1366 static void uec_halt(struct eth_device* dev)
1368 uec_private_t *uec = (uec_private_t *)dev->priv;
1369 uec_stop(uec, COMM_DIR_RX_AND_TX);
1372 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1375 ucc_fast_private_t *uccf;
1376 volatile qe_bd_t *bd;
1381 uec = (uec_private_t *)dev->priv;
1385 /* Find an empty TxBD */
1386 for (i = 0; bd->status & TxBD_READY; i++) {
1388 printf("%s: tx buffer not ready\n", dev->name);
1394 BD_DATA_SET(bd, buf);
1395 BD_LENGTH_SET(bd, len);
1396 status = bd->status;
1398 status |= (TxBD_READY | TxBD_LAST);
1399 BD_STATUS_SET(bd, status);
1401 /* Tell UCC to transmit the buffer */
1402 ucc_fast_transmit_on_demand(uccf);
1404 /* Wait for buffer to be transmitted */
1405 for (i = 0; bd->status & TxBD_READY; i++) {
1407 printf("%s: tx error\n", dev->name);
1412 /* Ok, the buffer be transimitted */
1413 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1420 static int uec_recv(struct eth_device* dev)
1422 uec_private_t *uec = dev->priv;
1423 volatile qe_bd_t *bd;
1429 status = bd->status;
1431 while (!(status & RxBD_EMPTY)) {
1432 if (!(status & RxBD_ERROR)) {
1434 len = BD_LENGTH(bd);
1435 NetReceive(data, len);
1437 printf("%s: Rx error\n", dev->name);
1440 BD_LENGTH_SET(bd, 0);
1441 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1442 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1443 status = bd->status;
1450 int uec_initialize(int index)
1452 struct eth_device *dev;
1455 uec_info_t *uec_info;
1458 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1461 memset(dev, 0, sizeof(struct eth_device));
1463 /* Allocate the UEC private struct */
1464 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1468 memset(uec, 0, sizeof(uec_private_t));
1470 /* Init UEC private struct, they come from board.h */
1473 #ifdef CONFIG_UEC_ETH1
1474 uec_info = ð1_uec_info;
1476 } else if (index == 1) {
1477 #ifdef CONFIG_UEC_ETH2
1478 uec_info = ð2_uec_info;
1480 } else if (index == 2) {
1481 #ifdef CONFIG_UEC_ETH3
1482 uec_info = ð3_uec_info;
1484 } else if (index == 3) {
1485 #ifdef CONFIG_UEC_ETH4
1486 uec_info = ð4_uec_info;
1488 } else if (index == 4) {
1489 #ifdef CONFIG_UEC_ETH5
1490 uec_info = ð5_uec_info;
1492 } else if (index == 5) {
1493 #ifdef CONFIG_UEC_ETH6
1494 uec_info = ð6_uec_info;
1497 printf("%s: index is illegal.\n", __FUNCTION__);
1501 devlist[index] = dev;
1503 uec->uec_info = uec_info;
1505 sprintf(dev->name, "FSL UEC%d", index);
1507 dev->priv = (void *)uec;
1508 dev->init = uec_init;
1509 dev->halt = uec_halt;
1510 dev->send = uec_send;
1511 dev->recv = uec_recv;
1513 /* Clear the ethnet address */
1514 for (i = 0; i < 6; i++)
1515 dev->enetaddr[i] = 0;
1519 err = uec_startup(uec);
1521 printf("%s: Cannot configure net device, aborting.",dev->name);
1525 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1526 && !defined(BITBANGMII)
1527 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);