drivers/qe/uec.c

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "common.h"
  23 #include "net.h"
  24 #include "malloc.h"
  25 #include "asm/errno.h"
  26 #include "asm/io.h"
  27 #include "asm/immap_qe.h"
  28 #include "qe.h"
  29 #include "uccf.h"
  30 #include "uec.h"
  31 #include "uec_phy.h"
  32 #include "miiphy.h"
  33
  34 #ifdef CONFIG_UEC_ETH1
  35 static uec_info_t eth1_uec_info = {
  36         .uf_info                = {
  37                 .ucc_num        = CONFIG_SYS_UEC1_UCC_NUM,
  38                 .rx_clock       = CONFIG_SYS_UEC1_RX_CLK,
  39                 .tx_clock       = CONFIG_SYS_UEC1_TX_CLK,
  40                 .eth_type       = CONFIG_SYS_UEC1_ETH_TYPE,
  41         },
  42 #if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
  43         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  44         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  45 #else
  46         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  47         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  48 #endif
  49 #if (MAX_QE_RISC == 4)
  50         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
  51         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
  52 #else
  53         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  54         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  55 #endif
  56         .tx_bd_ring_len         = 16,
  57         .rx_bd_ring_len         = 16,
  58         .phy_address            = CONFIG_SYS_UEC1_PHY_ADDR,
  59         .enet_interface         = CONFIG_SYS_UEC1_INTERFACE_MODE,
  60 };
  61 #endif
  62 #ifdef CONFIG_UEC_ETH2
  63 static uec_info_t eth2_uec_info = {
  64         .uf_info                = {
  65                 .ucc_num        = CONFIG_SYS_UEC2_UCC_NUM,
  66                 .rx_clock       = CONFIG_SYS_UEC2_RX_CLK,
  67                 .tx_clock       = CONFIG_SYS_UEC2_TX_CLK,
  68                 .eth_type       = CONFIG_SYS_UEC2_ETH_TYPE,
  69         },
  70 #if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
  71         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  72         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  73 #else
  74         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  75         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  76 #endif
  77 #if (MAX_QE_RISC == 4)
  78         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
  79         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
  80 #else
  81         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  82         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  83 #endif
  84         .tx_bd_ring_len         = 16,
  85         .rx_bd_ring_len         = 16,
  86         .phy_address            = CONFIG_SYS_UEC2_PHY_ADDR,
  87         .enet_interface         = CONFIG_SYS_UEC2_INTERFACE_MODE,
  88 };
  89 #endif
  90 #ifdef CONFIG_UEC_ETH3
  91 static uec_info_t eth3_uec_info = {
  92         .uf_info                = {
  93                 .ucc_num        = CONFIG_SYS_UEC3_UCC_NUM,
  94                 .rx_clock       = CONFIG_SYS_UEC3_RX_CLK,
  95                 .tx_clock       = CONFIG_SYS_UEC3_TX_CLK,
  96                 .eth_type       = CONFIG_SYS_UEC3_ETH_TYPE,
  97         },
  98 #if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
  99         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 100         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 101 #else
 102         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 103         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 104 #endif
 105 #if (MAX_QE_RISC == 4)
 106         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 107         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 108 #else
 109         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 110         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 111 #endif
 112         .tx_bd_ring_len         = 16,
 113         .rx_bd_ring_len         = 16,
 114         .phy_address            = CONFIG_SYS_UEC3_PHY_ADDR,
 115         .enet_interface         = CONFIG_SYS_UEC3_INTERFACE_MODE,
 116 };
 117 #endif
 118 #ifdef CONFIG_UEC_ETH4
 119 static uec_info_t eth4_uec_info = {
 120         .uf_info                = {
 121                 .ucc_num        = CONFIG_SYS_UEC4_UCC_NUM,
 122                 .rx_clock       = CONFIG_SYS_UEC4_RX_CLK,
 123                 .tx_clock       = CONFIG_SYS_UEC4_TX_CLK,
 124                 .eth_type       = CONFIG_SYS_UEC4_ETH_TYPE,
 125         },
 126 #if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
 127         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 128         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 129 #else
 130         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 131         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 132 #endif
 133 #if (MAX_QE_RISC == 4)
 134         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 135         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 136 #else
 137         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 138         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 139 #endif
 140         .tx_bd_ring_len         = 16,
 141         .rx_bd_ring_len         = 16,
 142         .phy_address            = CONFIG_SYS_UEC4_PHY_ADDR,
 143         .enet_interface         = CONFIG_SYS_UEC4_INTERFACE_MODE,
 144 };
 145 #endif
 146 #ifdef CONFIG_UEC_ETH5
 147 static uec_info_t eth5_uec_info = {
 148         .uf_info                = {
 149                 .ucc_num        = CONFIG_SYS_UEC5_UCC_NUM,
 150                 .rx_clock       = CONFIG_SYS_UEC5_RX_CLK,
 151                 .tx_clock       = CONFIG_SYS_UEC5_TX_CLK,
 152                 .eth_type       = CONFIG_SYS_UEC5_ETH_TYPE,
 153         },
 154 #if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
 155         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 156         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 157 #else
 158         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 159         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 160 #endif
 161 #if (MAX_QE_RISC == 4)
 162         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 163         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 164 #else
 165         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 166         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 167 #endif
 168         .tx_bd_ring_len         = 16,
 169         .rx_bd_ring_len         = 16,
 170         .phy_address            = CONFIG_SYS_UEC5_PHY_ADDR,
 171         .enet_interface         = CONFIG_SYS_UEC5_INTERFACE_MODE,
 172 };
 173 #endif
 174 #ifdef CONFIG_UEC_ETH6
 175 static uec_info_t eth6_uec_info = {
 176         .uf_info                = {
 177                 .ucc_num        = CONFIG_SYS_UEC6_UCC_NUM,
 178                 .rx_clock       = CONFIG_SYS_UEC6_RX_CLK,
 179                 .tx_clock       = CONFIG_SYS_UEC6_TX_CLK,
 180                 .eth_type       = CONFIG_SYS_UEC6_ETH_TYPE,
 181         },
 182 #if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
 183         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 184         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 185 #else
 186         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 187         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 188 #endif
 189 #if (MAX_QE_RISC == 4)
 190         .risc_tx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 191         .risc_rx                        = QE_RISC_ALLOCATION_FOUR_RISCS,
 192 #else
 193         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 194         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 195 #endif
 196         .tx_bd_ring_len         = 16,
 197         .rx_bd_ring_len         = 16,
 198         .phy_address            = CONFIG_SYS_UEC6_PHY_ADDR,
 199         .enet_interface         = CONFIG_SYS_UEC6_INTERFACE_MODE,
 200 };
 201 #endif
 202
 203 #define MAXCONTROLLERS  (6)
 204
 205 static struct eth_device *devlist[MAXCONTROLLERS];
 206
 207 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
 208 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
 209
 210 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 211 {
 212         uec_t           *uec_regs;
 213         u32             maccfg1;
 214
 215         if (!uec) {
 216                 printf("%s: uec not initial\n", __FUNCTION__);
 217                 return -EINVAL;
 218         }
 219         uec_regs = uec->uec_regs;
 220
 221         maccfg1 = in_be32(&uec_regs->maccfg1);
 222
 223         if (mode & COMM_DIR_TX) {
 224                 maccfg1 |= MACCFG1_ENABLE_TX;
 225                 out_be32(&uec_regs->maccfg1, maccfg1);
 226                 uec->mac_tx_enabled = 1;
 227         }
 228
 229         if (mode & COMM_DIR_RX) {
 230                 maccfg1 |= MACCFG1_ENABLE_RX;
 231                 out_be32(&uec_regs->maccfg1, maccfg1);
 232                 uec->mac_rx_enabled = 1;
 233         }
 234
 235         return 0;
 236 }
 237
 238 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
 239 {
 240         uec_t           *uec_regs;
 241         u32             maccfg1;
 242
 243         if (!uec) {
 244                 printf("%s: uec not initial\n", __FUNCTION__);
 245                 return -EINVAL;
 246         }
 247         uec_regs = uec->uec_regs;
 248
 249         maccfg1 = in_be32(&uec_regs->maccfg1);
 250
 251         if (mode & COMM_DIR_TX) {
 252                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 253                 out_be32(&uec_regs->maccfg1, maccfg1);
 254                 uec->mac_tx_enabled = 0;
 255         }
 256
 257         if (mode & COMM_DIR_RX) {
 258                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 259                 out_be32(&uec_regs->maccfg1, maccfg1);
 260                 uec->mac_rx_enabled = 0;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int uec_graceful_stop_tx(uec_private_t *uec)
 267 {
 268         ucc_fast_t              *uf_regs;
 269         u32                     cecr_subblock;
 270         u32                     ucce;
 271
 272         if (!uec || !uec->uccf) {
 273                 printf("%s: No handle passed.\n", __FUNCTION__);
 274                 return -EINVAL;
 275         }
 276
 277         uf_regs = uec->uccf->uf_regs;
 278
 279         /* Clear the grace stop event */
 280         out_be32(&uf_regs->ucce, UCCE_GRA);
 281
 282         /* Issue host command */
 283         cecr_subblock =
 284                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 285         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 286                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 287
 288         /* Wait for command to complete */
 289         do {
 290                 ucce = in_be32(&uf_regs->ucce);
 291         } while (! (ucce & UCCE_GRA));
 292
 293         uec->grace_stopped_tx = 1;
 294
 295         return 0;
 296 }
 297
 298 static int uec_graceful_stop_rx(uec_private_t *uec)
 299 {
 300         u32             cecr_subblock;
 301         u8              ack;
 302
 303         if (!uec) {
 304                 printf("%s: No handle passed.\n", __FUNCTION__);
 305                 return -EINVAL;
 306         }
 307
 308         if (!uec->p_rx_glbl_pram) {
 309                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 310                 return -EINVAL;
 311         }
 312
 313         /* Clear acknowledge bit */
 314         ack = uec->p_rx_glbl_pram->rxgstpack;
 315         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 316         uec->p_rx_glbl_pram->rxgstpack = ack;
 317
 318         /* Keep issuing cmd and checking ack bit until it is asserted */
 319         do {
 320                 /* Issue host command */
 321                 cecr_subblock =
 322                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 323                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 324                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 325                 ack = uec->p_rx_glbl_pram->rxgstpack;
 326         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 327
 328         uec->grace_stopped_rx = 1;
 329
 330         return 0;
 331 }
 332
 333 static int uec_restart_tx(uec_private_t *uec)
 334 {
 335         u32             cecr_subblock;
 336
 337         if (!uec || !uec->uec_info) {
 338                 printf("%s: No handle passed.\n", __FUNCTION__);
 339                 return -EINVAL;
 340         }
 341
 342         cecr_subblock =
 343          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 344         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 345                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 346
 347         uec->grace_stopped_tx = 0;
 348
 349         return 0;
 350 }
 351
 352 static int uec_restart_rx(uec_private_t *uec)
 353 {
 354         u32             cecr_subblock;
 355
 356         if (!uec || !uec->uec_info) {
 357                 printf("%s: No handle passed.\n", __FUNCTION__);
 358                 return -EINVAL;
 359         }
 360
 361         cecr_subblock =
 362          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 363         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 364                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 365
 366         uec->grace_stopped_rx = 0;
 367
 368         return 0;
 369 }
 370
 371 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 372 {
 373         ucc_fast_private_t      *uccf;
 374
 375         if (!uec || !uec->uccf) {
 376                 printf("%s: No handle passed.\n", __FUNCTION__);
 377                 return -EINVAL;
 378         }
 379         uccf = uec->uccf;
 380
 381         /* check if the UCC number is in range. */
 382         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 383                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 384                 return -EINVAL;
 385         }
 386
 387         /* Enable MAC */
 388         uec_mac_enable(uec, mode);
 389
 390         /* Enable UCC fast */
 391         ucc_fast_enable(uccf, mode);
 392
 393         /* RISC microcode start */
 394         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 395                 uec_restart_tx(uec);
 396         }
 397         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 398                 uec_restart_rx(uec);
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 405 {
 406         ucc_fast_private_t      *uccf;
 407
 408         if (!uec || !uec->uccf) {
 409                 printf("%s: No handle passed.\n", __FUNCTION__);
 410                 return -EINVAL;
 411         }
 412         uccf = uec->uccf;
 413
 414         /* check if the UCC number is in range. */
 415         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 416                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 417                 return -EINVAL;
 418         }
 419         /* Stop any transmissions */
 420         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 421                 uec_graceful_stop_tx(uec);
 422         }
 423         /* Stop any receptions */
 424         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 425                 uec_graceful_stop_rx(uec);
 426         }
 427
 428         /* Disable the UCC fast */
 429         ucc_fast_disable(uec->uccf, mode);
 430
 431         /* Disable the MAC */
 432         uec_mac_disable(uec, mode);
 433
 434         return 0;
 435 }
 436
 437 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 438 {
 439         uec_t           *uec_regs;
 440         u32             maccfg2;
 441
 442         if (!uec) {
 443                 printf("%s: uec not initial\n", __FUNCTION__);
 444                 return -EINVAL;
 445         }
 446         uec_regs = uec->uec_regs;
 447
 448         if (duplex == DUPLEX_HALF) {
 449                 maccfg2 = in_be32(&uec_regs->maccfg2);
 450                 maccfg2 &= ~MACCFG2_FDX;
 451                 out_be32(&uec_regs->maccfg2, maccfg2);
 452         }
 453
 454         if (duplex == DUPLEX_FULL) {
 455                 maccfg2 = in_be32(&uec_regs->maccfg2);
 456                 maccfg2 |= MACCFG2_FDX;
 457                 out_be32(&uec_regs->maccfg2, maccfg2);
 458         }
 459
 460         return 0;
 461 }
 462
 463 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 464 {
 465         enet_interface_e        enet_if_mode;
 466         uec_info_t              *uec_info;
 467         uec_t                   *uec_regs;
 468         u32                     upsmr;
 469         u32                     maccfg2;
 470
 471         if (!uec) {
 472                 printf("%s: uec not initial\n", __FUNCTION__);
 473                 return -EINVAL;
 474         }
 475
 476         uec_info = uec->uec_info;
 477         uec_regs = uec->uec_regs;
 478         enet_if_mode = if_mode;
 479
 480         maccfg2 = in_be32(&uec_regs->maccfg2);
 481         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 482
 483         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 484         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 485
 486         switch (enet_if_mode) {
 487                 case ENET_100_MII:
 488                 case ENET_10_MII:
 489                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 490                         break;
 491                 case ENET_1000_GMII:
 492                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 493                         break;
 494                 case ENET_1000_TBI:
 495                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 496                         upsmr |= UPSMR_TBIM;
 497                         break;
 498                 case ENET_1000_RTBI:
 499                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 500                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 501                         break;
 502                 case ENET_1000_RGMII_RXID:
 503                 case ENET_1000_RGMII_ID:
 504                 case ENET_1000_RGMII:
 505                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 506                         upsmr |= UPSMR_RPM;
 507                         break;
 508                 case ENET_100_RGMII:
 509                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 510                         upsmr |= UPSMR_RPM;
 511                         break;
 512                 case ENET_10_RGMII:
 513                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 514                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 515                         break;
 516                 case ENET_100_RMII:
 517                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 518                         upsmr |= UPSMR_RMM;
 519                         break;
 520                 case ENET_10_RMII:
 521                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 522                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 523                         break;
 524                 default:
 525                         return -EINVAL;
 526                         break;
 527         }
 528         out_be32(&uec_regs->maccfg2, maccfg2);
 529         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 530
 531         return 0;
 532 }
 533
 534 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 535 {
 536         uint            timeout = 0x1000;
 537         u32             miimcfg = 0;
 538
 539         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 540         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 541         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 542
 543         /* Wait until the bus is free */
 544         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 545         if (timeout <= 0) {
 546                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 547                 return -ETIMEDOUT;
 548         }
 549
 550         return 0;
 551 }
 552
 553 static int init_phy(struct eth_device *dev)
 554 {
 555         uec_private_t           *uec;
 556         uec_mii_t               *umii_regs;
 557         struct uec_mii_info     *mii_info;
 558         struct phy_info         *curphy;
 559         int                     err;
 560
 561         uec = (uec_private_t *)dev->priv;
 562         umii_regs = uec->uec_mii_regs;
 563
 564         uec->oldlink = 0;
 565         uec->oldspeed = 0;
 566         uec->oldduplex = -1;
 567
 568         mii_info = malloc(sizeof(*mii_info));
 569         if (!mii_info) {
 570                 printf("%s: Could not allocate mii_info", dev->name);
 571                 return -ENOMEM;
 572         }
 573         memset(mii_info, 0, sizeof(*mii_info));
 574
 575         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 576                 mii_info->speed = SPEED_1000;
 577         } else {
 578                 mii_info->speed = SPEED_100;
 579         }
 580
 581         mii_info->duplex = DUPLEX_FULL;
 582         mii_info->pause = 0;
 583         mii_info->link = 1;
 584
 585         mii_info->advertising = (ADVERTISED_10baseT_Half |
 586                                 ADVERTISED_10baseT_Full |
 587                                 ADVERTISED_100baseT_Half |
 588                                 ADVERTISED_100baseT_Full |
 589                                 ADVERTISED_1000baseT_Full);
 590         mii_info->autoneg = 1;
 591         mii_info->mii_id = uec->uec_info->phy_address;
 592         mii_info->dev = dev;
 593
 594         mii_info->mdio_read = &uec_read_phy_reg;
 595         mii_info->mdio_write = &uec_write_phy_reg;
 596
 597         uec->mii_info = mii_info;
 598
 599         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 600
 601         if (init_mii_management_configuration(umii_regs)) {
 602                 printf("%s: The MII Bus is stuck!", dev->name);
 603                 err = -1;
 604                 goto bus_fail;
 605         }
 606
 607         /* get info for this PHY */
 608         curphy = uec_get_phy_info(uec->mii_info);
 609         if (!curphy) {
 610                 printf("%s: No PHY found", dev->name);
 611                 err = -1;
 612                 goto no_phy;
 613         }
 614
 615         mii_info->phyinfo = curphy;
 616
 617         /* Run the commands which initialize the PHY */
 618         if (curphy->init) {
 619                 err = curphy->init(uec->mii_info);
 620                 if (err)
 621                         goto phy_init_fail;
 622         }
 623
 624         return 0;
 625
 626 phy_init_fail:
 627 no_phy:
 628 bus_fail:
 629         free(mii_info);
 630         return err;
 631 }
 632
 633 static void adjust_link(struct eth_device *dev)
 634 {
 635         uec_private_t           *uec = (uec_private_t *)dev->priv;
 636         uec_t                   *uec_regs;
 637         struct uec_mii_info     *mii_info = uec->mii_info;
 638
 639         extern void change_phy_interface_mode(struct eth_device *dev,
 640                                          enet_interface_e mode);
 641         uec_regs = uec->uec_regs;
 642
 643         if (mii_info->link) {
 644                 /* Now we make sure that we can be in full duplex mode.
 645                 * If not, we operate in half-duplex mode. */
 646                 if (mii_info->duplex != uec->oldduplex) {
 647                         if (!(mii_info->duplex)) {
 648                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 649                                 printf("%s: Half Duplex\n", dev->name);
 650                         } else {
 651                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 652                                 printf("%s: Full Duplex\n", dev->name);
 653                         }
 654                         uec->oldduplex = mii_info->duplex;
 655                 }
 656
 657                 if (mii_info->speed != uec->oldspeed) {
 658                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 659                                 switch (mii_info->speed) {
 660                                 case 1000:
 661                                         break;
 662                                 case 100:
 663                                         printf ("switching to rgmii 100\n");
 664                                         /* change phy to rgmii 100 */
 665                                         change_phy_interface_mode(dev,
 666                                                                 ENET_100_RGMII);
 667                                         /* change the MAC interface mode */
 668                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
 669                                         break;
 670                                 case 10:
 671                                         printf ("switching to rgmii 10\n");
 672                                         /* change phy to rgmii 10 */
 673                                         change_phy_interface_mode(dev,
 674                                                                 ENET_10_RGMII);
 675                                         /* change the MAC interface mode */
 676                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
 677                                         break;
 678                                 default:
 679                                         printf("%s: Ack,Speed(%d)is illegal\n",
 680                                                 dev->name, mii_info->speed);
 681                                         break;
 682                                 }
 683                         }
 684
 685                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 686                         uec->oldspeed = mii_info->speed;
 687                 }
 688
 689                 if (!uec->oldlink) {
 690                         printf("%s: Link is up\n", dev->name);
 691                         uec->oldlink = 1;
 692                 }
 693
 694         } else { /* if (mii_info->link) */
 695                 if (uec->oldlink) {
 696                         printf("%s: Link is down\n", dev->name);
 697                         uec->oldlink = 0;
 698                         uec->oldspeed = 0;
 699                         uec->oldduplex = -1;
 700                 }
 701         }
 702 }
 703
 704 static void phy_change(struct eth_device *dev)
 705 {
 706         uec_private_t   *uec = (uec_private_t *)dev->priv;
 707
 708         /* Update the link, speed, duplex */
 709         uec->mii_info->phyinfo->read_status(uec->mii_info);
 710
 711         /* Adjust the interface according to speed */
 712         adjust_link(dev);
 713 }
 714
 715 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 716         && !defined(BITBANGMII)
 717
 718 /*
 719  * Find a device index from the devlist by name
 720  *
 721  * Returns:
 722  *  The index where the device is located, -1 on error
 723  */
 724 static int uec_miiphy_find_dev_by_name(char *devname)
 725 {
 726         int i;
 727
 728         for (i = 0; i < MAXCONTROLLERS; i++) {
 729                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
 730                         break;
 731                 }
 732         }
 733
 734         /* If device cannot be found, returns -1 */
 735         if (i == MAXCONTROLLERS) {
 736                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
 737                 i = -1;
 738         }
 739
 740         return i;
 741 }
 742
 743 /*
 744  * Read a MII PHY register.
 745  *
 746  * Returns:
 747  *  0 on success
 748  */
 749 static int uec_miiphy_read(char *devname, unsigned char addr,
 750                             unsigned char reg, unsigned short *value)
 751 {
 752         int devindex = 0;
 753
 754         if (devname == NULL || value == NULL) {
 755                 debug("%s: NULL pointer given\n", __FUNCTION__);
 756         } else {
 757                 devindex = uec_miiphy_find_dev_by_name(devname);
 758                 if (devindex >= 0) {
 759                         *value = uec_read_phy_reg(devlist[devindex], addr, reg);
 760                 }
 761         }
 762         return 0;
 763 }
 764
 765 /*
 766  * Write a MII PHY register.
 767  *
 768  * Returns:
 769  *  0 on success
 770  */
 771 static int uec_miiphy_write(char *devname, unsigned char addr,
 772                              unsigned char reg, unsigned short value)
 773 {
 774         int devindex = 0;
 775
 776         if (devname == NULL) {
 777                 debug("%s: NULL pointer given\n", __FUNCTION__);
 778         } else {
 779                 devindex = uec_miiphy_find_dev_by_name(devname);
 780                 if (devindex >= 0) {
 781                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
 782                 }
 783         }
 784         return 0;
 785 }
 786 #endif
 787
 788 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 789 {
 790         uec_t           *uec_regs;
 791         u32             mac_addr1;
 792         u32             mac_addr2;
 793
 794         if (!uec) {
 795                 printf("%s: uec not initial\n", __FUNCTION__);
 796                 return -EINVAL;
 797         }
 798
 799         uec_regs = uec->uec_regs;
 800
 801         /* if a station address of 0x12345678ABCD, perform a write to
 802         MACSTNADDR1 of 0xCDAB7856,
 803         MACSTNADDR2 of 0x34120000 */
 804
 805         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 806                         (mac_addr[3] << 8)  | (mac_addr[2]);
 807         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 808
 809         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 810         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 811
 812         return 0;
 813 }
 814
 815 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 816                                          int *threads_num_ret)
 817 {
 818         int     num_threads_numerica;
 819
 820         switch (threads_num) {
 821                 case UEC_NUM_OF_THREADS_1:
 822                         num_threads_numerica = 1;
 823                         break;
 824                 case UEC_NUM_OF_THREADS_2:
 825                         num_threads_numerica = 2;
 826                         break;
 827                 case UEC_NUM_OF_THREADS_4:
 828                         num_threads_numerica = 4;
 829                         break;
 830                 case UEC_NUM_OF_THREADS_6:
 831                         num_threads_numerica = 6;
 832                         break;
 833                 case UEC_NUM_OF_THREADS_8:
 834                         num_threads_numerica = 8;
 835                         break;
 836                 default:
 837                         printf("%s: Bad number of threads value.",
 838                                  __FUNCTION__);
 839                         return -EINVAL;
 840         }
 841
 842         *threads_num_ret = num_threads_numerica;
 843
 844         return 0;
 845 }
 846
 847 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 848 {
 849         uec_info_t      *uec_info;
 850         u32             end_bd;
 851         u8              bmrx = 0;
 852         int             i;
 853
 854         uec_info = uec->uec_info;
 855
 856         /* Alloc global Tx parameter RAM page */
 857         uec->tx_glbl_pram_offset = qe_muram_alloc(
 858                                 sizeof(uec_tx_global_pram_t),
 859                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 860         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 861                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 862
 863         /* Zero the global Tx prameter RAM */
 864         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 865
 866         /* Init global Tx parameter RAM */
 867
 868         /* TEMODER, RMON statistics disable, one Tx queue */
 869         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 870
 871         /* SQPTR */
 872         uec->send_q_mem_reg_offset = qe_muram_alloc(
 873                                 sizeof(uec_send_queue_qd_t),
 874                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 875         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 876                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 877         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 878
 879         /* Setup the table with TxBDs ring */
 880         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 881                                          * SIZEOFBD;
 882         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 883                                  (u32)(uec->p_tx_bd_ring));
 884         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 885                                                  end_bd);
 886
 887         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 888         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 889
 890         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 891         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 892
 893         /* TSTATE, global snooping, big endian, the CSB bus selected */
 894         bmrx = BMR_INIT_VALUE;
 895         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 896
 897         /* IPH_Offset */
 898         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 899                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 900         }
 901
 902         /* VTAG table */
 903         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 904                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 905         }
 906
 907         /* TQPTR */
 908         uec->thread_dat_tx_offset = qe_muram_alloc(
 909                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 910                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 911
 912         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 913                                 qe_muram_addr(uec->thread_dat_tx_offset);
 914         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 915 }
 916
 917 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 918 {
 919         u8      bmrx = 0;
 920         int     i;
 921         uec_82xx_address_filtering_pram_t       *p_af_pram;
 922
 923         /* Allocate global Rx parameter RAM page */
 924         uec->rx_glbl_pram_offset = qe_muram_alloc(
 925                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 926         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 927                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 928
 929         /* Zero Global Rx parameter RAM */
 930         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 931
 932         /* Init global Rx parameter RAM */
 933         /* REMODER, Extended feature mode disable, VLAN disable,
 934          LossLess flow control disable, Receive firmware statisic disable,
 935          Extended address parsing mode disable, One Rx queues,
 936          Dynamic maximum/minimum frame length disable, IP checksum check
 937          disable, IP address alignment disable
 938         */
 939         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 940
 941         /* RQPTR */
 942         uec->thread_dat_rx_offset = qe_muram_alloc(
 943                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 944                          UEC_THREAD_DATA_ALIGNMENT);
 945         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 946                                 qe_muram_addr(uec->thread_dat_rx_offset);
 947         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 948
 949         /* Type_or_Len */
 950         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 951
 952         /* RxRMON base pointer, we don't need it */
 953         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 954
 955         /* IntCoalescingPTR, we don't need it, no interrupt */
 956         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 957
 958         /* RSTATE, global snooping, big endian, the CSB bus selected */
 959         bmrx = BMR_INIT_VALUE;
 960         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 961
 962         /* MRBLR */
 963         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 964
 965         /* RBDQPTR */
 966         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 967                                 sizeof(uec_rx_bd_queues_entry_t) + \
 968                                 sizeof(uec_rx_prefetched_bds_t),
 969                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 970         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 971                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 972
 973         /* Zero it */
 974         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 975                                         sizeof(uec_rx_prefetched_bds_t));
 976         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 977         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 978                  (u32)uec->p_rx_bd_ring);
 979
 980         /* MFLR */
 981         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 982         /* MINFLR */
 983         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 984         /* MAXD1 */
 985         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 986         /* MAXD2 */
 987         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 988         /* ECAM_PTR */
 989         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 990         /* L2QT */
 991         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 992         /* L3QT */
 993         for (i = 0; i < 8; i++) {
 994                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 995         }
 996
 997         /* VLAN_TYPE */
 998         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 999         /* TCI */
1000         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
1001
1002         /* Clear PQ2 style address filtering hash table */
1003         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
1004                         uec->p_rx_glbl_pram->addressfiltering;
1005
1006         p_af_pram->iaddr_h = 0;
1007         p_af_pram->iaddr_l = 0;
1008         p_af_pram->gaddr_h = 0;
1009         p_af_pram->gaddr_l = 0;
1010 }
1011
1012 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
1013                                          int thread_tx, int thread_rx)
1014 {
1015         uec_init_cmd_pram_t             *p_init_enet_param;
1016         u32                             init_enet_param_offset;
1017         uec_info_t                      *uec_info;
1018         int                             i;
1019         int                             snum;
1020         u32                             init_enet_offset;
1021         u32                             entry_val;
1022         u32                             command;
1023         u32                             cecr_subblock;
1024
1025         uec_info = uec->uec_info;
1026
1027         /* Allocate init enet command parameter */
1028         uec->init_enet_param_offset = qe_muram_alloc(
1029                                         sizeof(uec_init_cmd_pram_t), 4);
1030         init_enet_param_offset = uec->init_enet_param_offset;
1031         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
1032                                 qe_muram_addr(uec->init_enet_param_offset);
1033
1034         /* Zero init enet command struct */
1035         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
1036
1037         /* Init the command struct */
1038         p_init_enet_param = uec->p_init_enet_param;
1039         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
1040         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
1041         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
1042         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
1043         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
1044         p_init_enet_param->largestexternallookupkeysize = 0;
1045
1046         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
1047                                          << ENET_INIT_PARAM_RGF_SHIFT;
1048         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
1049                                          << ENET_INIT_PARAM_TGF_SHIFT;
1050
1051         /* Init Rx global parameter pointer */
1052         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
1053                                                  (u32)uec_info->risc_rx;
1054
1055         /* Init Rx threads */
1056         for (i = 0; i < (thread_rx + 1); i++) {
1057                 if ((snum = qe_get_snum()) < 0) {
1058                         printf("%s can not get snum\n", __FUNCTION__);
1059                         return -ENOMEM;
1060                 }
1061
1062                 if (i==0) {
1063                         init_enet_offset = 0;
1064                 } else {
1065                         init_enet_offset = qe_muram_alloc(
1066                                         sizeof(uec_thread_rx_pram_t),
1067                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
1068                 }
1069
1070                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1071                                  init_enet_offset | (u32)uec_info->risc_rx;
1072                 p_init_enet_param->rxthread[i] = entry_val;
1073         }
1074
1075         /* Init Tx global parameter pointer */
1076         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
1077                                          (u32)uec_info->risc_tx;
1078
1079         /* Init Tx threads */
1080         for (i = 0; i < thread_tx; i++) {
1081                 if ((snum = qe_get_snum()) < 0) {
1082                         printf("%s can not get snum\n", __FUNCTION__);
1083                         return -ENOMEM;
1084                 }
1085
1086                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
1087                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
1088
1089                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1090                                  init_enet_offset | (u32)uec_info->risc_tx;
1091                 p_init_enet_param->txthread[i] = entry_val;
1092         }
1093
1094         __asm__ __volatile__("sync");
1095
1096         /* Issue QE command */
1097         command = QE_INIT_TX_RX;
1098         cecr_subblock = ucc_fast_get_qe_cr_subblock(
1099                                 uec->uec_info->uf_info.ucc_num);
1100         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1101                                                  init_enet_param_offset);
1102
1103         return 0;
1104 }
1105
1106 static int uec_startup(uec_private_t *uec)
1107 {
1108         uec_info_t                      *uec_info;
1109         ucc_fast_info_t                 *uf_info;
1110         ucc_fast_private_t              *uccf;
1111         ucc_fast_t                      *uf_regs;
1112         uec_t                           *uec_regs;
1113         int                             num_threads_tx;
1114         int                             num_threads_rx;
1115         u32                             utbipar;
1116         enet_interface_e                enet_interface;
1117         u32                             length;
1118         u32                             align;
1119         qe_bd_t                         *bd;
1120         u8                              *buf;
1121         int                             i;
1122
1123         if (!uec || !uec->uec_info) {
1124                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1125                 return -EINVAL;
1126         }
1127
1128         uec_info = uec->uec_info;
1129         uf_info = &(uec_info->uf_info);
1130
1131         /* Check if Rx BD ring len is illegal */
1132         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1133                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1134                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1135                          __FUNCTION__);
1136                 return -EINVAL;
1137         }
1138
1139         /* Check if Tx BD ring len is illegal */
1140         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1141                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1142                          __FUNCTION__);
1143                 return -EINVAL;
1144         }
1145
1146         /* Check if MRBLR is illegal */
1147         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1148                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1149                          __FUNCTION__);
1150                 return -EINVAL;
1151         }
1152
1153         /* Both Rx and Tx are stopped */
1154         uec->grace_stopped_rx = 1;
1155         uec->grace_stopped_tx = 1;
1156
1157         /* Init UCC fast */
1158         if (ucc_fast_init(uf_info, &uccf)) {
1159                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1160                 return -ENOMEM;
1161         }
1162
1163         /* Save uccf */
1164         uec->uccf = uccf;
1165
1166         /* Convert the Tx threads number */
1167         if (uec_convert_threads_num(uec_info->num_threads_tx,
1168                                          &num_threads_tx)) {
1169                 return -EINVAL;
1170         }
1171
1172         /* Convert the Rx threads number */
1173         if (uec_convert_threads_num(uec_info->num_threads_rx,
1174                                          &num_threads_rx)) {
1175                 return -EINVAL;
1176         }
1177
1178         uf_regs = uccf->uf_regs;
1179
1180         /* UEC register is following UCC fast registers */
1181         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1182
1183         /* Save the UEC register pointer to UEC private struct */
1184         uec->uec_regs = uec_regs;
1185
1186         /* Init UPSMR, enable hardware statistics (UCC) */
1187         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1188
1189         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1190         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1191
1192         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1193         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1194
1195         /* Setup MAC interface mode */
1196         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1197
1198         /* Setup MII management base */
1199 #ifndef CONFIG_eTSEC_MDIO_BUS
1200         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1201 #else
1202         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1203 #endif
1204
1205         /* Setup MII master clock source */
1206         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1207
1208         /* Setup UTBIPAR */
1209         utbipar = in_be32(&uec_regs->utbipar);
1210         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1211         enet_interface = uec->uec_info->enet_interface;
1212         if (enet_interface == ENET_1000_TBI ||
1213                  enet_interface == ENET_1000_RTBI) {
1214                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1215                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1216         } else {
1217                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1218                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1219         }
1220
1221         out_be32(&uec_regs->utbipar, utbipar);
1222
1223         /* Allocate Tx BDs */
1224         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1225                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1226                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1227         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1228                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1229                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1230         }
1231
1232         align = UEC_TX_BD_RING_ALIGNMENT;
1233         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1234         if (uec->tx_bd_ring_offset != 0) {
1235                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1236                                                  & ~(align - 1));
1237         }
1238
1239         /* Zero all of Tx BDs */
1240         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1241
1242         /* Allocate Rx BDs */
1243         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1244         align = UEC_RX_BD_RING_ALIGNMENT;
1245         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1246         if (uec->rx_bd_ring_offset != 0) {
1247                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1248                                                          & ~(align - 1));
1249         }
1250
1251         /* Zero all of Rx BDs */
1252         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1253
1254         /* Allocate Rx buffer */
1255         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1256         align = UEC_RX_DATA_BUF_ALIGNMENT;
1257         uec->rx_buf_offset = (u32)malloc(length + align);
1258         if (uec->rx_buf_offset != 0) {
1259                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1260                                                  & ~(align - 1));
1261         }
1262
1263         /* Zero all of the Rx buffer */
1264         memset((void *)(uec->rx_buf_offset), 0, length + align);
1265
1266         /* Init TxBD ring */
1267         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1268         uec->txBd = bd;
1269
1270         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1271                 BD_DATA_CLEAR(bd);
1272                 BD_STATUS_SET(bd, 0);
1273                 BD_LENGTH_SET(bd, 0);
1274                 bd ++;
1275         }
1276         BD_STATUS_SET((--bd), TxBD_WRAP);
1277
1278         /* Init RxBD ring */
1279         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1280         uec->rxBd = bd;
1281         buf = uec->p_rx_buf;
1282         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1283                 BD_DATA_SET(bd, buf);
1284                 BD_LENGTH_SET(bd, 0);
1285                 BD_STATUS_SET(bd, RxBD_EMPTY);
1286                 buf += MAX_RXBUF_LEN;
1287                 bd ++;
1288         }
1289         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1290
1291         /* Init global Tx parameter RAM */
1292         uec_init_tx_parameter(uec, num_threads_tx);
1293
1294         /* Init global Rx parameter RAM */
1295         uec_init_rx_parameter(uec, num_threads_rx);
1296
1297         /* Init ethernet Tx and Rx parameter command */
1298         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1299                                          num_threads_rx)) {
1300                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1301                 return -ENOMEM;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int uec_init(struct eth_device* dev, bd_t *bd)
1308 {
1309         uec_private_t           *uec;
1310         int                     err, i;
1311         struct phy_info         *curphy;
1312
1313         uec = (uec_private_t *)dev->priv;
1314
1315         if (uec->the_first_run == 0) {
1316                 err = init_phy(dev);
1317                 if (err) {
1318                         printf("%s: Cannot initialize PHY, aborting.\n",
1319                                dev->name);
1320                         return err;
1321                 }
1322
1323                 curphy = uec->mii_info->phyinfo;
1324
1325                 if (curphy->config_aneg) {
1326                         err = curphy->config_aneg(uec->mii_info);
1327                         if (err) {
1328                                 printf("%s: Can't negotiate PHY\n", dev->name);
1329                                 return err;
1330                         }
1331                 }
1332
1333                 /* Give PHYs up to 5 sec to report a link */
1334                 i = 50;
1335                 do {
1336                         err = curphy->read_status(uec->mii_info);
1337                         udelay(100000);
1338                 } while (((i-- > 0) && !uec->mii_info->link) || err);
1339
1340                 if (err || i <= 0)
1341                         printf("warning: %s: timeout on PHY link\n", dev->name);
1342
1343                 uec->the_first_run = 1;
1344         }
1345
1346         /* Set up the MAC address */
1347         if (dev->enetaddr[0] & 0x01) {
1348                 printf("%s: MacAddress is multcast address\n",
1349                          __FUNCTION__);
1350                 return -1;
1351         }
1352         uec_set_mac_address(uec, dev->enetaddr);
1353
1354
1355         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1356         if (err) {
1357                 printf("%s: cannot enable UEC device\n", dev->name);
1358                 return -1;
1359         }
1360
1361         phy_change(dev);
1362
1363         return (uec->mii_info->link ? 0 : -1);
1364 }
1365
1366 static void uec_halt(struct eth_device* dev)
1367 {
1368         uec_private_t   *uec = (uec_private_t *)dev->priv;
1369         uec_stop(uec, COMM_DIR_RX_AND_TX);
1370 }
1371
1372 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1373 {
1374         uec_private_t           *uec;
1375         ucc_fast_private_t      *uccf;
1376         volatile qe_bd_t        *bd;
1377         u16                     status;
1378         int                     i;
1379         int                     result = 0;
1380
1381         uec = (uec_private_t *)dev->priv;
1382         uccf = uec->uccf;
1383         bd = uec->txBd;
1384
1385         /* Find an empty TxBD */
1386         for (i = 0; bd->status & TxBD_READY; i++) {
1387                 if (i > 0x100000) {
1388                         printf("%s: tx buffer not ready\n", dev->name);
1389                         return result;
1390                 }
1391         }
1392
1393         /* Init TxBD */
1394         BD_DATA_SET(bd, buf);
1395         BD_LENGTH_SET(bd, len);
1396         status = bd->status;
1397         status &= BD_WRAP;
1398         status |= (TxBD_READY | TxBD_LAST);
1399         BD_STATUS_SET(bd, status);
1400
1401         /* Tell UCC to transmit the buffer */
1402         ucc_fast_transmit_on_demand(uccf);
1403
1404         /* Wait for buffer to be transmitted */
1405         for (i = 0; bd->status & TxBD_READY; i++) {
1406                 if (i > 0x100000) {
1407                         printf("%s: tx error\n", dev->name);
1408                         return result;
1409                 }
1410         }
1411
1412         /* Ok, the buffer be transimitted */
1413         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1414         uec->txBd = bd;
1415         result = 1;
1416
1417         return result;
1418 }
1419
1420 static int uec_recv(struct eth_device* dev)
1421 {
1422         uec_private_t           *uec = dev->priv;
1423         volatile qe_bd_t        *bd;
1424         u16                     status;
1425         u16                     len;
1426         u8                      *data;
1427
1428         bd = uec->rxBd;
1429         status = bd->status;
1430
1431         while (!(status & RxBD_EMPTY)) {
1432                 if (!(status & RxBD_ERROR)) {
1433                         data = BD_DATA(bd);
1434                         len = BD_LENGTH(bd);
1435                         NetReceive(data, len);
1436                 } else {
1437                         printf("%s: Rx error\n", dev->name);
1438                 }
1439                 status &= BD_CLEAN;
1440                 BD_LENGTH_SET(bd, 0);
1441                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1442                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1443                 status = bd->status;
1444         }
1445         uec->rxBd = bd;
1446
1447         return 1;
1448 }
1449
1450 int uec_initialize(int index)
1451 {
1452         struct eth_device       *dev;
1453         int                     i;
1454         uec_private_t           *uec;
1455         uec_info_t              *uec_info;
1456         int                     err;
1457
1458         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1459         if (!dev)
1460                 return 0;
1461         memset(dev, 0, sizeof(struct eth_device));
1462
1463         /* Allocate the UEC private struct */
1464         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1465         if (!uec) {
1466                 return -ENOMEM;
1467         }
1468         memset(uec, 0, sizeof(uec_private_t));
1469
1470         /* Init UEC private struct, they come from board.h */
1471         uec_info = NULL;
1472         if (index == 0) {
1473 #ifdef CONFIG_UEC_ETH1
1474                 uec_info = &eth1_uec_info;
1475 #endif
1476         } else if (index == 1) {
1477 #ifdef CONFIG_UEC_ETH2
1478                 uec_info = &eth2_uec_info;
1479 #endif
1480         } else if (index == 2) {
1481 #ifdef CONFIG_UEC_ETH3
1482                 uec_info = &eth3_uec_info;
1483 #endif
1484         } else if (index == 3) {
1485 #ifdef CONFIG_UEC_ETH4
1486                 uec_info = &eth4_uec_info;
1487 #endif
1488         } else if (index == 4) {
1489 #ifdef CONFIG_UEC_ETH5
1490                 uec_info = &eth5_uec_info;
1491 #endif
1492         } else if (index == 5) {
1493 #ifdef CONFIG_UEC_ETH6
1494                 uec_info = &eth6_uec_info;
1495 #endif
1496         } else {
1497                 printf("%s: index is illegal.\n", __FUNCTION__);
1498                 return -EINVAL;
1499         }
1500
1501         devlist[index] = dev;
1502
1503         uec->uec_info = uec_info;
1504
1505         sprintf(dev->name, "FSL UEC%d", index);
1506         dev->iobase = 0;
1507         dev->priv = (void *)uec;
1508         dev->init = uec_init;
1509         dev->halt = uec_halt;
1510         dev->send = uec_send;
1511         dev->recv = uec_recv;
1512
1513         /* Clear the ethnet address */
1514         for (i = 0; i < 6; i++)
1515                 dev->enetaddr[i] = 0;
1516
1517         eth_register(dev);
1518
1519         err = uec_startup(uec);
1520         if (err) {
1521                 printf("%s: Cannot configure net device, aborting.",dev->name);
1522                 return err;
1523         }
1524
1525 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1526         && !defined(BITBANGMII)
1527         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1528 #endif
1529
1530         return 1;
1531 }