drivers/qe: Rename the camel-case identifiers in uec
[platform/kernel/u-boot.git] / drivers / qe / uec.c
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32 #include "miiphy.h"
33
34 #ifdef CONFIG_UEC_ETH1
35 static uec_info_t eth1_uec_info = {
36         .uf_info                = {
37                 .ucc_num        = CONFIG_SYS_UEC1_UCC_NUM,
38                 .rx_clock       = CONFIG_SYS_UEC1_RX_CLK,
39                 .tx_clock       = CONFIG_SYS_UEC1_TX_CLK,
40                 .eth_type       = CONFIG_SYS_UEC1_ETH_TYPE,
41         },
42 #if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
43         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
44         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
45 #else
46         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
47         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
48 #endif
49         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
50         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
51         .tx_bd_ring_len         = 16,
52         .rx_bd_ring_len         = 16,
53         .phy_address            = CONFIG_SYS_UEC1_PHY_ADDR,
54         .enet_interface         = CONFIG_SYS_UEC1_INTERFACE_MODE,
55 };
56 #endif
57 #ifdef CONFIG_UEC_ETH2
58 static uec_info_t eth2_uec_info = {
59         .uf_info                = {
60                 .ucc_num        = CONFIG_SYS_UEC2_UCC_NUM,
61                 .rx_clock       = CONFIG_SYS_UEC2_RX_CLK,
62                 .tx_clock       = CONFIG_SYS_UEC2_TX_CLK,
63                 .eth_type       = CONFIG_SYS_UEC2_ETH_TYPE,
64         },
65 #if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
66         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
67         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
68 #else
69         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
70         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
71 #endif
72         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
73         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
74         .tx_bd_ring_len         = 16,
75         .rx_bd_ring_len         = 16,
76         .phy_address            = CONFIG_SYS_UEC2_PHY_ADDR,
77         .enet_interface         = CONFIG_SYS_UEC2_INTERFACE_MODE,
78 };
79 #endif
80 #ifdef CONFIG_UEC_ETH3
81 static uec_info_t eth3_uec_info = {
82         .uf_info                = {
83                 .ucc_num        = CONFIG_SYS_UEC3_UCC_NUM,
84                 .rx_clock       = CONFIG_SYS_UEC3_RX_CLK,
85                 .tx_clock       = CONFIG_SYS_UEC3_TX_CLK,
86                 .eth_type       = CONFIG_SYS_UEC3_ETH_TYPE,
87         },
88 #if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
89         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
90         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
91 #else
92         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
93         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
94 #endif
95         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
96         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
97         .tx_bd_ring_len         = 16,
98         .rx_bd_ring_len         = 16,
99         .phy_address            = CONFIG_SYS_UEC3_PHY_ADDR,
100         .enet_interface         = CONFIG_SYS_UEC3_INTERFACE_MODE,
101 };
102 #endif
103 #ifdef CONFIG_UEC_ETH4
104 static uec_info_t eth4_uec_info = {
105         .uf_info                = {
106                 .ucc_num        = CONFIG_SYS_UEC4_UCC_NUM,
107                 .rx_clock       = CONFIG_SYS_UEC4_RX_CLK,
108                 .tx_clock       = CONFIG_SYS_UEC4_TX_CLK,
109                 .eth_type       = CONFIG_SYS_UEC4_ETH_TYPE,
110         },
111 #if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
112         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
113         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
114 #else
115         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
116         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
117 #endif
118         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
119         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
120         .tx_bd_ring_len         = 16,
121         .rx_bd_ring_len         = 16,
122         .phy_address            = CONFIG_SYS_UEC4_PHY_ADDR,
123         .enet_interface         = CONFIG_SYS_UEC4_INTERFACE_MODE,
124 };
125 #endif
126 #ifdef CONFIG_UEC_ETH5
127 static uec_info_t eth5_uec_info = {
128         .uf_info                = {
129                 .ucc_num        = CONFIG_SYS_UEC5_UCC_NUM,
130                 .rx_clock       = CONFIG_SYS_UEC5_RX_CLK,
131                 .tx_clock       = CONFIG_SYS_UEC5_TX_CLK,
132                 .eth_type       = CONFIG_SYS_UEC5_ETH_TYPE,
133         },
134 #if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
135         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
136         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
137 #else
138         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
139         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
140 #endif
141         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
142         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
143         .tx_bd_ring_len         = 16,
144         .rx_bd_ring_len         = 16,
145         .phy_address            = CONFIG_SYS_UEC5_PHY_ADDR,
146         .enet_interface         = CONFIG_SYS_UEC5_INTERFACE_MODE,
147 };
148 #endif
149 #ifdef CONFIG_UEC_ETH6
150 static uec_info_t eth6_uec_info = {
151         .uf_info                = {
152                 .ucc_num        = CONFIG_SYS_UEC6_UCC_NUM,
153                 .rx_clock       = CONFIG_SYS_UEC6_RX_CLK,
154                 .tx_clock       = CONFIG_SYS_UEC6_TX_CLK,
155                 .eth_type       = CONFIG_SYS_UEC6_ETH_TYPE,
156         },
157 #if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
158         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
159         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
160 #else
161         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
162         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
163 #endif
164         .risc_tx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
165         .risc_rx                        = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
166         .tx_bd_ring_len         = 16,
167         .rx_bd_ring_len         = 16,
168         .phy_address            = CONFIG_SYS_UEC6_PHY_ADDR,
169         .enet_interface         = CONFIG_SYS_UEC6_INTERFACE_MODE,
170 };
171 #endif
172
173 #define MAXCONTROLLERS  (6)
174
175 static struct eth_device *devlist[MAXCONTROLLERS];
176
177 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
178 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
179
180 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
181 {
182         uec_t           *uec_regs;
183         u32             maccfg1;
184
185         if (!uec) {
186                 printf("%s: uec not initial\n", __FUNCTION__);
187                 return -EINVAL;
188         }
189         uec_regs = uec->uec_regs;
190
191         maccfg1 = in_be32(&uec_regs->maccfg1);
192
193         if (mode & COMM_DIR_TX) {
194                 maccfg1 |= MACCFG1_ENABLE_TX;
195                 out_be32(&uec_regs->maccfg1, maccfg1);
196                 uec->mac_tx_enabled = 1;
197         }
198
199         if (mode & COMM_DIR_RX) {
200                 maccfg1 |= MACCFG1_ENABLE_RX;
201                 out_be32(&uec_regs->maccfg1, maccfg1);
202                 uec->mac_rx_enabled = 1;
203         }
204
205         return 0;
206 }
207
208 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
209 {
210         uec_t           *uec_regs;
211         u32             maccfg1;
212
213         if (!uec) {
214                 printf("%s: uec not initial\n", __FUNCTION__);
215                 return -EINVAL;
216         }
217         uec_regs = uec->uec_regs;
218
219         maccfg1 = in_be32(&uec_regs->maccfg1);
220
221         if (mode & COMM_DIR_TX) {
222                 maccfg1 &= ~MACCFG1_ENABLE_TX;
223                 out_be32(&uec_regs->maccfg1, maccfg1);
224                 uec->mac_tx_enabled = 0;
225         }
226
227         if (mode & COMM_DIR_RX) {
228                 maccfg1 &= ~MACCFG1_ENABLE_RX;
229                 out_be32(&uec_regs->maccfg1, maccfg1);
230                 uec->mac_rx_enabled = 0;
231         }
232
233         return 0;
234 }
235
236 static int uec_graceful_stop_tx(uec_private_t *uec)
237 {
238         ucc_fast_t              *uf_regs;
239         u32                     cecr_subblock;
240         u32                     ucce;
241
242         if (!uec || !uec->uccf) {
243                 printf("%s: No handle passed.\n", __FUNCTION__);
244                 return -EINVAL;
245         }
246
247         uf_regs = uec->uccf->uf_regs;
248
249         /* Clear the grace stop event */
250         out_be32(&uf_regs->ucce, UCCE_GRA);
251
252         /* Issue host command */
253         cecr_subblock =
254                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
255         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
256                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
257
258         /* Wait for command to complete */
259         do {
260                 ucce = in_be32(&uf_regs->ucce);
261         } while (! (ucce & UCCE_GRA));
262
263         uec->grace_stopped_tx = 1;
264
265         return 0;
266 }
267
268 static int uec_graceful_stop_rx(uec_private_t *uec)
269 {
270         u32             cecr_subblock;
271         u8              ack;
272
273         if (!uec) {
274                 printf("%s: No handle passed.\n", __FUNCTION__);
275                 return -EINVAL;
276         }
277
278         if (!uec->p_rx_glbl_pram) {
279                 printf("%s: No init rx global parameter\n", __FUNCTION__);
280                 return -EINVAL;
281         }
282
283         /* Clear acknowledge bit */
284         ack = uec->p_rx_glbl_pram->rxgstpack;
285         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
286         uec->p_rx_glbl_pram->rxgstpack = ack;
287
288         /* Keep issuing cmd and checking ack bit until it is asserted */
289         do {
290                 /* Issue host command */
291                 cecr_subblock =
292                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
293                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
294                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
295                 ack = uec->p_rx_glbl_pram->rxgstpack;
296         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
297
298         uec->grace_stopped_rx = 1;
299
300         return 0;
301 }
302
303 static int uec_restart_tx(uec_private_t *uec)
304 {
305         u32             cecr_subblock;
306
307         if (!uec || !uec->uec_info) {
308                 printf("%s: No handle passed.\n", __FUNCTION__);
309                 return -EINVAL;
310         }
311
312         cecr_subblock =
313          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
314         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
315                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
316
317         uec->grace_stopped_tx = 0;
318
319         return 0;
320 }
321
322 static int uec_restart_rx(uec_private_t *uec)
323 {
324         u32             cecr_subblock;
325
326         if (!uec || !uec->uec_info) {
327                 printf("%s: No handle passed.\n", __FUNCTION__);
328                 return -EINVAL;
329         }
330
331         cecr_subblock =
332          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
333         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
334                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
335
336         uec->grace_stopped_rx = 0;
337
338         return 0;
339 }
340
341 static int uec_open(uec_private_t *uec, comm_dir_e mode)
342 {
343         ucc_fast_private_t      *uccf;
344
345         if (!uec || !uec->uccf) {
346                 printf("%s: No handle passed.\n", __FUNCTION__);
347                 return -EINVAL;
348         }
349         uccf = uec->uccf;
350
351         /* check if the UCC number is in range. */
352         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
353                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
354                 return -EINVAL;
355         }
356
357         /* Enable MAC */
358         uec_mac_enable(uec, mode);
359
360         /* Enable UCC fast */
361         ucc_fast_enable(uccf, mode);
362
363         /* RISC microcode start */
364         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
365                 uec_restart_tx(uec);
366         }
367         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
368                 uec_restart_rx(uec);
369         }
370
371         return 0;
372 }
373
374 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
375 {
376         ucc_fast_private_t      *uccf;
377
378         if (!uec || !uec->uccf) {
379                 printf("%s: No handle passed.\n", __FUNCTION__);
380                 return -EINVAL;
381         }
382         uccf = uec->uccf;
383
384         /* check if the UCC number is in range. */
385         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
386                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
387                 return -EINVAL;
388         }
389         /* Stop any transmissions */
390         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
391                 uec_graceful_stop_tx(uec);
392         }
393         /* Stop any receptions */
394         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
395                 uec_graceful_stop_rx(uec);
396         }
397
398         /* Disable the UCC fast */
399         ucc_fast_disable(uec->uccf, mode);
400
401         /* Disable the MAC */
402         uec_mac_disable(uec, mode);
403
404         return 0;
405 }
406
407 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
408 {
409         uec_t           *uec_regs;
410         u32             maccfg2;
411
412         if (!uec) {
413                 printf("%s: uec not initial\n", __FUNCTION__);
414                 return -EINVAL;
415         }
416         uec_regs = uec->uec_regs;
417
418         if (duplex == DUPLEX_HALF) {
419                 maccfg2 = in_be32(&uec_regs->maccfg2);
420                 maccfg2 &= ~MACCFG2_FDX;
421                 out_be32(&uec_regs->maccfg2, maccfg2);
422         }
423
424         if (duplex == DUPLEX_FULL) {
425                 maccfg2 = in_be32(&uec_regs->maccfg2);
426                 maccfg2 |= MACCFG2_FDX;
427                 out_be32(&uec_regs->maccfg2, maccfg2);
428         }
429
430         return 0;
431 }
432
433 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
434 {
435         enet_interface_e        enet_if_mode;
436         uec_info_t              *uec_info;
437         uec_t                   *uec_regs;
438         u32                     upsmr;
439         u32                     maccfg2;
440
441         if (!uec) {
442                 printf("%s: uec not initial\n", __FUNCTION__);
443                 return -EINVAL;
444         }
445
446         uec_info = uec->uec_info;
447         uec_regs = uec->uec_regs;
448         enet_if_mode = if_mode;
449
450         maccfg2 = in_be32(&uec_regs->maccfg2);
451         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
452
453         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
454         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
455
456         switch (enet_if_mode) {
457                 case ENET_100_MII:
458                 case ENET_10_MII:
459                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
460                         break;
461                 case ENET_1000_GMII:
462                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
463                         break;
464                 case ENET_1000_TBI:
465                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
466                         upsmr |= UPSMR_TBIM;
467                         break;
468                 case ENET_1000_RTBI:
469                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
470                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
471                         break;
472                 case ENET_1000_RGMII_RXID:
473                 case ENET_1000_RGMII_ID:
474                 case ENET_1000_RGMII:
475                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
476                         upsmr |= UPSMR_RPM;
477                         break;
478                 case ENET_100_RGMII:
479                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
480                         upsmr |= UPSMR_RPM;
481                         break;
482                 case ENET_10_RGMII:
483                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
484                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
485                         break;
486                 case ENET_100_RMII:
487                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
488                         upsmr |= UPSMR_RMM;
489                         break;
490                 case ENET_10_RMII:
491                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
492                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
493                         break;
494                 default:
495                         return -EINVAL;
496                         break;
497         }
498         out_be32(&uec_regs->maccfg2, maccfg2);
499         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
500
501         return 0;
502 }
503
504 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
505 {
506         uint            timeout = 0x1000;
507         u32             miimcfg = 0;
508
509         miimcfg = in_be32(&uec_mii_regs->miimcfg);
510         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
511         out_be32(&uec_mii_regs->miimcfg, miimcfg);
512
513         /* Wait until the bus is free */
514         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
515         if (timeout <= 0) {
516                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
517                 return -ETIMEDOUT;
518         }
519
520         return 0;
521 }
522
523 static int init_phy(struct eth_device *dev)
524 {
525         uec_private_t           *uec;
526         uec_mii_t               *umii_regs;
527         struct uec_mii_info     *mii_info;
528         struct phy_info         *curphy;
529         int                     err;
530
531         uec = (uec_private_t *)dev->priv;
532         umii_regs = uec->uec_mii_regs;
533
534         uec->oldlink = 0;
535         uec->oldspeed = 0;
536         uec->oldduplex = -1;
537
538         mii_info = malloc(sizeof(*mii_info));
539         if (!mii_info) {
540                 printf("%s: Could not allocate mii_info", dev->name);
541                 return -ENOMEM;
542         }
543         memset(mii_info, 0, sizeof(*mii_info));
544
545         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
546                 mii_info->speed = SPEED_1000;
547         } else {
548                 mii_info->speed = SPEED_100;
549         }
550
551         mii_info->duplex = DUPLEX_FULL;
552         mii_info->pause = 0;
553         mii_info->link = 1;
554
555         mii_info->advertising = (ADVERTISED_10baseT_Half |
556                                 ADVERTISED_10baseT_Full |
557                                 ADVERTISED_100baseT_Half |
558                                 ADVERTISED_100baseT_Full |
559                                 ADVERTISED_1000baseT_Full);
560         mii_info->autoneg = 1;
561         mii_info->mii_id = uec->uec_info->phy_address;
562         mii_info->dev = dev;
563
564         mii_info->mdio_read = &uec_read_phy_reg;
565         mii_info->mdio_write = &uec_write_phy_reg;
566
567         uec->mii_info = mii_info;
568
569         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
570
571         if (init_mii_management_configuration(umii_regs)) {
572                 printf("%s: The MII Bus is stuck!", dev->name);
573                 err = -1;
574                 goto bus_fail;
575         }
576
577         /* get info for this PHY */
578         curphy = uec_get_phy_info(uec->mii_info);
579         if (!curphy) {
580                 printf("%s: No PHY found", dev->name);
581                 err = -1;
582                 goto no_phy;
583         }
584
585         mii_info->phyinfo = curphy;
586
587         /* Run the commands which initialize the PHY */
588         if (curphy->init) {
589                 err = curphy->init(uec->mii_info);
590                 if (err)
591                         goto phy_init_fail;
592         }
593
594         return 0;
595
596 phy_init_fail:
597 no_phy:
598 bus_fail:
599         free(mii_info);
600         return err;
601 }
602
603 static void adjust_link(struct eth_device *dev)
604 {
605         uec_private_t           *uec = (uec_private_t *)dev->priv;
606         uec_t                   *uec_regs;
607         struct uec_mii_info     *mii_info = uec->mii_info;
608
609         extern void change_phy_interface_mode(struct eth_device *dev,
610                                          enet_interface_e mode);
611         uec_regs = uec->uec_regs;
612
613         if (mii_info->link) {
614                 /* Now we make sure that we can be in full duplex mode.
615                 * If not, we operate in half-duplex mode. */
616                 if (mii_info->duplex != uec->oldduplex) {
617                         if (!(mii_info->duplex)) {
618                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
619                                 printf("%s: Half Duplex\n", dev->name);
620                         } else {
621                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
622                                 printf("%s: Full Duplex\n", dev->name);
623                         }
624                         uec->oldduplex = mii_info->duplex;
625                 }
626
627                 if (mii_info->speed != uec->oldspeed) {
628                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
629                                 switch (mii_info->speed) {
630                                 case 1000:
631                                         break;
632                                 case 100:
633                                         printf ("switching to rgmii 100\n");
634                                         /* change phy to rgmii 100 */
635                                         change_phy_interface_mode(dev,
636                                                                 ENET_100_RGMII);
637                                         /* change the MAC interface mode */
638                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
639                                         break;
640                                 case 10:
641                                         printf ("switching to rgmii 10\n");
642                                         /* change phy to rgmii 10 */
643                                         change_phy_interface_mode(dev,
644                                                                 ENET_10_RGMII);
645                                         /* change the MAC interface mode */
646                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
647                                         break;
648                                 default:
649                                         printf("%s: Ack,Speed(%d)is illegal\n",
650                                                 dev->name, mii_info->speed);
651                                         break;
652                                 }
653                         }
654
655                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
656                         uec->oldspeed = mii_info->speed;
657                 }
658
659                 if (!uec->oldlink) {
660                         printf("%s: Link is up\n", dev->name);
661                         uec->oldlink = 1;
662                 }
663
664         } else { /* if (mii_info->link) */
665                 if (uec->oldlink) {
666                         printf("%s: Link is down\n", dev->name);
667                         uec->oldlink = 0;
668                         uec->oldspeed = 0;
669                         uec->oldduplex = -1;
670                 }
671         }
672 }
673
674 static void phy_change(struct eth_device *dev)
675 {
676         uec_private_t   *uec = (uec_private_t *)dev->priv;
677
678         /* Update the link, speed, duplex */
679         uec->mii_info->phyinfo->read_status(uec->mii_info);
680
681         /* Adjust the interface according to speed */
682         adjust_link(dev);
683 }
684
685 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
686         && !defined(BITBANGMII)
687
688 /*
689  * Find a device index from the devlist by name
690  *
691  * Returns:
692  *  The index where the device is located, -1 on error
693  */
694 static int uec_miiphy_find_dev_by_name(char *devname)
695 {
696         int i;
697
698         for (i = 0; i < MAXCONTROLLERS; i++) {
699                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
700                         break;
701                 }
702         }
703
704         /* If device cannot be found, returns -1 */
705         if (i == MAXCONTROLLERS) {
706                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
707                 i = -1;
708         }
709
710         return i;
711 }
712
713 /*
714  * Read a MII PHY register.
715  *
716  * Returns:
717  *  0 on success
718  */
719 static int uec_miiphy_read(char *devname, unsigned char addr,
720                             unsigned char reg, unsigned short *value)
721 {
722         int devindex = 0;
723
724         if (devname == NULL || value == NULL) {
725                 debug("%s: NULL pointer given\n", __FUNCTION__);
726         } else {
727                 devindex = uec_miiphy_find_dev_by_name(devname);
728                 if (devindex >= 0) {
729                         *value = uec_read_phy_reg(devlist[devindex], addr, reg);
730                 }
731         }
732         return 0;
733 }
734
735 /*
736  * Write a MII PHY register.
737  *
738  * Returns:
739  *  0 on success
740  */
741 static int uec_miiphy_write(char *devname, unsigned char addr,
742                              unsigned char reg, unsigned short value)
743 {
744         int devindex = 0;
745
746         if (devname == NULL) {
747                 debug("%s: NULL pointer given\n", __FUNCTION__);
748         } else {
749                 devindex = uec_miiphy_find_dev_by_name(devname);
750                 if (devindex >= 0) {
751                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
752                 }
753         }
754         return 0;
755 }
756 #endif
757
758 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
759 {
760         uec_t           *uec_regs;
761         u32             mac_addr1;
762         u32             mac_addr2;
763
764         if (!uec) {
765                 printf("%s: uec not initial\n", __FUNCTION__);
766                 return -EINVAL;
767         }
768
769         uec_regs = uec->uec_regs;
770
771         /* if a station address of 0x12345678ABCD, perform a write to
772         MACSTNADDR1 of 0xCDAB7856,
773         MACSTNADDR2 of 0x34120000 */
774
775         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
776                         (mac_addr[3] << 8)  | (mac_addr[2]);
777         out_be32(&uec_regs->macstnaddr1, mac_addr1);
778
779         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
780         out_be32(&uec_regs->macstnaddr2, mac_addr2);
781
782         return 0;
783 }
784
785 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
786                                          int *threads_num_ret)
787 {
788         int     num_threads_numerica;
789
790         switch (threads_num) {
791                 case UEC_NUM_OF_THREADS_1:
792                         num_threads_numerica = 1;
793                         break;
794                 case UEC_NUM_OF_THREADS_2:
795                         num_threads_numerica = 2;
796                         break;
797                 case UEC_NUM_OF_THREADS_4:
798                         num_threads_numerica = 4;
799                         break;
800                 case UEC_NUM_OF_THREADS_6:
801                         num_threads_numerica = 6;
802                         break;
803                 case UEC_NUM_OF_THREADS_8:
804                         num_threads_numerica = 8;
805                         break;
806                 default:
807                         printf("%s: Bad number of threads value.",
808                                  __FUNCTION__);
809                         return -EINVAL;
810         }
811
812         *threads_num_ret = num_threads_numerica;
813
814         return 0;
815 }
816
817 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
818 {
819         uec_info_t      *uec_info;
820         u32             end_bd;
821         u8              bmrx = 0;
822         int             i;
823
824         uec_info = uec->uec_info;
825
826         /* Alloc global Tx parameter RAM page */
827         uec->tx_glbl_pram_offset = qe_muram_alloc(
828                                 sizeof(uec_tx_global_pram_t),
829                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
830         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
831                                 qe_muram_addr(uec->tx_glbl_pram_offset);
832
833         /* Zero the global Tx prameter RAM */
834         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
835
836         /* Init global Tx parameter RAM */
837
838         /* TEMODER, RMON statistics disable, one Tx queue */
839         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
840
841         /* SQPTR */
842         uec->send_q_mem_reg_offset = qe_muram_alloc(
843                                 sizeof(uec_send_queue_qd_t),
844                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
845         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
846                                 qe_muram_addr(uec->send_q_mem_reg_offset);
847         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
848
849         /* Setup the table with TxBDs ring */
850         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
851                                          * SIZEOFBD;
852         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
853                                  (u32)(uec->p_tx_bd_ring));
854         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
855                                                  end_bd);
856
857         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
858         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
859
860         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
861         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
862
863         /* TSTATE, global snooping, big endian, the CSB bus selected */
864         bmrx = BMR_INIT_VALUE;
865         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
866
867         /* IPH_Offset */
868         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
869                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
870         }
871
872         /* VTAG table */
873         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
874                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
875         }
876
877         /* TQPTR */
878         uec->thread_dat_tx_offset = qe_muram_alloc(
879                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
880                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
881
882         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
883                                 qe_muram_addr(uec->thread_dat_tx_offset);
884         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
885 }
886
887 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
888 {
889         u8      bmrx = 0;
890         int     i;
891         uec_82xx_address_filtering_pram_t       *p_af_pram;
892
893         /* Allocate global Rx parameter RAM page */
894         uec->rx_glbl_pram_offset = qe_muram_alloc(
895                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
896         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
897                                 qe_muram_addr(uec->rx_glbl_pram_offset);
898
899         /* Zero Global Rx parameter RAM */
900         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
901
902         /* Init global Rx parameter RAM */
903         /* REMODER, Extended feature mode disable, VLAN disable,
904          LossLess flow control disable, Receive firmware statisic disable,
905          Extended address parsing mode disable, One Rx queues,
906          Dynamic maximum/minimum frame length disable, IP checksum check
907          disable, IP address alignment disable
908         */
909         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
910
911         /* RQPTR */
912         uec->thread_dat_rx_offset = qe_muram_alloc(
913                         num_threads_rx * sizeof(uec_thread_data_rx_t),
914                          UEC_THREAD_DATA_ALIGNMENT);
915         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
916                                 qe_muram_addr(uec->thread_dat_rx_offset);
917         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
918
919         /* Type_or_Len */
920         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
921
922         /* RxRMON base pointer, we don't need it */
923         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
924
925         /* IntCoalescingPTR, we don't need it, no interrupt */
926         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
927
928         /* RSTATE, global snooping, big endian, the CSB bus selected */
929         bmrx = BMR_INIT_VALUE;
930         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
931
932         /* MRBLR */
933         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
934
935         /* RBDQPTR */
936         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
937                                 sizeof(uec_rx_bd_queues_entry_t) + \
938                                 sizeof(uec_rx_prefetched_bds_t),
939                                  UEC_RX_BD_QUEUES_ALIGNMENT);
940         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
941                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
942
943         /* Zero it */
944         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
945                                         sizeof(uec_rx_prefetched_bds_t));
946         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
947         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
948                  (u32)uec->p_rx_bd_ring);
949
950         /* MFLR */
951         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
952         /* MINFLR */
953         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
954         /* MAXD1 */
955         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
956         /* MAXD2 */
957         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
958         /* ECAM_PTR */
959         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
960         /* L2QT */
961         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
962         /* L3QT */
963         for (i = 0; i < 8; i++) {
964                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
965         }
966
967         /* VLAN_TYPE */
968         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
969         /* TCI */
970         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
971
972         /* Clear PQ2 style address filtering hash table */
973         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
974                         uec->p_rx_glbl_pram->addressfiltering;
975
976         p_af_pram->iaddr_h = 0;
977         p_af_pram->iaddr_l = 0;
978         p_af_pram->gaddr_h = 0;
979         p_af_pram->gaddr_l = 0;
980 }
981
982 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
983                                          int thread_tx, int thread_rx)
984 {
985         uec_init_cmd_pram_t             *p_init_enet_param;
986         u32                             init_enet_param_offset;
987         uec_info_t                      *uec_info;
988         int                             i;
989         int                             snum;
990         u32                             init_enet_offset;
991         u32                             entry_val;
992         u32                             command;
993         u32                             cecr_subblock;
994
995         uec_info = uec->uec_info;
996
997         /* Allocate init enet command parameter */
998         uec->init_enet_param_offset = qe_muram_alloc(
999                                         sizeof(uec_init_cmd_pram_t), 4);
1000         init_enet_param_offset = uec->init_enet_param_offset;
1001         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
1002                                 qe_muram_addr(uec->init_enet_param_offset);
1003
1004         /* Zero init enet command struct */
1005         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
1006
1007         /* Init the command struct */
1008         p_init_enet_param = uec->p_init_enet_param;
1009         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
1010         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
1011         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
1012         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
1013         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
1014         p_init_enet_param->largestexternallookupkeysize = 0;
1015
1016         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
1017                                          << ENET_INIT_PARAM_RGF_SHIFT;
1018         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
1019                                          << ENET_INIT_PARAM_TGF_SHIFT;
1020
1021         /* Init Rx global parameter pointer */
1022         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
1023                                                  (u32)uec_info->risc_rx;
1024
1025         /* Init Rx threads */
1026         for (i = 0; i < (thread_rx + 1); i++) {
1027                 if ((snum = qe_get_snum()) < 0) {
1028                         printf("%s can not get snum\n", __FUNCTION__);
1029                         return -ENOMEM;
1030                 }
1031
1032                 if (i==0) {
1033                         init_enet_offset = 0;
1034                 } else {
1035                         init_enet_offset = qe_muram_alloc(
1036                                         sizeof(uec_thread_rx_pram_t),
1037                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
1038                 }
1039
1040                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1041                                  init_enet_offset | (u32)uec_info->risc_rx;
1042                 p_init_enet_param->rxthread[i] = entry_val;
1043         }
1044
1045         /* Init Tx global parameter pointer */
1046         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
1047                                          (u32)uec_info->risc_tx;
1048
1049         /* Init Tx threads */
1050         for (i = 0; i < thread_tx; i++) {
1051                 if ((snum = qe_get_snum()) < 0) {
1052                         printf("%s can not get snum\n", __FUNCTION__);
1053                         return -ENOMEM;
1054                 }
1055
1056                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
1057                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
1058
1059                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1060                                  init_enet_offset | (u32)uec_info->risc_tx;
1061                 p_init_enet_param->txthread[i] = entry_val;
1062         }
1063
1064         __asm__ __volatile__("sync");
1065
1066         /* Issue QE command */
1067         command = QE_INIT_TX_RX;
1068         cecr_subblock = ucc_fast_get_qe_cr_subblock(
1069                                 uec->uec_info->uf_info.ucc_num);
1070         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1071                                                  init_enet_param_offset);
1072
1073         return 0;
1074 }
1075
1076 static int uec_startup(uec_private_t *uec)
1077 {
1078         uec_info_t                      *uec_info;
1079         ucc_fast_info_t                 *uf_info;
1080         ucc_fast_private_t              *uccf;
1081         ucc_fast_t                      *uf_regs;
1082         uec_t                           *uec_regs;
1083         int                             num_threads_tx;
1084         int                             num_threads_rx;
1085         u32                             utbipar;
1086         enet_interface_e                enet_interface;
1087         u32                             length;
1088         u32                             align;
1089         qe_bd_t                         *bd;
1090         u8                              *buf;
1091         int                             i;
1092
1093         if (!uec || !uec->uec_info) {
1094                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1095                 return -EINVAL;
1096         }
1097
1098         uec_info = uec->uec_info;
1099         uf_info = &(uec_info->uf_info);
1100
1101         /* Check if Rx BD ring len is illegal */
1102         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1103                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1104                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1105                          __FUNCTION__);
1106                 return -EINVAL;
1107         }
1108
1109         /* Check if Tx BD ring len is illegal */
1110         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1111                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1112                          __FUNCTION__);
1113                 return -EINVAL;
1114         }
1115
1116         /* Check if MRBLR is illegal */
1117         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1118                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1119                          __FUNCTION__);
1120                 return -EINVAL;
1121         }
1122
1123         /* Both Rx and Tx are stopped */
1124         uec->grace_stopped_rx = 1;
1125         uec->grace_stopped_tx = 1;
1126
1127         /* Init UCC fast */
1128         if (ucc_fast_init(uf_info, &uccf)) {
1129                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1130                 return -ENOMEM;
1131         }
1132
1133         /* Save uccf */
1134         uec->uccf = uccf;
1135
1136         /* Convert the Tx threads number */
1137         if (uec_convert_threads_num(uec_info->num_threads_tx,
1138                                          &num_threads_tx)) {
1139                 return -EINVAL;
1140         }
1141
1142         /* Convert the Rx threads number */
1143         if (uec_convert_threads_num(uec_info->num_threads_rx,
1144                                          &num_threads_rx)) {
1145                 return -EINVAL;
1146         }
1147
1148         uf_regs = uccf->uf_regs;
1149
1150         /* UEC register is following UCC fast registers */
1151         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1152
1153         /* Save the UEC register pointer to UEC private struct */
1154         uec->uec_regs = uec_regs;
1155
1156         /* Init UPSMR, enable hardware statistics (UCC) */
1157         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1158
1159         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1160         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1161
1162         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1163         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1164
1165         /* Setup MAC interface mode */
1166         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1167
1168         /* Setup MII management base */
1169 #ifndef CONFIG_eTSEC_MDIO_BUS
1170         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1171 #else
1172         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1173 #endif
1174
1175         /* Setup MII master clock source */
1176         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1177
1178         /* Setup UTBIPAR */
1179         utbipar = in_be32(&uec_regs->utbipar);
1180         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1181         enet_interface = uec->uec_info->enet_interface;
1182         if (enet_interface == ENET_1000_TBI ||
1183                  enet_interface == ENET_1000_RTBI) {
1184                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1185                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1186         } else {
1187                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1188                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1189         }
1190
1191         out_be32(&uec_regs->utbipar, utbipar);
1192
1193         /* Allocate Tx BDs */
1194         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1195                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1196                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1197         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1198                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1199                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1200         }
1201
1202         align = UEC_TX_BD_RING_ALIGNMENT;
1203         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1204         if (uec->tx_bd_ring_offset != 0) {
1205                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1206                                                  & ~(align - 1));
1207         }
1208
1209         /* Zero all of Tx BDs */
1210         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1211
1212         /* Allocate Rx BDs */
1213         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1214         align = UEC_RX_BD_RING_ALIGNMENT;
1215         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1216         if (uec->rx_bd_ring_offset != 0) {
1217                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1218                                                          & ~(align - 1));
1219         }
1220
1221         /* Zero all of Rx BDs */
1222         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1223
1224         /* Allocate Rx buffer */
1225         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1226         align = UEC_RX_DATA_BUF_ALIGNMENT;
1227         uec->rx_buf_offset = (u32)malloc(length + align);
1228         if (uec->rx_buf_offset != 0) {
1229                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1230                                                  & ~(align - 1));
1231         }
1232
1233         /* Zero all of the Rx buffer */
1234         memset((void *)(uec->rx_buf_offset), 0, length + align);
1235
1236         /* Init TxBD ring */
1237         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1238         uec->txBd = bd;
1239
1240         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1241                 BD_DATA_CLEAR(bd);
1242                 BD_STATUS_SET(bd, 0);
1243                 BD_LENGTH_SET(bd, 0);
1244                 bd ++;
1245         }
1246         BD_STATUS_SET((--bd), TxBD_WRAP);
1247
1248         /* Init RxBD ring */
1249         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1250         uec->rxBd = bd;
1251         buf = uec->p_rx_buf;
1252         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1253                 BD_DATA_SET(bd, buf);
1254                 BD_LENGTH_SET(bd, 0);
1255                 BD_STATUS_SET(bd, RxBD_EMPTY);
1256                 buf += MAX_RXBUF_LEN;
1257                 bd ++;
1258         }
1259         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1260
1261         /* Init global Tx parameter RAM */
1262         uec_init_tx_parameter(uec, num_threads_tx);
1263
1264         /* Init global Rx parameter RAM */
1265         uec_init_rx_parameter(uec, num_threads_rx);
1266
1267         /* Init ethernet Tx and Rx parameter command */
1268         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1269                                          num_threads_rx)) {
1270                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1271                 return -ENOMEM;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int uec_init(struct eth_device* dev, bd_t *bd)
1278 {
1279         uec_private_t           *uec;
1280         int                     err, i;
1281         struct phy_info         *curphy;
1282
1283         uec = (uec_private_t *)dev->priv;
1284
1285         if (uec->the_first_run == 0) {
1286                 err = init_phy(dev);
1287                 if (err) {
1288                         printf("%s: Cannot initialize PHY, aborting.\n",
1289                                dev->name);
1290                         return err;
1291                 }
1292
1293                 curphy = uec->mii_info->phyinfo;
1294
1295                 if (curphy->config_aneg) {
1296                         err = curphy->config_aneg(uec->mii_info);
1297                         if (err) {
1298                                 printf("%s: Can't negotiate PHY\n", dev->name);
1299                                 return err;
1300                         }
1301                 }
1302
1303                 /* Give PHYs up to 5 sec to report a link */
1304                 i = 50;
1305                 do {
1306                         err = curphy->read_status(uec->mii_info);
1307                         udelay(100000);
1308                 } while (((i-- > 0) && !uec->mii_info->link) || err);
1309
1310                 if (err || i <= 0)
1311                         printf("warning: %s: timeout on PHY link\n", dev->name);
1312
1313                 uec->the_first_run = 1;
1314         }
1315
1316         /* Set up the MAC address */
1317         if (dev->enetaddr[0] & 0x01) {
1318                 printf("%s: MacAddress is multcast address\n",
1319                          __FUNCTION__);
1320                 return -1;
1321         }
1322         uec_set_mac_address(uec, dev->enetaddr);
1323
1324
1325         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1326         if (err) {
1327                 printf("%s: cannot enable UEC device\n", dev->name);
1328                 return -1;
1329         }
1330
1331         phy_change(dev);
1332
1333         return (uec->mii_info->link ? 0 : -1);
1334 }
1335
1336 static void uec_halt(struct eth_device* dev)
1337 {
1338         uec_private_t   *uec = (uec_private_t *)dev->priv;
1339         uec_stop(uec, COMM_DIR_RX_AND_TX);
1340 }
1341
1342 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1343 {
1344         uec_private_t           *uec;
1345         ucc_fast_private_t      *uccf;
1346         volatile qe_bd_t        *bd;
1347         u16                     status;
1348         int                     i;
1349         int                     result = 0;
1350
1351         uec = (uec_private_t *)dev->priv;
1352         uccf = uec->uccf;
1353         bd = uec->txBd;
1354
1355         /* Find an empty TxBD */
1356         for (i = 0; bd->status & TxBD_READY; i++) {
1357                 if (i > 0x100000) {
1358                         printf("%s: tx buffer not ready\n", dev->name);
1359                         return result;
1360                 }
1361         }
1362
1363         /* Init TxBD */
1364         BD_DATA_SET(bd, buf);
1365         BD_LENGTH_SET(bd, len);
1366         status = bd->status;
1367         status &= BD_WRAP;
1368         status |= (TxBD_READY | TxBD_LAST);
1369         BD_STATUS_SET(bd, status);
1370
1371         /* Tell UCC to transmit the buffer */
1372         ucc_fast_transmit_on_demand(uccf);
1373
1374         /* Wait for buffer to be transmitted */
1375         for (i = 0; bd->status & TxBD_READY; i++) {
1376                 if (i > 0x100000) {
1377                         printf("%s: tx error\n", dev->name);
1378                         return result;
1379                 }
1380         }
1381
1382         /* Ok, the buffer be transimitted */
1383         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1384         uec->txBd = bd;
1385         result = 1;
1386
1387         return result;
1388 }
1389
1390 static int uec_recv(struct eth_device* dev)
1391 {
1392         uec_private_t           *uec = dev->priv;
1393         volatile qe_bd_t        *bd;
1394         u16                     status;
1395         u16                     len;
1396         u8                      *data;
1397
1398         bd = uec->rxBd;
1399         status = bd->status;
1400
1401         while (!(status & RxBD_EMPTY)) {
1402                 if (!(status & RxBD_ERROR)) {
1403                         data = BD_DATA(bd);
1404                         len = BD_LENGTH(bd);
1405                         NetReceive(data, len);
1406                 } else {
1407                         printf("%s: Rx error\n", dev->name);
1408                 }
1409                 status &= BD_CLEAN;
1410                 BD_LENGTH_SET(bd, 0);
1411                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1412                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1413                 status = bd->status;
1414         }
1415         uec->rxBd = bd;
1416
1417         return 1;
1418 }
1419
1420 int uec_initialize(int index)
1421 {
1422         struct eth_device       *dev;
1423         int                     i;
1424         uec_private_t           *uec;
1425         uec_info_t              *uec_info;
1426         int                     err;
1427
1428         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1429         if (!dev)
1430                 return 0;
1431         memset(dev, 0, sizeof(struct eth_device));
1432
1433         /* Allocate the UEC private struct */
1434         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1435         if (!uec) {
1436                 return -ENOMEM;
1437         }
1438         memset(uec, 0, sizeof(uec_private_t));
1439
1440         /* Init UEC private struct, they come from board.h */
1441         uec_info = NULL;
1442         if (index == 0) {
1443 #ifdef CONFIG_UEC_ETH1
1444                 uec_info = &eth1_uec_info;
1445 #endif
1446         } else if (index == 1) {
1447 #ifdef CONFIG_UEC_ETH2
1448                 uec_info = &eth2_uec_info;
1449 #endif
1450         } else if (index == 2) {
1451 #ifdef CONFIG_UEC_ETH3
1452                 uec_info = &eth3_uec_info;
1453 #endif
1454         } else if (index == 3) {
1455 #ifdef CONFIG_UEC_ETH4
1456                 uec_info = &eth4_uec_info;
1457 #endif
1458         } else if (index == 4) {
1459 #ifdef CONFIG_UEC_ETH5
1460                 uec_info = &eth5_uec_info;
1461 #endif
1462         } else if (index == 5) {
1463 #ifdef CONFIG_UEC_ETH6
1464                 uec_info = &eth6_uec_info;
1465 #endif
1466         } else {
1467                 printf("%s: index is illegal.\n", __FUNCTION__);
1468                 return -EINVAL;
1469         }
1470
1471         devlist[index] = dev;
1472
1473         uec->uec_info = uec_info;
1474
1475         sprintf(dev->name, "FSL UEC%d", index);
1476         dev->iobase = 0;
1477         dev->priv = (void *)uec;
1478         dev->init = uec_init;
1479         dev->halt = uec_halt;
1480         dev->send = uec_send;
1481         dev->recv = uec_recv;
1482
1483         /* Clear the ethnet address */
1484         for (i = 0; i < 6; i++)
1485                 dev->enetaddr[i] = 0;
1486
1487         eth_register(dev);
1488
1489         err = uec_startup(uec);
1490         if (err) {
1491                 printf("%s: Cannot configure net device, aborting.",dev->name);
1492                 return err;
1493         }
1494
1495 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1496         && !defined(BITBANGMII)
1497         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1498 #endif
1499
1500         return 1;
1501 }