Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[platform/kernel/u-boot.git] / drivers / qe / uec.c
1 /*
2  * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32 #include "miiphy.h"
33
34 /* Default UTBIPAR SMI address */
35 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
36 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
37 #endif
38
39 static uec_info_t uec_info[] = {
40 #ifdef CONFIG_UEC_ETH1
41         STD_UEC_INFO(1),        /* UEC1 */
42 #endif
43 #ifdef CONFIG_UEC_ETH2
44         STD_UEC_INFO(2),        /* UEC2 */
45 #endif
46 #ifdef CONFIG_UEC_ETH3
47         STD_UEC_INFO(3),        /* UEC3 */
48 #endif
49 #ifdef CONFIG_UEC_ETH4
50         STD_UEC_INFO(4),        /* UEC4 */
51 #endif
52 #ifdef CONFIG_UEC_ETH5
53         STD_UEC_INFO(5),        /* UEC5 */
54 #endif
55 #ifdef CONFIG_UEC_ETH6
56         STD_UEC_INFO(6),        /* UEC6 */
57 #endif
58 #ifdef CONFIG_UEC_ETH7
59         STD_UEC_INFO(7),        /* UEC7 */
60 #endif
61 #ifdef CONFIG_UEC_ETH8
62         STD_UEC_INFO(8),        /* UEC8 */
63 #endif
64 };
65
66 #define MAXCONTROLLERS  (8)
67
68 static struct eth_device *devlist[MAXCONTROLLERS];
69
70 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
71 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
72
73 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
74 {
75         uec_t           *uec_regs;
76         u32             maccfg1;
77
78         if (!uec) {
79                 printf("%s: uec not initial\n", __FUNCTION__);
80                 return -EINVAL;
81         }
82         uec_regs = uec->uec_regs;
83
84         maccfg1 = in_be32(&uec_regs->maccfg1);
85
86         if (mode & COMM_DIR_TX) {
87                 maccfg1 |= MACCFG1_ENABLE_TX;
88                 out_be32(&uec_regs->maccfg1, maccfg1);
89                 uec->mac_tx_enabled = 1;
90         }
91
92         if (mode & COMM_DIR_RX) {
93                 maccfg1 |= MACCFG1_ENABLE_RX;
94                 out_be32(&uec_regs->maccfg1, maccfg1);
95                 uec->mac_rx_enabled = 1;
96         }
97
98         return 0;
99 }
100
101 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
102 {
103         uec_t           *uec_regs;
104         u32             maccfg1;
105
106         if (!uec) {
107                 printf("%s: uec not initial\n", __FUNCTION__);
108                 return -EINVAL;
109         }
110         uec_regs = uec->uec_regs;
111
112         maccfg1 = in_be32(&uec_regs->maccfg1);
113
114         if (mode & COMM_DIR_TX) {
115                 maccfg1 &= ~MACCFG1_ENABLE_TX;
116                 out_be32(&uec_regs->maccfg1, maccfg1);
117                 uec->mac_tx_enabled = 0;
118         }
119
120         if (mode & COMM_DIR_RX) {
121                 maccfg1 &= ~MACCFG1_ENABLE_RX;
122                 out_be32(&uec_regs->maccfg1, maccfg1);
123                 uec->mac_rx_enabled = 0;
124         }
125
126         return 0;
127 }
128
129 static int uec_graceful_stop_tx(uec_private_t *uec)
130 {
131         ucc_fast_t              *uf_regs;
132         u32                     cecr_subblock;
133         u32                     ucce;
134
135         if (!uec || !uec->uccf) {
136                 printf("%s: No handle passed.\n", __FUNCTION__);
137                 return -EINVAL;
138         }
139
140         uf_regs = uec->uccf->uf_regs;
141
142         /* Clear the grace stop event */
143         out_be32(&uf_regs->ucce, UCCE_GRA);
144
145         /* Issue host command */
146         cecr_subblock =
147                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
148         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
149                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
150
151         /* Wait for command to complete */
152         do {
153                 ucce = in_be32(&uf_regs->ucce);
154         } while (! (ucce & UCCE_GRA));
155
156         uec->grace_stopped_tx = 1;
157
158         return 0;
159 }
160
161 static int uec_graceful_stop_rx(uec_private_t *uec)
162 {
163         u32             cecr_subblock;
164         u8              ack;
165
166         if (!uec) {
167                 printf("%s: No handle passed.\n", __FUNCTION__);
168                 return -EINVAL;
169         }
170
171         if (!uec->p_rx_glbl_pram) {
172                 printf("%s: No init rx global parameter\n", __FUNCTION__);
173                 return -EINVAL;
174         }
175
176         /* Clear acknowledge bit */
177         ack = uec->p_rx_glbl_pram->rxgstpack;
178         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
179         uec->p_rx_glbl_pram->rxgstpack = ack;
180
181         /* Keep issuing cmd and checking ack bit until it is asserted */
182         do {
183                 /* Issue host command */
184                 cecr_subblock =
185                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
186                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
187                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
188                 ack = uec->p_rx_glbl_pram->rxgstpack;
189         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
190
191         uec->grace_stopped_rx = 1;
192
193         return 0;
194 }
195
196 static int uec_restart_tx(uec_private_t *uec)
197 {
198         u32             cecr_subblock;
199
200         if (!uec || !uec->uec_info) {
201                 printf("%s: No handle passed.\n", __FUNCTION__);
202                 return -EINVAL;
203         }
204
205         cecr_subblock =
206          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
207         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
208                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
209
210         uec->grace_stopped_tx = 0;
211
212         return 0;
213 }
214
215 static int uec_restart_rx(uec_private_t *uec)
216 {
217         u32             cecr_subblock;
218
219         if (!uec || !uec->uec_info) {
220                 printf("%s: No handle passed.\n", __FUNCTION__);
221                 return -EINVAL;
222         }
223
224         cecr_subblock =
225          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
226         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
227                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
228
229         uec->grace_stopped_rx = 0;
230
231         return 0;
232 }
233
234 static int uec_open(uec_private_t *uec, comm_dir_e mode)
235 {
236         ucc_fast_private_t      *uccf;
237
238         if (!uec || !uec->uccf) {
239                 printf("%s: No handle passed.\n", __FUNCTION__);
240                 return -EINVAL;
241         }
242         uccf = uec->uccf;
243
244         /* check if the UCC number is in range. */
245         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
246                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
247                 return -EINVAL;
248         }
249
250         /* Enable MAC */
251         uec_mac_enable(uec, mode);
252
253         /* Enable UCC fast */
254         ucc_fast_enable(uccf, mode);
255
256         /* RISC microcode start */
257         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
258                 uec_restart_tx(uec);
259         }
260         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
261                 uec_restart_rx(uec);
262         }
263
264         return 0;
265 }
266
267 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
268 {
269         ucc_fast_private_t      *uccf;
270
271         if (!uec || !uec->uccf) {
272                 printf("%s: No handle passed.\n", __FUNCTION__);
273                 return -EINVAL;
274         }
275         uccf = uec->uccf;
276
277         /* check if the UCC number is in range. */
278         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
279                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
280                 return -EINVAL;
281         }
282         /* Stop any transmissions */
283         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
284                 uec_graceful_stop_tx(uec);
285         }
286         /* Stop any receptions */
287         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
288                 uec_graceful_stop_rx(uec);
289         }
290
291         /* Disable the UCC fast */
292         ucc_fast_disable(uec->uccf, mode);
293
294         /* Disable the MAC */
295         uec_mac_disable(uec, mode);
296
297         return 0;
298 }
299
300 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
301 {
302         uec_t           *uec_regs;
303         u32             maccfg2;
304
305         if (!uec) {
306                 printf("%s: uec not initial\n", __FUNCTION__);
307                 return -EINVAL;
308         }
309         uec_regs = uec->uec_regs;
310
311         if (duplex == DUPLEX_HALF) {
312                 maccfg2 = in_be32(&uec_regs->maccfg2);
313                 maccfg2 &= ~MACCFG2_FDX;
314                 out_be32(&uec_regs->maccfg2, maccfg2);
315         }
316
317         if (duplex == DUPLEX_FULL) {
318                 maccfg2 = in_be32(&uec_regs->maccfg2);
319                 maccfg2 |= MACCFG2_FDX;
320                 out_be32(&uec_regs->maccfg2, maccfg2);
321         }
322
323         return 0;
324 }
325
326 static int uec_set_mac_if_mode(uec_private_t *uec,
327                 enum fsl_phy_enet_if if_mode, int speed)
328 {
329         enum fsl_phy_enet_if    enet_if_mode;
330         uec_info_t              *uec_info;
331         uec_t                   *uec_regs;
332         u32                     upsmr;
333         u32                     maccfg2;
334
335         if (!uec) {
336                 printf("%s: uec not initial\n", __FUNCTION__);
337                 return -EINVAL;
338         }
339
340         uec_info = uec->uec_info;
341         uec_regs = uec->uec_regs;
342         enet_if_mode = if_mode;
343
344         maccfg2 = in_be32(&uec_regs->maccfg2);
345         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
346
347         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
348         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
349
350         switch (speed) {
351                 case 10:
352                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
353                         switch (enet_if_mode) {
354                                 case MII:
355                                         break;
356                                 case RGMII:
357                                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
358                                         break;
359                                 case RMII:
360                                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
361                                         break;
362                                 default:
363                                         return -EINVAL;
364                                         break;
365                         }
366                         break;
367                 case 100:
368                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
369                         switch (enet_if_mode) {
370                                 case MII:
371                                         break;
372                                 case RGMII:
373                                         upsmr |= UPSMR_RPM;
374                                         break;
375                                 case RMII:
376                                         upsmr |= UPSMR_RMM;
377                                         break;
378                                 default:
379                                         return -EINVAL;
380                                         break;
381                         }
382                         break;
383                 case 1000:
384                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
385                         switch (enet_if_mode) {
386                                 case GMII:
387                                         break;
388                                 case TBI:
389                                         upsmr |= UPSMR_TBIM;
390                                         break;
391                                 case RTBI:
392                                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
393                                         break;
394                                 case RGMII_RXID:
395                                 case RGMII_ID:
396                                 case RGMII:
397                                         upsmr |= UPSMR_RPM;
398                                         break;
399                                 case SGMII:
400                                         upsmr |= UPSMR_SGMM;
401                                         break;
402                                 default:
403                                         return -EINVAL;
404                                         break;
405                         }
406                         break;
407                 default:
408                         return -EINVAL;
409                         break;
410         }
411
412         out_be32(&uec_regs->maccfg2, maccfg2);
413         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
414
415         return 0;
416 }
417
418 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
419 {
420         uint            timeout = 0x1000;
421         u32             miimcfg = 0;
422
423         miimcfg = in_be32(&uec_mii_regs->miimcfg);
424         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
425         out_be32(&uec_mii_regs->miimcfg, miimcfg);
426
427         /* Wait until the bus is free */
428         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
429         if (timeout <= 0) {
430                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
431                 return -ETIMEDOUT;
432         }
433
434         return 0;
435 }
436
437 static int init_phy(struct eth_device *dev)
438 {
439         uec_private_t           *uec;
440         uec_mii_t               *umii_regs;
441         struct uec_mii_info     *mii_info;
442         struct phy_info         *curphy;
443         int                     err;
444
445         uec = (uec_private_t *)dev->priv;
446         umii_regs = uec->uec_mii_regs;
447
448         uec->oldlink = 0;
449         uec->oldspeed = 0;
450         uec->oldduplex = -1;
451
452         mii_info = malloc(sizeof(*mii_info));
453         if (!mii_info) {
454                 printf("%s: Could not allocate mii_info", dev->name);
455                 return -ENOMEM;
456         }
457         memset(mii_info, 0, sizeof(*mii_info));
458
459         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
460                 mii_info->speed = SPEED_1000;
461         } else {
462                 mii_info->speed = SPEED_100;
463         }
464
465         mii_info->duplex = DUPLEX_FULL;
466         mii_info->pause = 0;
467         mii_info->link = 1;
468
469         mii_info->advertising = (ADVERTISED_10baseT_Half |
470                                 ADVERTISED_10baseT_Full |
471                                 ADVERTISED_100baseT_Half |
472                                 ADVERTISED_100baseT_Full |
473                                 ADVERTISED_1000baseT_Full);
474         mii_info->autoneg = 1;
475         mii_info->mii_id = uec->uec_info->phy_address;
476         mii_info->dev = dev;
477
478         mii_info->mdio_read = &uec_read_phy_reg;
479         mii_info->mdio_write = &uec_write_phy_reg;
480
481         uec->mii_info = mii_info;
482
483         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
484
485         if (init_mii_management_configuration(umii_regs)) {
486                 printf("%s: The MII Bus is stuck!", dev->name);
487                 err = -1;
488                 goto bus_fail;
489         }
490
491         /* get info for this PHY */
492         curphy = uec_get_phy_info(uec->mii_info);
493         if (!curphy) {
494                 printf("%s: No PHY found", dev->name);
495                 err = -1;
496                 goto no_phy;
497         }
498
499         mii_info->phyinfo = curphy;
500
501         /* Run the commands which initialize the PHY */
502         if (curphy->init) {
503                 err = curphy->init(uec->mii_info);
504                 if (err)
505                         goto phy_init_fail;
506         }
507
508         return 0;
509
510 phy_init_fail:
511 no_phy:
512 bus_fail:
513         free(mii_info);
514         return err;
515 }
516
517 static void adjust_link(struct eth_device *dev)
518 {
519         uec_private_t           *uec = (uec_private_t *)dev->priv;
520         uec_t                   *uec_regs;
521         struct uec_mii_info     *mii_info = uec->mii_info;
522
523         extern void change_phy_interface_mode(struct eth_device *dev,
524                                  enum fsl_phy_enet_if mode, int speed);
525         uec_regs = uec->uec_regs;
526
527         if (mii_info->link) {
528                 /* Now we make sure that we can be in full duplex mode.
529                 * If not, we operate in half-duplex mode. */
530                 if (mii_info->duplex != uec->oldduplex) {
531                         if (!(mii_info->duplex)) {
532                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
533                                 printf("%s: Half Duplex\n", dev->name);
534                         } else {
535                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
536                                 printf("%s: Full Duplex\n", dev->name);
537                         }
538                         uec->oldduplex = mii_info->duplex;
539                 }
540
541                 if (mii_info->speed != uec->oldspeed) {
542                         enum fsl_phy_enet_if    mode = \
543                                 uec->uec_info->enet_interface_type;
544                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
545                                 switch (mii_info->speed) {
546                                 case 1000:
547                                         break;
548                                 case 100:
549                                         printf ("switching to rgmii 100\n");
550                                         mode = RGMII;
551                                         break;
552                                 case 10:
553                                         printf ("switching to rgmii 10\n");
554                                         mode = RGMII;
555                                         break;
556                                 default:
557                                         printf("%s: Ack,Speed(%d)is illegal\n",
558                                                 dev->name, mii_info->speed);
559                                         break;
560                                 }
561                         }
562
563                         /* change phy */
564                         change_phy_interface_mode(dev, mode, mii_info->speed);
565                         /* change the MAC interface mode */
566                         uec_set_mac_if_mode(uec, mode, mii_info->speed);
567
568                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
569                         uec->oldspeed = mii_info->speed;
570                 }
571
572                 if (!uec->oldlink) {
573                         printf("%s: Link is up\n", dev->name);
574                         uec->oldlink = 1;
575                 }
576
577         } else { /* if (mii_info->link) */
578                 if (uec->oldlink) {
579                         printf("%s: Link is down\n", dev->name);
580                         uec->oldlink = 0;
581                         uec->oldspeed = 0;
582                         uec->oldduplex = -1;
583                 }
584         }
585 }
586
587 static void phy_change(struct eth_device *dev)
588 {
589         uec_private_t   *uec = (uec_private_t *)dev->priv;
590
591 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
592     defined(CONFIG_P1021) || defined(CONFIG_P1025)
593         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
594
595         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
596         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
597         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
598 #endif
599
600         /* Update the link, speed, duplex */
601         uec->mii_info->phyinfo->read_status(uec->mii_info);
602
603 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
604     defined(CONFIG_P1021) || defined(CONFIG_P1025)
605         /*
606          * QE12 is muxed with LBCTL, it needs to be released for enabling
607          * LBCTL signal for LBC usage.
608          */
609         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
610 #endif
611
612         /* Adjust the interface according to speed */
613         adjust_link(dev);
614 }
615
616 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
617
618 /*
619  * Find a device index from the devlist by name
620  *
621  * Returns:
622  *  The index where the device is located, -1 on error
623  */
624 static int uec_miiphy_find_dev_by_name(const char *devname)
625 {
626         int i;
627
628         for (i = 0; i < MAXCONTROLLERS; i++) {
629                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
630                         break;
631                 }
632         }
633
634         /* If device cannot be found, returns -1 */
635         if (i == MAXCONTROLLERS) {
636                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
637                 i = -1;
638         }
639
640         return i;
641 }
642
643 /*
644  * Read a MII PHY register.
645  *
646  * Returns:
647  *  0 on success
648  */
649 static int uec_miiphy_read(const char *devname, unsigned char addr,
650                             unsigned char reg, unsigned short *value)
651 {
652         int devindex = 0;
653
654         if (devname == NULL || value == NULL) {
655                 debug("%s: NULL pointer given\n", __FUNCTION__);
656         } else {
657                 devindex = uec_miiphy_find_dev_by_name(devname);
658                 if (devindex >= 0) {
659                         *value = uec_read_phy_reg(devlist[devindex], addr, reg);
660                 }
661         }
662         return 0;
663 }
664
665 /*
666  * Write a MII PHY register.
667  *
668  * Returns:
669  *  0 on success
670  */
671 static int uec_miiphy_write(const char *devname, unsigned char addr,
672                              unsigned char reg, unsigned short value)
673 {
674         int devindex = 0;
675
676         if (devname == NULL) {
677                 debug("%s: NULL pointer given\n", __FUNCTION__);
678         } else {
679                 devindex = uec_miiphy_find_dev_by_name(devname);
680                 if (devindex >= 0) {
681                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
682                 }
683         }
684         return 0;
685 }
686 #endif
687
688 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
689 {
690         uec_t           *uec_regs;
691         u32             mac_addr1;
692         u32             mac_addr2;
693
694         if (!uec) {
695                 printf("%s: uec not initial\n", __FUNCTION__);
696                 return -EINVAL;
697         }
698
699         uec_regs = uec->uec_regs;
700
701         /* if a station address of 0x12345678ABCD, perform a write to
702         MACSTNADDR1 of 0xCDAB7856,
703         MACSTNADDR2 of 0x34120000 */
704
705         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
706                         (mac_addr[3] << 8)  | (mac_addr[2]);
707         out_be32(&uec_regs->macstnaddr1, mac_addr1);
708
709         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
710         out_be32(&uec_regs->macstnaddr2, mac_addr2);
711
712         return 0;
713 }
714
715 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
716                                          int *threads_num_ret)
717 {
718         int     num_threads_numerica;
719
720         switch (threads_num) {
721                 case UEC_NUM_OF_THREADS_1:
722                         num_threads_numerica = 1;
723                         break;
724                 case UEC_NUM_OF_THREADS_2:
725                         num_threads_numerica = 2;
726                         break;
727                 case UEC_NUM_OF_THREADS_4:
728                         num_threads_numerica = 4;
729                         break;
730                 case UEC_NUM_OF_THREADS_6:
731                         num_threads_numerica = 6;
732                         break;
733                 case UEC_NUM_OF_THREADS_8:
734                         num_threads_numerica = 8;
735                         break;
736                 default:
737                         printf("%s: Bad number of threads value.",
738                                  __FUNCTION__);
739                         return -EINVAL;
740         }
741
742         *threads_num_ret = num_threads_numerica;
743
744         return 0;
745 }
746
747 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
748 {
749         uec_info_t      *uec_info;
750         u32             end_bd;
751         u8              bmrx = 0;
752         int             i;
753
754         uec_info = uec->uec_info;
755
756         /* Alloc global Tx parameter RAM page */
757         uec->tx_glbl_pram_offset = qe_muram_alloc(
758                                 sizeof(uec_tx_global_pram_t),
759                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
760         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
761                                 qe_muram_addr(uec->tx_glbl_pram_offset);
762
763         /* Zero the global Tx prameter RAM */
764         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
765
766         /* Init global Tx parameter RAM */
767
768         /* TEMODER, RMON statistics disable, one Tx queue */
769         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
770
771         /* SQPTR */
772         uec->send_q_mem_reg_offset = qe_muram_alloc(
773                                 sizeof(uec_send_queue_qd_t),
774                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
775         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
776                                 qe_muram_addr(uec->send_q_mem_reg_offset);
777         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
778
779         /* Setup the table with TxBDs ring */
780         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
781                                          * SIZEOFBD;
782         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
783                                  (u32)(uec->p_tx_bd_ring));
784         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
785                                                  end_bd);
786
787         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
788         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
789
790         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
791         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
792
793         /* TSTATE, global snooping, big endian, the CSB bus selected */
794         bmrx = BMR_INIT_VALUE;
795         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
796
797         /* IPH_Offset */
798         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
799                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
800         }
801
802         /* VTAG table */
803         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
804                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
805         }
806
807         /* TQPTR */
808         uec->thread_dat_tx_offset = qe_muram_alloc(
809                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
810                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
811
812         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
813                                 qe_muram_addr(uec->thread_dat_tx_offset);
814         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
815 }
816
817 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
818 {
819         u8      bmrx = 0;
820         int     i;
821         uec_82xx_address_filtering_pram_t       *p_af_pram;
822
823         /* Allocate global Rx parameter RAM page */
824         uec->rx_glbl_pram_offset = qe_muram_alloc(
825                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
826         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
827                                 qe_muram_addr(uec->rx_glbl_pram_offset);
828
829         /* Zero Global Rx parameter RAM */
830         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
831
832         /* Init global Rx parameter RAM */
833         /* REMODER, Extended feature mode disable, VLAN disable,
834          LossLess flow control disable, Receive firmware statisic disable,
835          Extended address parsing mode disable, One Rx queues,
836          Dynamic maximum/minimum frame length disable, IP checksum check
837          disable, IP address alignment disable
838         */
839         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
840
841         /* RQPTR */
842         uec->thread_dat_rx_offset = qe_muram_alloc(
843                         num_threads_rx * sizeof(uec_thread_data_rx_t),
844                          UEC_THREAD_DATA_ALIGNMENT);
845         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
846                                 qe_muram_addr(uec->thread_dat_rx_offset);
847         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
848
849         /* Type_or_Len */
850         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
851
852         /* RxRMON base pointer, we don't need it */
853         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
854
855         /* IntCoalescingPTR, we don't need it, no interrupt */
856         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
857
858         /* RSTATE, global snooping, big endian, the CSB bus selected */
859         bmrx = BMR_INIT_VALUE;
860         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
861
862         /* MRBLR */
863         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
864
865         /* RBDQPTR */
866         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
867                                 sizeof(uec_rx_bd_queues_entry_t) + \
868                                 sizeof(uec_rx_prefetched_bds_t),
869                                  UEC_RX_BD_QUEUES_ALIGNMENT);
870         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
871                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
872
873         /* Zero it */
874         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
875                                         sizeof(uec_rx_prefetched_bds_t));
876         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
877         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
878                  (u32)uec->p_rx_bd_ring);
879
880         /* MFLR */
881         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
882         /* MINFLR */
883         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
884         /* MAXD1 */
885         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
886         /* MAXD2 */
887         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
888         /* ECAM_PTR */
889         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
890         /* L2QT */
891         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
892         /* L3QT */
893         for (i = 0; i < 8; i++) {
894                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
895         }
896
897         /* VLAN_TYPE */
898         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
899         /* TCI */
900         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
901
902         /* Clear PQ2 style address filtering hash table */
903         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
904                         uec->p_rx_glbl_pram->addressfiltering;
905
906         p_af_pram->iaddr_h = 0;
907         p_af_pram->iaddr_l = 0;
908         p_af_pram->gaddr_h = 0;
909         p_af_pram->gaddr_l = 0;
910 }
911
912 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
913                                          int thread_tx, int thread_rx)
914 {
915         uec_init_cmd_pram_t             *p_init_enet_param;
916         u32                             init_enet_param_offset;
917         uec_info_t                      *uec_info;
918         int                             i;
919         int                             snum;
920         u32                             init_enet_offset;
921         u32                             entry_val;
922         u32                             command;
923         u32                             cecr_subblock;
924
925         uec_info = uec->uec_info;
926
927         /* Allocate init enet command parameter */
928         uec->init_enet_param_offset = qe_muram_alloc(
929                                         sizeof(uec_init_cmd_pram_t), 4);
930         init_enet_param_offset = uec->init_enet_param_offset;
931         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
932                                 qe_muram_addr(uec->init_enet_param_offset);
933
934         /* Zero init enet command struct */
935         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
936
937         /* Init the command struct */
938         p_init_enet_param = uec->p_init_enet_param;
939         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
940         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
941         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
942         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
943         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
944         p_init_enet_param->largestexternallookupkeysize = 0;
945
946         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
947                                          << ENET_INIT_PARAM_RGF_SHIFT;
948         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
949                                          << ENET_INIT_PARAM_TGF_SHIFT;
950
951         /* Init Rx global parameter pointer */
952         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
953                                                  (u32)uec_info->risc_rx;
954
955         /* Init Rx threads */
956         for (i = 0; i < (thread_rx + 1); i++) {
957                 if ((snum = qe_get_snum()) < 0) {
958                         printf("%s can not get snum\n", __FUNCTION__);
959                         return -ENOMEM;
960                 }
961
962                 if (i==0) {
963                         init_enet_offset = 0;
964                 } else {
965                         init_enet_offset = qe_muram_alloc(
966                                         sizeof(uec_thread_rx_pram_t),
967                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
968                 }
969
970                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
971                                  init_enet_offset | (u32)uec_info->risc_rx;
972                 p_init_enet_param->rxthread[i] = entry_val;
973         }
974
975         /* Init Tx global parameter pointer */
976         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
977                                          (u32)uec_info->risc_tx;
978
979         /* Init Tx threads */
980         for (i = 0; i < thread_tx; i++) {
981                 if ((snum = qe_get_snum()) < 0) {
982                         printf("%s can not get snum\n", __FUNCTION__);
983                         return -ENOMEM;
984                 }
985
986                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
987                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
988
989                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
990                                  init_enet_offset | (u32)uec_info->risc_tx;
991                 p_init_enet_param->txthread[i] = entry_val;
992         }
993
994         __asm__ __volatile__("sync");
995
996         /* Issue QE command */
997         command = QE_INIT_TX_RX;
998         cecr_subblock = ucc_fast_get_qe_cr_subblock(
999                                 uec->uec_info->uf_info.ucc_num);
1000         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1001                                                  init_enet_param_offset);
1002
1003         return 0;
1004 }
1005
1006 static int uec_startup(uec_private_t *uec)
1007 {
1008         uec_info_t                      *uec_info;
1009         ucc_fast_info_t                 *uf_info;
1010         ucc_fast_private_t              *uccf;
1011         ucc_fast_t                      *uf_regs;
1012         uec_t                           *uec_regs;
1013         int                             num_threads_tx;
1014         int                             num_threads_rx;
1015         u32                             utbipar;
1016         u32                             length;
1017         u32                             align;
1018         qe_bd_t                         *bd;
1019         u8                              *buf;
1020         int                             i;
1021
1022         if (!uec || !uec->uec_info) {
1023                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1024                 return -EINVAL;
1025         }
1026
1027         uec_info = uec->uec_info;
1028         uf_info = &(uec_info->uf_info);
1029
1030         /* Check if Rx BD ring len is illegal */
1031         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1032                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1033                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1034                          __FUNCTION__);
1035                 return -EINVAL;
1036         }
1037
1038         /* Check if Tx BD ring len is illegal */
1039         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1040                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1041                          __FUNCTION__);
1042                 return -EINVAL;
1043         }
1044
1045         /* Check if MRBLR is illegal */
1046         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1047                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1048                          __FUNCTION__);
1049                 return -EINVAL;
1050         }
1051
1052         /* Both Rx and Tx are stopped */
1053         uec->grace_stopped_rx = 1;
1054         uec->grace_stopped_tx = 1;
1055
1056         /* Init UCC fast */
1057         if (ucc_fast_init(uf_info, &uccf)) {
1058                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1059                 return -ENOMEM;
1060         }
1061
1062         /* Save uccf */
1063         uec->uccf = uccf;
1064
1065         /* Convert the Tx threads number */
1066         if (uec_convert_threads_num(uec_info->num_threads_tx,
1067                                          &num_threads_tx)) {
1068                 return -EINVAL;
1069         }
1070
1071         /* Convert the Rx threads number */
1072         if (uec_convert_threads_num(uec_info->num_threads_rx,
1073                                          &num_threads_rx)) {
1074                 return -EINVAL;
1075         }
1076
1077         uf_regs = uccf->uf_regs;
1078
1079         /* UEC register is following UCC fast registers */
1080         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1081
1082         /* Save the UEC register pointer to UEC private struct */
1083         uec->uec_regs = uec_regs;
1084
1085         /* Init UPSMR, enable hardware statistics (UCC) */
1086         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1087
1088         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1089         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1090
1091         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1092         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1093
1094         /* Setup MAC interface mode */
1095         uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1096
1097         /* Setup MII management base */
1098 #ifndef CONFIG_eTSEC_MDIO_BUS
1099         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1100 #else
1101         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1102 #endif
1103
1104         /* Setup MII master clock source */
1105         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1106
1107         /* Setup UTBIPAR */
1108         utbipar = in_be32(&uec_regs->utbipar);
1109         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1110
1111         /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1112          * This frees up the remaining SMI addresses for use.
1113          */
1114         utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1115         out_be32(&uec_regs->utbipar, utbipar);
1116
1117         /* Configure the TBI for SGMII operation */
1118         if ((uec->uec_info->enet_interface_type == SGMII) &&
1119            (uec->uec_info->speed == 1000)) {
1120                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1121                         ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1122
1123                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1124                         ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1125
1126                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1127                         ENET_TBI_MII_CR, TBICR_SETTINGS);
1128         }
1129
1130         /* Allocate Tx BDs */
1131         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1132                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1133                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1134         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1135                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1136                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1137         }
1138
1139         align = UEC_TX_BD_RING_ALIGNMENT;
1140         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1141         if (uec->tx_bd_ring_offset != 0) {
1142                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1143                                                  & ~(align - 1));
1144         }
1145
1146         /* Zero all of Tx BDs */
1147         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1148
1149         /* Allocate Rx BDs */
1150         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1151         align = UEC_RX_BD_RING_ALIGNMENT;
1152         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1153         if (uec->rx_bd_ring_offset != 0) {
1154                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1155                                                          & ~(align - 1));
1156         }
1157
1158         /* Zero all of Rx BDs */
1159         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1160
1161         /* Allocate Rx buffer */
1162         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1163         align = UEC_RX_DATA_BUF_ALIGNMENT;
1164         uec->rx_buf_offset = (u32)malloc(length + align);
1165         if (uec->rx_buf_offset != 0) {
1166                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1167                                                  & ~(align - 1));
1168         }
1169
1170         /* Zero all of the Rx buffer */
1171         memset((void *)(uec->rx_buf_offset), 0, length + align);
1172
1173         /* Init TxBD ring */
1174         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1175         uec->txBd = bd;
1176
1177         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1178                 BD_DATA_CLEAR(bd);
1179                 BD_STATUS_SET(bd, 0);
1180                 BD_LENGTH_SET(bd, 0);
1181                 bd ++;
1182         }
1183         BD_STATUS_SET((--bd), TxBD_WRAP);
1184
1185         /* Init RxBD ring */
1186         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1187         uec->rxBd = bd;
1188         buf = uec->p_rx_buf;
1189         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1190                 BD_DATA_SET(bd, buf);
1191                 BD_LENGTH_SET(bd, 0);
1192                 BD_STATUS_SET(bd, RxBD_EMPTY);
1193                 buf += MAX_RXBUF_LEN;
1194                 bd ++;
1195         }
1196         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1197
1198         /* Init global Tx parameter RAM */
1199         uec_init_tx_parameter(uec, num_threads_tx);
1200
1201         /* Init global Rx parameter RAM */
1202         uec_init_rx_parameter(uec, num_threads_rx);
1203
1204         /* Init ethernet Tx and Rx parameter command */
1205         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1206                                          num_threads_rx)) {
1207                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1208                 return -ENOMEM;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int uec_init(struct eth_device* dev, bd_t *bd)
1215 {
1216         uec_private_t           *uec;
1217         int                     err, i;
1218         struct phy_info         *curphy;
1219 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1220     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1221         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1222 #endif
1223
1224         uec = (uec_private_t *)dev->priv;
1225
1226         if (uec->the_first_run == 0) {
1227 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1228     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1229         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1230         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1231         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1232 #endif
1233
1234                 err = init_phy(dev);
1235                 if (err) {
1236                         printf("%s: Cannot initialize PHY, aborting.\n",
1237                                dev->name);
1238                         return err;
1239                 }
1240
1241                 curphy = uec->mii_info->phyinfo;
1242
1243                 if (curphy->config_aneg) {
1244                         err = curphy->config_aneg(uec->mii_info);
1245                         if (err) {
1246                                 printf("%s: Can't negotiate PHY\n", dev->name);
1247                                 return err;
1248                         }
1249                 }
1250
1251                 /* Give PHYs up to 5 sec to report a link */
1252                 i = 50;
1253                 do {
1254                         err = curphy->read_status(uec->mii_info);
1255                         if (!(((i-- > 0) && !uec->mii_info->link) || err))
1256                                 break;
1257                         udelay(100000);
1258                 } while (1);
1259
1260 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1261     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1262                 /* QE12 needs to be released for enabling LBCTL signal*/
1263                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1264 #endif
1265
1266                 if (err || i <= 0)
1267                         printf("warning: %s: timeout on PHY link\n", dev->name);
1268
1269                 adjust_link(dev);
1270                 uec->the_first_run = 1;
1271         }
1272
1273         /* Set up the MAC address */
1274         if (dev->enetaddr[0] & 0x01) {
1275                 printf("%s: MacAddress is multcast address\n",
1276                          __FUNCTION__);
1277                 return -1;
1278         }
1279         uec_set_mac_address(uec, dev->enetaddr);
1280
1281
1282         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1283         if (err) {
1284                 printf("%s: cannot enable UEC device\n", dev->name);
1285                 return -1;
1286         }
1287
1288         phy_change(dev);
1289
1290         return (uec->mii_info->link ? 0 : -1);
1291 }
1292
1293 static void uec_halt(struct eth_device* dev)
1294 {
1295         uec_private_t   *uec = (uec_private_t *)dev->priv;
1296         uec_stop(uec, COMM_DIR_RX_AND_TX);
1297 }
1298
1299 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1300 {
1301         uec_private_t           *uec;
1302         ucc_fast_private_t      *uccf;
1303         volatile qe_bd_t        *bd;
1304         u16                     status;
1305         int                     i;
1306         int                     result = 0;
1307
1308         uec = (uec_private_t *)dev->priv;
1309         uccf = uec->uccf;
1310         bd = uec->txBd;
1311
1312         /* Find an empty TxBD */
1313         for (i = 0; bd->status & TxBD_READY; i++) {
1314                 if (i > 0x100000) {
1315                         printf("%s: tx buffer not ready\n", dev->name);
1316                         return result;
1317                 }
1318         }
1319
1320         /* Init TxBD */
1321         BD_DATA_SET(bd, buf);
1322         BD_LENGTH_SET(bd, len);
1323         status = bd->status;
1324         status &= BD_WRAP;
1325         status |= (TxBD_READY | TxBD_LAST);
1326         BD_STATUS_SET(bd, status);
1327
1328         /* Tell UCC to transmit the buffer */
1329         ucc_fast_transmit_on_demand(uccf);
1330
1331         /* Wait for buffer to be transmitted */
1332         for (i = 0; bd->status & TxBD_READY; i++) {
1333                 if (i > 0x100000) {
1334                         printf("%s: tx error\n", dev->name);
1335                         return result;
1336                 }
1337         }
1338
1339         /* Ok, the buffer be transimitted */
1340         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1341         uec->txBd = bd;
1342         result = 1;
1343
1344         return result;
1345 }
1346
1347 static int uec_recv(struct eth_device* dev)
1348 {
1349         uec_private_t           *uec = dev->priv;
1350         volatile qe_bd_t        *bd;
1351         u16                     status;
1352         u16                     len;
1353         u8                      *data;
1354
1355         bd = uec->rxBd;
1356         status = bd->status;
1357
1358         while (!(status & RxBD_EMPTY)) {
1359                 if (!(status & RxBD_ERROR)) {
1360                         data = BD_DATA(bd);
1361                         len = BD_LENGTH(bd);
1362                         NetReceive(data, len);
1363                 } else {
1364                         printf("%s: Rx error\n", dev->name);
1365                 }
1366                 status &= BD_CLEAN;
1367                 BD_LENGTH_SET(bd, 0);
1368                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1369                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1370                 status = bd->status;
1371         }
1372         uec->rxBd = bd;
1373
1374         return 1;
1375 }
1376
1377 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1378 {
1379         struct eth_device       *dev;
1380         int                     i;
1381         uec_private_t           *uec;
1382         int                     err;
1383
1384         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1385         if (!dev)
1386                 return 0;
1387         memset(dev, 0, sizeof(struct eth_device));
1388
1389         /* Allocate the UEC private struct */
1390         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1391         if (!uec) {
1392                 return -ENOMEM;
1393         }
1394         memset(uec, 0, sizeof(uec_private_t));
1395
1396         /* Adjust uec_info */
1397 #if (MAX_QE_RISC == 4)
1398         uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1399         uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1400 #endif
1401
1402         devlist[uec_info->uf_info.ucc_num] = dev;
1403
1404         uec->uec_info = uec_info;
1405         uec->dev = dev;
1406
1407         sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1408         dev->iobase = 0;
1409         dev->priv = (void *)uec;
1410         dev->init = uec_init;
1411         dev->halt = uec_halt;
1412         dev->send = uec_send;
1413         dev->recv = uec_recv;
1414
1415         /* Clear the ethnet address */
1416         for (i = 0; i < 6; i++)
1417                 dev->enetaddr[i] = 0;
1418
1419         eth_register(dev);
1420
1421         err = uec_startup(uec);
1422         if (err) {
1423                 printf("%s: Cannot configure net device, aborting.",dev->name);
1424                 return err;
1425         }
1426
1427 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1428         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1429 #endif
1430
1431         return 1;
1432 }
1433
1434 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1435 {
1436         int i;
1437
1438         for (i = 0; i < num; i++)
1439                 uec_initialize(bis, &uecs[i]);
1440
1441         return 0;
1442 }
1443
1444 int uec_standard_init(bd_t *bis)
1445 {
1446         return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1447 }