Merge branch 'master' of /home/stefan/git/u-boot/u-boot
[platform/kernel/u-boot.git] / drivers / qe / uec.c
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32 #include "miiphy.h"
33
34 #if defined(CONFIG_QE)
35
36 #ifdef CONFIG_UEC_ETH1
37 static uec_info_t eth1_uec_info = {
38         .uf_info                = {
39                 .ucc_num        = CFG_UEC1_UCC_NUM,
40                 .rx_clock       = CFG_UEC1_RX_CLK,
41                 .tx_clock       = CFG_UEC1_TX_CLK,
42                 .eth_type       = CFG_UEC1_ETH_TYPE,
43         },
44 #if (CFG_UEC1_ETH_TYPE == FAST_ETH)
45         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
46         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
47 #else
48         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
49         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
50 #endif
51         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
52         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
53         .tx_bd_ring_len         = 16,
54         .rx_bd_ring_len         = 16,
55         .phy_address            = CFG_UEC1_PHY_ADDR,
56         .enet_interface         = CFG_UEC1_INTERFACE_MODE,
57 };
58 #endif
59 #ifdef CONFIG_UEC_ETH2
60 static uec_info_t eth2_uec_info = {
61         .uf_info                = {
62                 .ucc_num        = CFG_UEC2_UCC_NUM,
63                 .rx_clock       = CFG_UEC2_RX_CLK,
64                 .tx_clock       = CFG_UEC2_TX_CLK,
65                 .eth_type       = CFG_UEC2_ETH_TYPE,
66         },
67 #if (CFG_UEC2_ETH_TYPE == FAST_ETH)
68         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
69         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
70 #else
71         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
72         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
73 #endif
74         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
75         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
76         .tx_bd_ring_len         = 16,
77         .rx_bd_ring_len         = 16,
78         .phy_address            = CFG_UEC2_PHY_ADDR,
79         .enet_interface         = CFG_UEC2_INTERFACE_MODE,
80 };
81 #endif
82 #ifdef CONFIG_UEC_ETH3
83 static uec_info_t eth3_uec_info = {
84         .uf_info                = {
85                 .ucc_num        = CFG_UEC3_UCC_NUM,
86                 .rx_clock       = CFG_UEC3_RX_CLK,
87                 .tx_clock       = CFG_UEC3_TX_CLK,
88                 .eth_type       = CFG_UEC3_ETH_TYPE,
89         },
90 #if (CFG_UEC3_ETH_TYPE == FAST_ETH)
91         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
92         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
93 #else
94         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
95         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
96 #endif
97         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
98         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
99         .tx_bd_ring_len         = 16,
100         .rx_bd_ring_len         = 16,
101         .phy_address            = CFG_UEC3_PHY_ADDR,
102         .enet_interface         = CFG_UEC3_INTERFACE_MODE,
103 };
104 #endif
105 #ifdef CONFIG_UEC_ETH4
106 static uec_info_t eth4_uec_info = {
107         .uf_info                = {
108                 .ucc_num        = CFG_UEC4_UCC_NUM,
109                 .rx_clock       = CFG_UEC4_RX_CLK,
110                 .tx_clock       = CFG_UEC4_TX_CLK,
111                 .eth_type       = CFG_UEC4_ETH_TYPE,
112         },
113 #if (CFG_UEC4_ETH_TYPE == FAST_ETH)
114         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
115         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
116 #else
117         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
118         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
119 #endif
120         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
121         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
122         .tx_bd_ring_len         = 16,
123         .rx_bd_ring_len         = 16,
124         .phy_address            = CFG_UEC4_PHY_ADDR,
125         .enet_interface         = CFG_UEC4_INTERFACE_MODE,
126 };
127 #endif
128
129 #define MAXCONTROLLERS  (4)
130
131 static struct eth_device *devlist[MAXCONTROLLERS];
132
133 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
134 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
135
136 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
137 {
138         uec_t           *uec_regs;
139         u32             maccfg1;
140
141         if (!uec) {
142                 printf("%s: uec not initial\n", __FUNCTION__);
143                 return -EINVAL;
144         }
145         uec_regs = uec->uec_regs;
146
147         maccfg1 = in_be32(&uec_regs->maccfg1);
148
149         if (mode & COMM_DIR_TX) {
150                 maccfg1 |= MACCFG1_ENABLE_TX;
151                 out_be32(&uec_regs->maccfg1, maccfg1);
152                 uec->mac_tx_enabled = 1;
153         }
154
155         if (mode & COMM_DIR_RX) {
156                 maccfg1 |= MACCFG1_ENABLE_RX;
157                 out_be32(&uec_regs->maccfg1, maccfg1);
158                 uec->mac_rx_enabled = 1;
159         }
160
161         return 0;
162 }
163
164 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
165 {
166         uec_t           *uec_regs;
167         u32             maccfg1;
168
169         if (!uec) {
170                 printf("%s: uec not initial\n", __FUNCTION__);
171                 return -EINVAL;
172         }
173         uec_regs = uec->uec_regs;
174
175         maccfg1 = in_be32(&uec_regs->maccfg1);
176
177         if (mode & COMM_DIR_TX) {
178                 maccfg1 &= ~MACCFG1_ENABLE_TX;
179                 out_be32(&uec_regs->maccfg1, maccfg1);
180                 uec->mac_tx_enabled = 0;
181         }
182
183         if (mode & COMM_DIR_RX) {
184                 maccfg1 &= ~MACCFG1_ENABLE_RX;
185                 out_be32(&uec_regs->maccfg1, maccfg1);
186                 uec->mac_rx_enabled = 0;
187         }
188
189         return 0;
190 }
191
192 static int uec_graceful_stop_tx(uec_private_t *uec)
193 {
194         ucc_fast_t              *uf_regs;
195         u32                     cecr_subblock;
196         u32                     ucce;
197
198         if (!uec || !uec->uccf) {
199                 printf("%s: No handle passed.\n", __FUNCTION__);
200                 return -EINVAL;
201         }
202
203         uf_regs = uec->uccf->uf_regs;
204
205         /* Clear the grace stop event */
206         out_be32(&uf_regs->ucce, UCCE_GRA);
207
208         /* Issue host command */
209         cecr_subblock =
210                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
211         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
212                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
213
214         /* Wait for command to complete */
215         do {
216                 ucce = in_be32(&uf_regs->ucce);
217         } while (! (ucce & UCCE_GRA));
218
219         uec->grace_stopped_tx = 1;
220
221         return 0;
222 }
223
224 static int uec_graceful_stop_rx(uec_private_t *uec)
225 {
226         u32             cecr_subblock;
227         u8              ack;
228
229         if (!uec) {
230                 printf("%s: No handle passed.\n", __FUNCTION__);
231                 return -EINVAL;
232         }
233
234         if (!uec->p_rx_glbl_pram) {
235                 printf("%s: No init rx global parameter\n", __FUNCTION__);
236                 return -EINVAL;
237         }
238
239         /* Clear acknowledge bit */
240         ack = uec->p_rx_glbl_pram->rxgstpack;
241         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
242         uec->p_rx_glbl_pram->rxgstpack = ack;
243
244         /* Keep issuing cmd and checking ack bit until it is asserted */
245         do {
246                 /* Issue host command */
247                 cecr_subblock =
248                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
249                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
250                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
251                 ack = uec->p_rx_glbl_pram->rxgstpack;
252         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
253
254         uec->grace_stopped_rx = 1;
255
256         return 0;
257 }
258
259 static int uec_restart_tx(uec_private_t *uec)
260 {
261         u32             cecr_subblock;
262
263         if (!uec || !uec->uec_info) {
264                 printf("%s: No handle passed.\n", __FUNCTION__);
265                 return -EINVAL;
266         }
267
268         cecr_subblock =
269          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
270         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
271                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
272
273         uec->grace_stopped_tx = 0;
274
275         return 0;
276 }
277
278 static int uec_restart_rx(uec_private_t *uec)
279 {
280         u32             cecr_subblock;
281
282         if (!uec || !uec->uec_info) {
283                 printf("%s: No handle passed.\n", __FUNCTION__);
284                 return -EINVAL;
285         }
286
287         cecr_subblock =
288          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
289         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
290                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
291
292         uec->grace_stopped_rx = 0;
293
294         return 0;
295 }
296
297 static int uec_open(uec_private_t *uec, comm_dir_e mode)
298 {
299         ucc_fast_private_t      *uccf;
300
301         if (!uec || !uec->uccf) {
302                 printf("%s: No handle passed.\n", __FUNCTION__);
303                 return -EINVAL;
304         }
305         uccf = uec->uccf;
306
307         /* check if the UCC number is in range. */
308         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
309                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
310                 return -EINVAL;
311         }
312
313         /* Enable MAC */
314         uec_mac_enable(uec, mode);
315
316         /* Enable UCC fast */
317         ucc_fast_enable(uccf, mode);
318
319         /* RISC microcode start */
320         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
321                 uec_restart_tx(uec);
322         }
323         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
324                 uec_restart_rx(uec);
325         }
326
327         return 0;
328 }
329
330 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
331 {
332         ucc_fast_private_t      *uccf;
333
334         if (!uec || !uec->uccf) {
335                 printf("%s: No handle passed.\n", __FUNCTION__);
336                 return -EINVAL;
337         }
338         uccf = uec->uccf;
339
340         /* check if the UCC number is in range. */
341         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
342                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
343                 return -EINVAL;
344         }
345         /* Stop any transmissions */
346         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
347                 uec_graceful_stop_tx(uec);
348         }
349         /* Stop any receptions */
350         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
351                 uec_graceful_stop_rx(uec);
352         }
353
354         /* Disable the UCC fast */
355         ucc_fast_disable(uec->uccf, mode);
356
357         /* Disable the MAC */
358         uec_mac_disable(uec, mode);
359
360         return 0;
361 }
362
363 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
364 {
365         uec_t           *uec_regs;
366         u32             maccfg2;
367
368         if (!uec) {
369                 printf("%s: uec not initial\n", __FUNCTION__);
370                 return -EINVAL;
371         }
372         uec_regs = uec->uec_regs;
373
374         if (duplex == DUPLEX_HALF) {
375                 maccfg2 = in_be32(&uec_regs->maccfg2);
376                 maccfg2 &= ~MACCFG2_FDX;
377                 out_be32(&uec_regs->maccfg2, maccfg2);
378         }
379
380         if (duplex == DUPLEX_FULL) {
381                 maccfg2 = in_be32(&uec_regs->maccfg2);
382                 maccfg2 |= MACCFG2_FDX;
383                 out_be32(&uec_regs->maccfg2, maccfg2);
384         }
385
386         return 0;
387 }
388
389 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
390 {
391         enet_interface_e        enet_if_mode;
392         uec_info_t              *uec_info;
393         uec_t                   *uec_regs;
394         u32                     upsmr;
395         u32                     maccfg2;
396
397         if (!uec) {
398                 printf("%s: uec not initial\n", __FUNCTION__);
399                 return -EINVAL;
400         }
401
402         uec_info = uec->uec_info;
403         uec_regs = uec->uec_regs;
404         enet_if_mode = if_mode;
405
406         maccfg2 = in_be32(&uec_regs->maccfg2);
407         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
408
409         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
410         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
411
412         switch (enet_if_mode) {
413                 case ENET_100_MII:
414                 case ENET_10_MII:
415                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
416                         break;
417                 case ENET_1000_GMII:
418                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
419                         break;
420                 case ENET_1000_TBI:
421                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
422                         upsmr |= UPSMR_TBIM;
423                         break;
424                 case ENET_1000_RTBI:
425                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
426                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
427                         break;
428                 case ENET_1000_RGMII_RXID:
429                 case ENET_1000_RGMII:
430                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
431                         upsmr |= UPSMR_RPM;
432                         break;
433                 case ENET_100_RGMII:
434                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
435                         upsmr |= UPSMR_RPM;
436                         break;
437                 case ENET_10_RGMII:
438                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
439                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
440                         break;
441                 case ENET_100_RMII:
442                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
443                         upsmr |= UPSMR_RMM;
444                         break;
445                 case ENET_10_RMII:
446                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
447                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
448                         break;
449                 default:
450                         return -EINVAL;
451                         break;
452         }
453         out_be32(&uec_regs->maccfg2, maccfg2);
454         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
455
456         return 0;
457 }
458
459 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
460 {
461         uint            timeout = 0x1000;
462         u32             miimcfg = 0;
463
464         miimcfg = in_be32(&uec_mii_regs->miimcfg);
465         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
466         out_be32(&uec_mii_regs->miimcfg, miimcfg);
467
468         /* Wait until the bus is free */
469         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
470         if (timeout <= 0) {
471                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
472                 return -ETIMEDOUT;
473         }
474
475         return 0;
476 }
477
478 static int init_phy(struct eth_device *dev)
479 {
480         uec_private_t           *uec;
481         uec_mii_t               *umii_regs;
482         struct uec_mii_info     *mii_info;
483         struct phy_info         *curphy;
484         int                     err;
485
486         uec = (uec_private_t *)dev->priv;
487         umii_regs = uec->uec_mii_regs;
488
489         uec->oldlink = 0;
490         uec->oldspeed = 0;
491         uec->oldduplex = -1;
492
493         mii_info = malloc(sizeof(*mii_info));
494         if (!mii_info) {
495                 printf("%s: Could not allocate mii_info", dev->name);
496                 return -ENOMEM;
497         }
498         memset(mii_info, 0, sizeof(*mii_info));
499
500         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
501                 mii_info->speed = SPEED_1000;
502         } else {
503                 mii_info->speed = SPEED_100;
504         }
505
506         mii_info->duplex = DUPLEX_FULL;
507         mii_info->pause = 0;
508         mii_info->link = 1;
509
510         mii_info->advertising = (ADVERTISED_10baseT_Half |
511                                 ADVERTISED_10baseT_Full |
512                                 ADVERTISED_100baseT_Half |
513                                 ADVERTISED_100baseT_Full |
514                                 ADVERTISED_1000baseT_Full);
515         mii_info->autoneg = 1;
516         mii_info->mii_id = uec->uec_info->phy_address;
517         mii_info->dev = dev;
518
519         mii_info->mdio_read = &uec_read_phy_reg;
520         mii_info->mdio_write = &uec_write_phy_reg;
521
522         uec->mii_info = mii_info;
523
524         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
525
526         if (init_mii_management_configuration(umii_regs)) {
527                 printf("%s: The MII Bus is stuck!", dev->name);
528                 err = -1;
529                 goto bus_fail;
530         }
531
532         /* get info for this PHY */
533         curphy = uec_get_phy_info(uec->mii_info);
534         if (!curphy) {
535                 printf("%s: No PHY found", dev->name);
536                 err = -1;
537                 goto no_phy;
538         }
539
540         mii_info->phyinfo = curphy;
541
542         /* Run the commands which initialize the PHY */
543         if (curphy->init) {
544                 err = curphy->init(uec->mii_info);
545                 if (err)
546                         goto phy_init_fail;
547         }
548
549         return 0;
550
551 phy_init_fail:
552 no_phy:
553 bus_fail:
554         free(mii_info);
555         return err;
556 }
557
558 static void adjust_link(struct eth_device *dev)
559 {
560         uec_private_t           *uec = (uec_private_t *)dev->priv;
561         uec_t                   *uec_regs;
562         struct uec_mii_info     *mii_info = uec->mii_info;
563
564         extern void change_phy_interface_mode(struct eth_device *dev,
565                                          enet_interface_e mode);
566         uec_regs = uec->uec_regs;
567
568         if (mii_info->link) {
569                 /* Now we make sure that we can be in full duplex mode.
570                 * If not, we operate in half-duplex mode. */
571                 if (mii_info->duplex != uec->oldduplex) {
572                         if (!(mii_info->duplex)) {
573                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
574                                 printf("%s: Half Duplex\n", dev->name);
575                         } else {
576                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
577                                 printf("%s: Full Duplex\n", dev->name);
578                         }
579                         uec->oldduplex = mii_info->duplex;
580                 }
581
582                 if (mii_info->speed != uec->oldspeed) {
583                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
584                                 switch (mii_info->speed) {
585                                 case 1000:
586                                         break;
587                                 case 100:
588                                         printf ("switching to rgmii 100\n");
589                                         /* change phy to rgmii 100 */
590                                         change_phy_interface_mode(dev,
591                                                                 ENET_100_RGMII);
592                                         /* change the MAC interface mode */
593                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
594                                         break;
595                                 case 10:
596                                         printf ("switching to rgmii 10\n");
597                                         /* change phy to rgmii 10 */
598                                         change_phy_interface_mode(dev,
599                                                                 ENET_10_RGMII);
600                                         /* change the MAC interface mode */
601                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
602                                         break;
603                                 default:
604                                         printf("%s: Ack,Speed(%d)is illegal\n",
605                                                 dev->name, mii_info->speed);
606                                         break;
607                                 }
608                         }
609
610                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
611                         uec->oldspeed = mii_info->speed;
612                 }
613
614                 if (!uec->oldlink) {
615                         printf("%s: Link is up\n", dev->name);
616                         uec->oldlink = 1;
617                 }
618
619         } else { /* if (mii_info->link) */
620                 if (uec->oldlink) {
621                         printf("%s: Link is down\n", dev->name);
622                         uec->oldlink = 0;
623                         uec->oldspeed = 0;
624                         uec->oldduplex = -1;
625                 }
626         }
627 }
628
629 static void phy_change(struct eth_device *dev)
630 {
631         uec_private_t   *uec = (uec_private_t *)dev->priv;
632
633         /* Update the link, speed, duplex */
634         uec->mii_info->phyinfo->read_status(uec->mii_info);
635
636         /* Adjust the interface according to speed */
637         adjust_link(dev);
638 }
639
640 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
641         && !defined(BITBANGMII)
642
643 /*
644  * Read a MII PHY register.
645  *
646  * Returns:
647  *  0 on success
648  */
649 static int uec_miiphy_read(char *devname, unsigned char addr,
650                             unsigned char reg, unsigned short *value)
651 {
652         *value = uec_read_phy_reg(devlist[0], addr, reg);
653
654         return 0;
655 }
656
657 /*
658  * Write a MII PHY register.
659  *
660  * Returns:
661  *  0 on success
662  */
663 static int uec_miiphy_write(char *devname, unsigned char addr,
664                              unsigned char reg, unsigned short value)
665 {
666         uec_write_phy_reg(devlist[0], addr, reg, value);
667
668         return 0;
669 }
670
671 #endif
672
673 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
674 {
675         uec_t           *uec_regs;
676         u32             mac_addr1;
677         u32             mac_addr2;
678
679         if (!uec) {
680                 printf("%s: uec not initial\n", __FUNCTION__);
681                 return -EINVAL;
682         }
683
684         uec_regs = uec->uec_regs;
685
686         /* if a station address of 0x12345678ABCD, perform a write to
687         MACSTNADDR1 of 0xCDAB7856,
688         MACSTNADDR2 of 0x34120000 */
689
690         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
691                         (mac_addr[3] << 8)  | (mac_addr[2]);
692         out_be32(&uec_regs->macstnaddr1, mac_addr1);
693
694         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
695         out_be32(&uec_regs->macstnaddr2, mac_addr2);
696
697         return 0;
698 }
699
700 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
701                                          int *threads_num_ret)
702 {
703         int     num_threads_numerica;
704
705         switch (threads_num) {
706                 case UEC_NUM_OF_THREADS_1:
707                         num_threads_numerica = 1;
708                         break;
709                 case UEC_NUM_OF_THREADS_2:
710                         num_threads_numerica = 2;
711                         break;
712                 case UEC_NUM_OF_THREADS_4:
713                         num_threads_numerica = 4;
714                         break;
715                 case UEC_NUM_OF_THREADS_6:
716                         num_threads_numerica = 6;
717                         break;
718                 case UEC_NUM_OF_THREADS_8:
719                         num_threads_numerica = 8;
720                         break;
721                 default:
722                         printf("%s: Bad number of threads value.",
723                                  __FUNCTION__);
724                         return -EINVAL;
725         }
726
727         *threads_num_ret = num_threads_numerica;
728
729         return 0;
730 }
731
732 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
733 {
734         uec_info_t      *uec_info;
735         u32             end_bd;
736         u8              bmrx = 0;
737         int             i;
738
739         uec_info = uec->uec_info;
740
741         /* Alloc global Tx parameter RAM page */
742         uec->tx_glbl_pram_offset = qe_muram_alloc(
743                                 sizeof(uec_tx_global_pram_t),
744                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
745         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
746                                 qe_muram_addr(uec->tx_glbl_pram_offset);
747
748         /* Zero the global Tx prameter RAM */
749         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
750
751         /* Init global Tx parameter RAM */
752
753         /* TEMODER, RMON statistics disable, one Tx queue */
754         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
755
756         /* SQPTR */
757         uec->send_q_mem_reg_offset = qe_muram_alloc(
758                                 sizeof(uec_send_queue_qd_t),
759                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
760         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
761                                 qe_muram_addr(uec->send_q_mem_reg_offset);
762         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
763
764         /* Setup the table with TxBDs ring */
765         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
766                                          * SIZEOFBD;
767         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
768                                  (u32)(uec->p_tx_bd_ring));
769         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
770                                                  end_bd);
771
772         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
773         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
774
775         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
776         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
777
778         /* TSTATE, global snooping, big endian, the CSB bus selected */
779         bmrx = BMR_INIT_VALUE;
780         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
781
782         /* IPH_Offset */
783         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
784                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
785         }
786
787         /* VTAG table */
788         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
789                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
790         }
791
792         /* TQPTR */
793         uec->thread_dat_tx_offset = qe_muram_alloc(
794                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
795                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
796
797         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
798                                 qe_muram_addr(uec->thread_dat_tx_offset);
799         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
800 }
801
802 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
803 {
804         u8      bmrx = 0;
805         int     i;
806         uec_82xx_address_filtering_pram_t       *p_af_pram;
807
808         /* Allocate global Rx parameter RAM page */
809         uec->rx_glbl_pram_offset = qe_muram_alloc(
810                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
811         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
812                                 qe_muram_addr(uec->rx_glbl_pram_offset);
813
814         /* Zero Global Rx parameter RAM */
815         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
816
817         /* Init global Rx parameter RAM */
818         /* REMODER, Extended feature mode disable, VLAN disable,
819          LossLess flow control disable, Receive firmware statisic disable,
820          Extended address parsing mode disable, One Rx queues,
821          Dynamic maximum/minimum frame length disable, IP checksum check
822          disable, IP address alignment disable
823         */
824         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
825
826         /* RQPTR */
827         uec->thread_dat_rx_offset = qe_muram_alloc(
828                         num_threads_rx * sizeof(uec_thread_data_rx_t),
829                          UEC_THREAD_DATA_ALIGNMENT);
830         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
831                                 qe_muram_addr(uec->thread_dat_rx_offset);
832         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
833
834         /* Type_or_Len */
835         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
836
837         /* RxRMON base pointer, we don't need it */
838         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
839
840         /* IntCoalescingPTR, we don't need it, no interrupt */
841         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
842
843         /* RSTATE, global snooping, big endian, the CSB bus selected */
844         bmrx = BMR_INIT_VALUE;
845         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
846
847         /* MRBLR */
848         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
849
850         /* RBDQPTR */
851         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
852                                 sizeof(uec_rx_bd_queues_entry_t) + \
853                                 sizeof(uec_rx_prefetched_bds_t),
854                                  UEC_RX_BD_QUEUES_ALIGNMENT);
855         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
856                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
857
858         /* Zero it */
859         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
860                                         sizeof(uec_rx_prefetched_bds_t));
861         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
862         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
863                  (u32)uec->p_rx_bd_ring);
864
865         /* MFLR */
866         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
867         /* MINFLR */
868         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
869         /* MAXD1 */
870         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
871         /* MAXD2 */
872         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
873         /* ECAM_PTR */
874         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
875         /* L2QT */
876         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
877         /* L3QT */
878         for (i = 0; i < 8; i++) {
879                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
880         }
881
882         /* VLAN_TYPE */
883         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
884         /* TCI */
885         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
886
887         /* Clear PQ2 style address filtering hash table */
888         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
889                         uec->p_rx_glbl_pram->addressfiltering;
890
891         p_af_pram->iaddr_h = 0;
892         p_af_pram->iaddr_l = 0;
893         p_af_pram->gaddr_h = 0;
894         p_af_pram->gaddr_l = 0;
895 }
896
897 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
898                                          int thread_tx, int thread_rx)
899 {
900         uec_init_cmd_pram_t             *p_init_enet_param;
901         u32                             init_enet_param_offset;
902         uec_info_t                      *uec_info;
903         int                             i;
904         int                             snum;
905         u32                             init_enet_offset;
906         u32                             entry_val;
907         u32                             command;
908         u32                             cecr_subblock;
909
910         uec_info = uec->uec_info;
911
912         /* Allocate init enet command parameter */
913         uec->init_enet_param_offset = qe_muram_alloc(
914                                         sizeof(uec_init_cmd_pram_t), 4);
915         init_enet_param_offset = uec->init_enet_param_offset;
916         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
917                                 qe_muram_addr(uec->init_enet_param_offset);
918
919         /* Zero init enet command struct */
920         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
921
922         /* Init the command struct */
923         p_init_enet_param = uec->p_init_enet_param;
924         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
925         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
926         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
927         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
928         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
929         p_init_enet_param->largestexternallookupkeysize = 0;
930
931         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
932                                          << ENET_INIT_PARAM_RGF_SHIFT;
933         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
934                                          << ENET_INIT_PARAM_TGF_SHIFT;
935
936         /* Init Rx global parameter pointer */
937         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
938                                                  (u32)uec_info->riscRx;
939
940         /* Init Rx threads */
941         for (i = 0; i < (thread_rx + 1); i++) {
942                 if ((snum = qe_get_snum()) < 0) {
943                         printf("%s can not get snum\n", __FUNCTION__);
944                         return -ENOMEM;
945                 }
946
947                 if (i==0) {
948                         init_enet_offset = 0;
949                 } else {
950                         init_enet_offset = qe_muram_alloc(
951                                         sizeof(uec_thread_rx_pram_t),
952                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
953                 }
954
955                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
956                                  init_enet_offset | (u32)uec_info->riscRx;
957                 p_init_enet_param->rxthread[i] = entry_val;
958         }
959
960         /* Init Tx global parameter pointer */
961         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
962                                          (u32)uec_info->riscTx;
963
964         /* Init Tx threads */
965         for (i = 0; i < thread_tx; i++) {
966                 if ((snum = qe_get_snum()) < 0) {
967                         printf("%s can not get snum\n", __FUNCTION__);
968                         return -ENOMEM;
969                 }
970
971                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
972                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
973
974                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
975                                  init_enet_offset | (u32)uec_info->riscTx;
976                 p_init_enet_param->txthread[i] = entry_val;
977         }
978
979         __asm__ __volatile__("sync");
980
981         /* Issue QE command */
982         command = QE_INIT_TX_RX;
983         cecr_subblock = ucc_fast_get_qe_cr_subblock(
984                                 uec->uec_info->uf_info.ucc_num);
985         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
986                                                  init_enet_param_offset);
987
988         return 0;
989 }
990
991 static int uec_startup(uec_private_t *uec)
992 {
993         uec_info_t                      *uec_info;
994         ucc_fast_info_t                 *uf_info;
995         ucc_fast_private_t              *uccf;
996         ucc_fast_t                      *uf_regs;
997         uec_t                           *uec_regs;
998         int                             num_threads_tx;
999         int                             num_threads_rx;
1000         u32                             utbipar;
1001         enet_interface_e                enet_interface;
1002         u32                             length;
1003         u32                             align;
1004         qe_bd_t                         *bd;
1005         u8                              *buf;
1006         int                             i;
1007
1008         if (!uec || !uec->uec_info) {
1009                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1010                 return -EINVAL;
1011         }
1012
1013         uec_info = uec->uec_info;
1014         uf_info = &(uec_info->uf_info);
1015
1016         /* Check if Rx BD ring len is illegal */
1017         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1018                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1019                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1020                          __FUNCTION__);
1021                 return -EINVAL;
1022         }
1023
1024         /* Check if Tx BD ring len is illegal */
1025         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1026                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1027                          __FUNCTION__);
1028                 return -EINVAL;
1029         }
1030
1031         /* Check if MRBLR is illegal */
1032         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1033                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1034                          __FUNCTION__);
1035                 return -EINVAL;
1036         }
1037
1038         /* Both Rx and Tx are stopped */
1039         uec->grace_stopped_rx = 1;
1040         uec->grace_stopped_tx = 1;
1041
1042         /* Init UCC fast */
1043         if (ucc_fast_init(uf_info, &uccf)) {
1044                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1045                 return -ENOMEM;
1046         }
1047
1048         /* Save uccf */
1049         uec->uccf = uccf;
1050
1051         /* Convert the Tx threads number */
1052         if (uec_convert_threads_num(uec_info->num_threads_tx,
1053                                          &num_threads_tx)) {
1054                 return -EINVAL;
1055         }
1056
1057         /* Convert the Rx threads number */
1058         if (uec_convert_threads_num(uec_info->num_threads_rx,
1059                                          &num_threads_rx)) {
1060                 return -EINVAL;
1061         }
1062
1063         uf_regs = uccf->uf_regs;
1064
1065         /* UEC register is following UCC fast registers */
1066         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1067
1068         /* Save the UEC register pointer to UEC private struct */
1069         uec->uec_regs = uec_regs;
1070
1071         /* Init UPSMR, enable hardware statistics (UCC) */
1072         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1073
1074         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1075         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1076
1077         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1078         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1079
1080         /* Setup MAC interface mode */
1081         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1082
1083         /* Setup MII management base */
1084 #ifndef CONFIG_eTSEC_MDIO_BUS
1085         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1086 #else
1087         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1088 #endif
1089
1090         /* Setup MII master clock source */
1091         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1092
1093         /* Setup UTBIPAR */
1094         utbipar = in_be32(&uec_regs->utbipar);
1095         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1096         enet_interface = uec->uec_info->enet_interface;
1097         if (enet_interface == ENET_1000_TBI ||
1098                  enet_interface == ENET_1000_RTBI) {
1099                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1100                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1101         } else {
1102                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1103                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1104         }
1105
1106         out_be32(&uec_regs->utbipar, utbipar);
1107
1108         /* Allocate Tx BDs */
1109         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1110                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1111                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1112         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1113                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1114                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1115         }
1116
1117         align = UEC_TX_BD_RING_ALIGNMENT;
1118         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1119         if (uec->tx_bd_ring_offset != 0) {
1120                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1121                                                  & ~(align - 1));
1122         }
1123
1124         /* Zero all of Tx BDs */
1125         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1126
1127         /* Allocate Rx BDs */
1128         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1129         align = UEC_RX_BD_RING_ALIGNMENT;
1130         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1131         if (uec->rx_bd_ring_offset != 0) {
1132                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1133                                                          & ~(align - 1));
1134         }
1135
1136         /* Zero all of Rx BDs */
1137         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1138
1139         /* Allocate Rx buffer */
1140         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1141         align = UEC_RX_DATA_BUF_ALIGNMENT;
1142         uec->rx_buf_offset = (u32)malloc(length + align);
1143         if (uec->rx_buf_offset != 0) {
1144                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1145                                                  & ~(align - 1));
1146         }
1147
1148         /* Zero all of the Rx buffer */
1149         memset((void *)(uec->rx_buf_offset), 0, length + align);
1150
1151         /* Init TxBD ring */
1152         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1153         uec->txBd = bd;
1154
1155         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1156                 BD_DATA_CLEAR(bd);
1157                 BD_STATUS_SET(bd, 0);
1158                 BD_LENGTH_SET(bd, 0);
1159                 bd ++;
1160         }
1161         BD_STATUS_SET((--bd), TxBD_WRAP);
1162
1163         /* Init RxBD ring */
1164         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1165         uec->rxBd = bd;
1166         buf = uec->p_rx_buf;
1167         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1168                 BD_DATA_SET(bd, buf);
1169                 BD_LENGTH_SET(bd, 0);
1170                 BD_STATUS_SET(bd, RxBD_EMPTY);
1171                 buf += MAX_RXBUF_LEN;
1172                 bd ++;
1173         }
1174         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1175
1176         /* Init global Tx parameter RAM */
1177         uec_init_tx_parameter(uec, num_threads_tx);
1178
1179         /* Init global Rx parameter RAM */
1180         uec_init_rx_parameter(uec, num_threads_rx);
1181
1182         /* Init ethernet Tx and Rx parameter command */
1183         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1184                                          num_threads_rx)) {
1185                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1186                 return -ENOMEM;
1187         }
1188
1189         return 0;
1190 }
1191
1192 static int uec_init(struct eth_device* dev, bd_t *bd)
1193 {
1194         uec_private_t           *uec;
1195         int                     err, i;
1196         struct phy_info         *curphy;
1197
1198         uec = (uec_private_t *)dev->priv;
1199
1200         if (uec->the_first_run == 0) {
1201                 err = init_phy(dev);
1202                 if (err) {
1203                         printf("%s: Cannot initialize PHY, aborting.\n",
1204                                dev->name);
1205                         return err;
1206                 }
1207
1208                 curphy = uec->mii_info->phyinfo;
1209
1210                 if (curphy->config_aneg) {
1211                         err = curphy->config_aneg(uec->mii_info);
1212                         if (err) {
1213                                 printf("%s: Can't negotiate PHY\n", dev->name);
1214                                 return err;
1215                         }
1216                 }
1217
1218                 /* Give PHYs up to 5 sec to report a link */
1219                 i = 50;
1220                 do {
1221                         err = curphy->read_status(uec->mii_info);
1222                         udelay(100000);
1223                 } while (((i-- > 0) && !uec->mii_info->link) || err);
1224
1225                 if (err || i <= 0)
1226                         printf("warning: %s: timeout on PHY link\n", dev->name);
1227
1228                 uec->the_first_run = 1;
1229         }
1230
1231         /* Set up the MAC address */
1232         if (dev->enetaddr[0] & 0x01) {
1233                 printf("%s: MacAddress is multcast address\n",
1234                          __FUNCTION__);
1235                 return -1;
1236         }
1237         uec_set_mac_address(uec, dev->enetaddr);
1238
1239
1240         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1241         if (err) {
1242                 printf("%s: cannot enable UEC device\n", dev->name);
1243                 return -1;
1244         }
1245
1246         phy_change(dev);
1247
1248         return (uec->mii_info->link ? 0 : -1);
1249 }
1250
1251 static void uec_halt(struct eth_device* dev)
1252 {
1253         uec_private_t   *uec = (uec_private_t *)dev->priv;
1254         uec_stop(uec, COMM_DIR_RX_AND_TX);
1255 }
1256
1257 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1258 {
1259         uec_private_t           *uec;
1260         ucc_fast_private_t      *uccf;
1261         volatile qe_bd_t        *bd;
1262         u16                     status;
1263         int                     i;
1264         int                     result = 0;
1265
1266         uec = (uec_private_t *)dev->priv;
1267         uccf = uec->uccf;
1268         bd = uec->txBd;
1269
1270         /* Find an empty TxBD */
1271         for (i = 0; bd->status & TxBD_READY; i++) {
1272                 if (i > 0x100000) {
1273                         printf("%s: tx buffer not ready\n", dev->name);
1274                         return result;
1275                 }
1276         }
1277
1278         /* Init TxBD */
1279         BD_DATA_SET(bd, buf);
1280         BD_LENGTH_SET(bd, len);
1281         status = bd->status;
1282         status &= BD_WRAP;
1283         status |= (TxBD_READY | TxBD_LAST);
1284         BD_STATUS_SET(bd, status);
1285
1286         /* Tell UCC to transmit the buffer */
1287         ucc_fast_transmit_on_demand(uccf);
1288
1289         /* Wait for buffer to be transmitted */
1290         for (i = 0; bd->status & TxBD_READY; i++) {
1291                 if (i > 0x100000) {
1292                         printf("%s: tx error\n", dev->name);
1293                         return result;
1294                 }
1295         }
1296
1297         /* Ok, the buffer be transimitted */
1298         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1299         uec->txBd = bd;
1300         result = 1;
1301
1302         return result;
1303 }
1304
1305 static int uec_recv(struct eth_device* dev)
1306 {
1307         uec_private_t           *uec = dev->priv;
1308         volatile qe_bd_t        *bd;
1309         u16                     status;
1310         u16                     len;
1311         u8                      *data;
1312
1313         bd = uec->rxBd;
1314         status = bd->status;
1315
1316         while (!(status & RxBD_EMPTY)) {
1317                 if (!(status & RxBD_ERROR)) {
1318                         data = BD_DATA(bd);
1319                         len = BD_LENGTH(bd);
1320                         NetReceive(data, len);
1321                 } else {
1322                         printf("%s: Rx error\n", dev->name);
1323                 }
1324                 status &= BD_CLEAN;
1325                 BD_LENGTH_SET(bd, 0);
1326                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1327                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1328                 status = bd->status;
1329         }
1330         uec->rxBd = bd;
1331
1332         return 1;
1333 }
1334
1335 int uec_initialize(int index)
1336 {
1337         struct eth_device       *dev;
1338         int                     i;
1339         uec_private_t           *uec;
1340         uec_info_t              *uec_info;
1341         int                     err;
1342
1343         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1344         if (!dev)
1345                 return 0;
1346         memset(dev, 0, sizeof(struct eth_device));
1347
1348         /* Allocate the UEC private struct */
1349         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1350         if (!uec) {
1351                 return -ENOMEM;
1352         }
1353         memset(uec, 0, sizeof(uec_private_t));
1354
1355         /* Init UEC private struct, they come from board.h */
1356         uec_info = NULL;
1357         if (index == 0) {
1358 #ifdef CONFIG_UEC_ETH1
1359                 uec_info = &eth1_uec_info;
1360 #endif
1361         } else if (index == 1) {
1362 #ifdef CONFIG_UEC_ETH2
1363                 uec_info = &eth2_uec_info;
1364 #endif
1365         } else if (index == 2) {
1366 #ifdef CONFIG_UEC_ETH3
1367                 uec_info = &eth3_uec_info;
1368 #endif
1369         } else if (index == 3) {
1370 #ifdef CONFIG_UEC_ETH4
1371                 uec_info = &eth4_uec_info;
1372 #endif
1373         } else {
1374                 printf("%s: index is illegal.\n", __FUNCTION__);
1375                 return -EINVAL;
1376         }
1377
1378         devlist[index] = dev;
1379
1380         uec->uec_info = uec_info;
1381
1382         sprintf(dev->name, "FSL UEC%d", index);
1383         dev->iobase = 0;
1384         dev->priv = (void *)uec;
1385         dev->init = uec_init;
1386         dev->halt = uec_halt;
1387         dev->send = uec_send;
1388         dev->recv = uec_recv;
1389
1390         /* Clear the ethnet address */
1391         for (i = 0; i < 6; i++)
1392                 dev->enetaddr[i] = 0;
1393
1394         eth_register(dev);
1395
1396         err = uec_startup(uec);
1397         if (err) {
1398                 printf("%s: Cannot configure net device, aborting.",dev->name);
1399                 return err;
1400         }
1401
1402 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1403         && !defined(BITBANGMII)
1404         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1405 #endif
1406
1407         return 1;
1408 }
1409
1410
1411 #endif /* CONFIG_QE */