drivers/qe/uec.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "common.h"
  23 #include "net.h"
  24 #include "malloc.h"
  25 #include "asm/errno.h"
  26 #include "asm/io.h"
  27 #include "asm/immap_qe.h"
  28 #include "qe.h"
  29 #include "uccf.h"
  30 #include "uec.h"
  31 #include "uec_phy.h"
  32 #include "miiphy.h"
  33
  34 #if defined(CONFIG_QE)
  35
  36 #ifdef CONFIG_UEC_ETH1
  37 static uec_info_t eth1_uec_info = {
  38         .uf_info                = {
  39                 .ucc_num        = CFG_UEC1_UCC_NUM,
  40                 .rx_clock       = CFG_UEC1_RX_CLK,
  41                 .tx_clock       = CFG_UEC1_TX_CLK,
  42                 .eth_type       = CFG_UEC1_ETH_TYPE,
  43         },
  44 #if (CFG_UEC1_ETH_TYPE == FAST_ETH)
  45         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  46         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  47 #else
  48         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  49         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  50 #endif
  51         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  52         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  53         .tx_bd_ring_len         = 16,
  54         .rx_bd_ring_len         = 16,
  55         .phy_address            = CFG_UEC1_PHY_ADDR,
  56         .enet_interface         = CFG_UEC1_INTERFACE_MODE,
  57 };
  58 #endif
  59 #ifdef CONFIG_UEC_ETH2
  60 static uec_info_t eth2_uec_info = {
  61         .uf_info                = {
  62                 .ucc_num        = CFG_UEC2_UCC_NUM,
  63                 .rx_clock       = CFG_UEC2_RX_CLK,
  64                 .tx_clock       = CFG_UEC2_TX_CLK,
  65                 .eth_type       = CFG_UEC2_ETH_TYPE,
  66         },
  67 #if (CFG_UEC2_ETH_TYPE == FAST_ETH)
  68         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  69         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  70 #else
  71         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  72         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  73 #endif
  74         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  75         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  76         .tx_bd_ring_len         = 16,
  77         .rx_bd_ring_len         = 16,
  78         .phy_address            = CFG_UEC2_PHY_ADDR,
  79         .enet_interface         = CFG_UEC2_INTERFACE_MODE,
  80 };
  81 #endif
  82 #ifdef CONFIG_UEC_ETH3
  83 static uec_info_t eth3_uec_info = {
  84         .uf_info                = {
  85                 .ucc_num        = CFG_UEC3_UCC_NUM,
  86                 .rx_clock       = CFG_UEC3_RX_CLK,
  87                 .tx_clock       = CFG_UEC3_TX_CLK,
  88                 .eth_type       = CFG_UEC3_ETH_TYPE,
  89         },
  90 #if (CFG_UEC3_ETH_TYPE == FAST_ETH)
  91         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  92         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  93 #else
  94         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  95         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  96 #endif
  97         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  98         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  99         .tx_bd_ring_len         = 16,
 100         .rx_bd_ring_len         = 16,
 101         .phy_address            = CFG_UEC3_PHY_ADDR,
 102         .enet_interface         = CFG_UEC3_INTERFACE_MODE,
 103 };
 104 #endif
 105 #ifdef CONFIG_UEC_ETH4
 106 static uec_info_t eth4_uec_info = {
 107         .uf_info                = {
 108                 .ucc_num        = CFG_UEC4_UCC_NUM,
 109                 .rx_clock       = CFG_UEC4_RX_CLK,
 110                 .tx_clock       = CFG_UEC4_TX_CLK,
 111                 .eth_type       = CFG_UEC4_ETH_TYPE,
 112         },
 113 #if (CFG_UEC4_ETH_TYPE == FAST_ETH)
 114         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 115         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 116 #else
 117         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 118         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 119 #endif
 120         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 121         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 122         .tx_bd_ring_len         = 16,
 123         .rx_bd_ring_len         = 16,
 124         .phy_address            = CFG_UEC4_PHY_ADDR,
 125         .enet_interface         = CFG_UEC4_INTERFACE_MODE,
 126 };
 127 #endif
 128
 129 #define MAXCONTROLLERS  (4)
 130
 131 static struct eth_device *devlist[MAXCONTROLLERS];
 132
 133 static int uec_miiphy_read(char *devname, unsigned char addr,
 134                             unsigned char reg, unsigned short *value);
 135 static int uec_miiphy_write(char *devname, unsigned char addr,
 136                              unsigned char reg, unsigned short value);
 137 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
 138 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
 139
 140 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 141 {
 142         uec_t           *uec_regs;
 143         u32             maccfg1;
 144
 145         if (!uec) {
 146                 printf("%s: uec not initial\n", __FUNCTION__);
 147                 return -EINVAL;
 148         }
 149         uec_regs = uec->uec_regs;
 150
 151         maccfg1 = in_be32(&uec_regs->maccfg1);
 152
 153         if (mode & COMM_DIR_TX) {
 154                 maccfg1 |= MACCFG1_ENABLE_TX;
 155                 out_be32(&uec_regs->maccfg1, maccfg1);
 156                 uec->mac_tx_enabled = 1;
 157         }
 158
 159         if (mode & COMM_DIR_RX) {
 160                 maccfg1 |= MACCFG1_ENABLE_RX;
 161                 out_be32(&uec_regs->maccfg1, maccfg1);
 162                 uec->mac_rx_enabled = 1;
 163         }
 164
 165         return 0;
 166 }
 167
 168 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
 169 {
 170         uec_t           *uec_regs;
 171         u32             maccfg1;
 172
 173         if (!uec) {
 174                 printf("%s: uec not initial\n", __FUNCTION__);
 175                 return -EINVAL;
 176         }
 177         uec_regs = uec->uec_regs;
 178
 179         maccfg1 = in_be32(&uec_regs->maccfg1);
 180
 181         if (mode & COMM_DIR_TX) {
 182                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 183                 out_be32(&uec_regs->maccfg1, maccfg1);
 184                 uec->mac_tx_enabled = 0;
 185         }
 186
 187         if (mode & COMM_DIR_RX) {
 188                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 189                 out_be32(&uec_regs->maccfg1, maccfg1);
 190                 uec->mac_rx_enabled = 0;
 191         }
 192
 193         return 0;
 194 }
 195
 196 static int uec_graceful_stop_tx(uec_private_t *uec)
 197 {
 198         ucc_fast_t              *uf_regs;
 199         u32                     cecr_subblock;
 200         u32                     ucce;
 201
 202         if (!uec || !uec->uccf) {
 203                 printf("%s: No handle passed.\n", __FUNCTION__);
 204                 return -EINVAL;
 205         }
 206
 207         uf_regs = uec->uccf->uf_regs;
 208
 209         /* Clear the grace stop event */
 210         out_be32(&uf_regs->ucce, UCCE_GRA);
 211
 212         /* Issue host command */
 213         cecr_subblock =
 214                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 215         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 216                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 217
 218         /* Wait for command to complete */
 219         do {
 220                 ucce = in_be32(&uf_regs->ucce);
 221         } while (! (ucce & UCCE_GRA));
 222
 223         uec->grace_stopped_tx = 1;
 224
 225         return 0;
 226 }
 227
 228 static int uec_graceful_stop_rx(uec_private_t *uec)
 229 {
 230         u32             cecr_subblock;
 231         u8              ack;
 232
 233         if (!uec) {
 234                 printf("%s: No handle passed.\n", __FUNCTION__);
 235                 return -EINVAL;
 236         }
 237
 238         if (!uec->p_rx_glbl_pram) {
 239                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 240                 return -EINVAL;
 241         }
 242
 243         /* Clear acknowledge bit */
 244         ack = uec->p_rx_glbl_pram->rxgstpack;
 245         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 246         uec->p_rx_glbl_pram->rxgstpack = ack;
 247
 248         /* Keep issuing cmd and checking ack bit until it is asserted */
 249         do {
 250                 /* Issue host command */
 251                 cecr_subblock =
 252                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 253                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 254                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 255                 ack = uec->p_rx_glbl_pram->rxgstpack;
 256         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 257
 258         uec->grace_stopped_rx = 1;
 259
 260         return 0;
 261 }
 262
 263 static int uec_restart_tx(uec_private_t *uec)
 264 {
 265         u32             cecr_subblock;
 266
 267         if (!uec || !uec->uec_info) {
 268                 printf("%s: No handle passed.\n", __FUNCTION__);
 269                 return -EINVAL;
 270         }
 271
 272         cecr_subblock =
 273          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 274         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 275                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 276
 277         uec->grace_stopped_tx = 0;
 278
 279         return 0;
 280 }
 281
 282 static int uec_restart_rx(uec_private_t *uec)
 283 {
 284         u32             cecr_subblock;
 285
 286         if (!uec || !uec->uec_info) {
 287                 printf("%s: No handle passed.\n", __FUNCTION__);
 288                 return -EINVAL;
 289         }
 290
 291         cecr_subblock =
 292          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 293         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 294                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 295
 296         uec->grace_stopped_rx = 0;
 297
 298         return 0;
 299 }
 300
 301 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 302 {
 303         ucc_fast_private_t      *uccf;
 304
 305         if (!uec || !uec->uccf) {
 306                 printf("%s: No handle passed.\n", __FUNCTION__);
 307                 return -EINVAL;
 308         }
 309         uccf = uec->uccf;
 310
 311         /* check if the UCC number is in range. */
 312         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 313                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 314                 return -EINVAL;
 315         }
 316
 317         /* Enable MAC */
 318         uec_mac_enable(uec, mode);
 319
 320         /* Enable UCC fast */
 321         ucc_fast_enable(uccf, mode);
 322
 323         /* RISC microcode start */
 324         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 325                 uec_restart_tx(uec);
 326         }
 327         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 328                 uec_restart_rx(uec);
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 335 {
 336         ucc_fast_private_t      *uccf;
 337
 338         if (!uec || !uec->uccf) {
 339                 printf("%s: No handle passed.\n", __FUNCTION__);
 340                 return -EINVAL;
 341         }
 342         uccf = uec->uccf;
 343
 344         /* check if the UCC number is in range. */
 345         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 346                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 347                 return -EINVAL;
 348         }
 349         /* Stop any transmissions */
 350         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 351                 uec_graceful_stop_tx(uec);
 352         }
 353         /* Stop any receptions */
 354         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 355                 uec_graceful_stop_rx(uec);
 356         }
 357
 358         /* Disable the UCC fast */
 359         ucc_fast_disable(uec->uccf, mode);
 360
 361         /* Disable the MAC */
 362         uec_mac_disable(uec, mode);
 363
 364         return 0;
 365 }
 366
 367 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 368 {
 369         uec_t           *uec_regs;
 370         u32             maccfg2;
 371
 372         if (!uec) {
 373                 printf("%s: uec not initial\n", __FUNCTION__);
 374                 return -EINVAL;
 375         }
 376         uec_regs = uec->uec_regs;
 377
 378         if (duplex == DUPLEX_HALF) {
 379                 maccfg2 = in_be32(&uec_regs->maccfg2);
 380                 maccfg2 &= ~MACCFG2_FDX;
 381                 out_be32(&uec_regs->maccfg2, maccfg2);
 382         }
 383
 384         if (duplex == DUPLEX_FULL) {
 385                 maccfg2 = in_be32(&uec_regs->maccfg2);
 386                 maccfg2 |= MACCFG2_FDX;
 387                 out_be32(&uec_regs->maccfg2, maccfg2);
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 394 {
 395         enet_interface_e        enet_if_mode;
 396         uec_info_t              *uec_info;
 397         uec_t                   *uec_regs;
 398         u32                     upsmr;
 399         u32                     maccfg2;
 400
 401         if (!uec) {
 402                 printf("%s: uec not initial\n", __FUNCTION__);
 403                 return -EINVAL;
 404         }
 405
 406         uec_info = uec->uec_info;
 407         uec_regs = uec->uec_regs;
 408         enet_if_mode = if_mode;
 409
 410         maccfg2 = in_be32(&uec_regs->maccfg2);
 411         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 412
 413         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 414         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 415
 416         switch (enet_if_mode) {
 417                 case ENET_100_MII:
 418                 case ENET_10_MII:
 419                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 420                         break;
 421                 case ENET_1000_GMII:
 422                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 423                         break;
 424                 case ENET_1000_TBI:
 425                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 426                         upsmr |= UPSMR_TBIM;
 427                         break;
 428                 case ENET_1000_RTBI:
 429                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 430                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 431                         break;
 432                 case ENET_1000_RGMII_RXID:
 433                 case ENET_1000_RGMII:
 434                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 435                         upsmr |= UPSMR_RPM;
 436                         break;
 437                 case ENET_100_RGMII:
 438                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 439                         upsmr |= UPSMR_RPM;
 440                         break;
 441                 case ENET_10_RGMII:
 442                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 443                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 444                         break;
 445                 case ENET_100_RMII:
 446                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 447                         upsmr |= UPSMR_RMM;
 448                         break;
 449                 case ENET_10_RMII:
 450                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 451                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 452                         break;
 453                 default:
 454                         return -EINVAL;
 455                         break;
 456         }
 457         out_be32(&uec_regs->maccfg2, maccfg2);
 458         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 459
 460         return 0;
 461 }
 462
 463 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 464 {
 465         uint            timeout = 0x1000;
 466         u32             miimcfg = 0;
 467
 468         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 469         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 470         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 471
 472         /* Wait until the bus is free */
 473         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 474         if (timeout <= 0) {
 475                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 476                 return -ETIMEDOUT;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int init_phy(struct eth_device *dev)
 483 {
 484         uec_private_t           *uec;
 485         uec_mii_t               *umii_regs;
 486         struct uec_mii_info     *mii_info;
 487         struct phy_info         *curphy;
 488         int                     err;
 489
 490         uec = (uec_private_t *)dev->priv;
 491         umii_regs = uec->uec_mii_regs;
 492
 493         uec->oldlink = 0;
 494         uec->oldspeed = 0;
 495         uec->oldduplex = -1;
 496
 497         mii_info = malloc(sizeof(*mii_info));
 498         if (!mii_info) {
 499                 printf("%s: Could not allocate mii_info", dev->name);
 500                 return -ENOMEM;
 501         }
 502         memset(mii_info, 0, sizeof(*mii_info));
 503
 504         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 505                 mii_info->speed = SPEED_1000;
 506         } else {
 507                 mii_info->speed = SPEED_100;
 508         }
 509
 510         mii_info->duplex = DUPLEX_FULL;
 511         mii_info->pause = 0;
 512         mii_info->link = 1;
 513
 514         mii_info->advertising = (ADVERTISED_10baseT_Half |
 515                                 ADVERTISED_10baseT_Full |
 516                                 ADVERTISED_100baseT_Half |
 517                                 ADVERTISED_100baseT_Full |
 518                                 ADVERTISED_1000baseT_Full);
 519         mii_info->autoneg = 1;
 520         mii_info->mii_id = uec->uec_info->phy_address;
 521         mii_info->dev = dev;
 522
 523         mii_info->mdio_read = &uec_read_phy_reg;
 524         mii_info->mdio_write = &uec_write_phy_reg;
 525
 526         uec->mii_info = mii_info;
 527
 528         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 529
 530         if (init_mii_management_configuration(umii_regs)) {
 531                 printf("%s: The MII Bus is stuck!", dev->name);
 532                 err = -1;
 533                 goto bus_fail;
 534         }
 535
 536         /* get info for this PHY */
 537         curphy = uec_get_phy_info(uec->mii_info);
 538         if (!curphy) {
 539                 printf("%s: No PHY found", dev->name);
 540                 err = -1;
 541                 goto no_phy;
 542         }
 543
 544         mii_info->phyinfo = curphy;
 545
 546         /* Run the commands which initialize the PHY */
 547         if (curphy->init) {
 548                 err = curphy->init(uec->mii_info);
 549                 if (err)
 550                         goto phy_init_fail;
 551         }
 552
 553         return 0;
 554
 555 phy_init_fail:
 556 no_phy:
 557 bus_fail:
 558         free(mii_info);
 559         return err;
 560 }
 561
 562 static void adjust_link(struct eth_device *dev)
 563 {
 564         uec_private_t           *uec = (uec_private_t *)dev->priv;
 565         uec_t                   *uec_regs;
 566         struct uec_mii_info     *mii_info = uec->mii_info;
 567
 568         extern void change_phy_interface_mode(struct eth_device *dev,
 569                                          enet_interface_e mode);
 570         uec_regs = uec->uec_regs;
 571
 572         if (mii_info->link) {
 573                 /* Now we make sure that we can be in full duplex mode.
 574                 * If not, we operate in half-duplex mode. */
 575                 if (mii_info->duplex != uec->oldduplex) {
 576                         if (!(mii_info->duplex)) {
 577                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 578                                 printf("%s: Half Duplex\n", dev->name);
 579                         } else {
 580                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 581                                 printf("%s: Full Duplex\n", dev->name);
 582                         }
 583                         uec->oldduplex = mii_info->duplex;
 584                 }
 585
 586                 if (mii_info->speed != uec->oldspeed) {
 587                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 588                                 switch (mii_info->speed) {
 589                                 case 1000:
 590                                         break;
 591                                 case 100:
 592                                         printf ("switching to rgmii 100\n");
 593                                         /* change phy to rgmii 100 */
 594                                         change_phy_interface_mode(dev,
 595                                                                 ENET_100_RGMII);
 596                                         /* change the MAC interface mode */
 597                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
 598                                         break;
 599                                 case 10:
 600                                         printf ("switching to rgmii 10\n");
 601                                         /* change phy to rgmii 10 */
 602                                         change_phy_interface_mode(dev,
 603                                                                 ENET_10_RGMII);
 604                                         /* change the MAC interface mode */
 605                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
 606                                         break;
 607                                 default:
 608                                         printf("%s: Ack,Speed(%d)is illegal\n",
 609                                                 dev->name, mii_info->speed);
 610                                         break;
 611                                 }
 612                         }
 613
 614                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 615                         uec->oldspeed = mii_info->speed;
 616                 }
 617
 618                 if (!uec->oldlink) {
 619                         printf("%s: Link is up\n", dev->name);
 620                         uec->oldlink = 1;
 621                 }
 622
 623         } else { /* if (mii_info->link) */
 624                 if (uec->oldlink) {
 625                         printf("%s: Link is down\n", dev->name);
 626                         uec->oldlink = 0;
 627                         uec->oldspeed = 0;
 628                         uec->oldduplex = -1;
 629                 }
 630         }
 631 }
 632
 633 static void phy_change(struct eth_device *dev)
 634 {
 635         uec_private_t   *uec = (uec_private_t *)dev->priv;
 636
 637         /* Update the link, speed, duplex */
 638         uec->mii_info->phyinfo->read_status(uec->mii_info);
 639
 640         /* Adjust the interface according to speed */
 641         adjust_link(dev);
 642 }
 643
 644 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 645 {
 646         uec_t           *uec_regs;
 647         u32             mac_addr1;
 648         u32             mac_addr2;
 649
 650         if (!uec) {
 651                 printf("%s: uec not initial\n", __FUNCTION__);
 652                 return -EINVAL;
 653         }
 654
 655         uec_regs = uec->uec_regs;
 656
 657         /* if a station address of 0x12345678ABCD, perform a write to
 658         MACSTNADDR1 of 0xCDAB7856,
 659         MACSTNADDR2 of 0x34120000 */
 660
 661         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 662                         (mac_addr[3] << 8)  | (mac_addr[2]);
 663         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 664
 665         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 666         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 667
 668         return 0;
 669 }
 670
 671 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 672                                          int *threads_num_ret)
 673 {
 674         int     num_threads_numerica;
 675
 676         switch (threads_num) {
 677                 case UEC_NUM_OF_THREADS_1:
 678                         num_threads_numerica = 1;
 679                         break;
 680                 case UEC_NUM_OF_THREADS_2:
 681                         num_threads_numerica = 2;
 682                         break;
 683                 case UEC_NUM_OF_THREADS_4:
 684                         num_threads_numerica = 4;
 685                         break;
 686                 case UEC_NUM_OF_THREADS_6:
 687                         num_threads_numerica = 6;
 688                         break;
 689                 case UEC_NUM_OF_THREADS_8:
 690                         num_threads_numerica = 8;
 691                         break;
 692                 default:
 693                         printf("%s: Bad number of threads value.",
 694                                  __FUNCTION__);
 695                         return -EINVAL;
 696         }
 697
 698         *threads_num_ret = num_threads_numerica;
 699
 700         return 0;
 701 }
 702
 703 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 704 {
 705         uec_info_t      *uec_info;
 706         u32             end_bd;
 707         u8              bmrx = 0;
 708         int             i;
 709
 710         uec_info = uec->uec_info;
 711
 712         /* Alloc global Tx parameter RAM page */
 713         uec->tx_glbl_pram_offset = qe_muram_alloc(
 714                                 sizeof(uec_tx_global_pram_t),
 715                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 716         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 717                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 718
 719         /* Zero the global Tx prameter RAM */
 720         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 721
 722         /* Init global Tx parameter RAM */
 723
 724         /* TEMODER, RMON statistics disable, one Tx queue */
 725         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 726
 727         /* SQPTR */
 728         uec->send_q_mem_reg_offset = qe_muram_alloc(
 729                                 sizeof(uec_send_queue_qd_t),
 730                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 731         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 732                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 733         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 734
 735         /* Setup the table with TxBDs ring */
 736         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 737                                          * SIZEOFBD;
 738         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 739                                  (u32)(uec->p_tx_bd_ring));
 740         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 741                                                  end_bd);
 742
 743         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 744         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 745
 746         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 747         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 748
 749         /* TSTATE, global snooping, big endian, the CSB bus selected */
 750         bmrx = BMR_INIT_VALUE;
 751         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 752
 753         /* IPH_Offset */
 754         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 755                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 756         }
 757
 758         /* VTAG table */
 759         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 760                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 761         }
 762
 763         /* TQPTR */
 764         uec->thread_dat_tx_offset = qe_muram_alloc(
 765                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 766                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 767
 768         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 769                                 qe_muram_addr(uec->thread_dat_tx_offset);
 770         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 771 }
 772
 773 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 774 {
 775         u8      bmrx = 0;
 776         int     i;
 777         uec_82xx_address_filtering_pram_t       *p_af_pram;
 778
 779         /* Allocate global Rx parameter RAM page */
 780         uec->rx_glbl_pram_offset = qe_muram_alloc(
 781                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 782         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 783                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 784
 785         /* Zero Global Rx parameter RAM */
 786         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 787
 788         /* Init global Rx parameter RAM */
 789         /* REMODER, Extended feature mode disable, VLAN disable,
 790          LossLess flow control disable, Receive firmware statisic disable,
 791          Extended address parsing mode disable, One Rx queues,
 792          Dynamic maximum/minimum frame length disable, IP checksum check
 793          disable, IP address alignment disable
 794         */
 795         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 796
 797         /* RQPTR */
 798         uec->thread_dat_rx_offset = qe_muram_alloc(
 799                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 800                          UEC_THREAD_DATA_ALIGNMENT);
 801         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 802                                 qe_muram_addr(uec->thread_dat_rx_offset);
 803         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 804
 805         /* Type_or_Len */
 806         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 807
 808         /* RxRMON base pointer, we don't need it */
 809         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 810
 811         /* IntCoalescingPTR, we don't need it, no interrupt */
 812         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 813
 814         /* RSTATE, global snooping, big endian, the CSB bus selected */
 815         bmrx = BMR_INIT_VALUE;
 816         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 817
 818         /* MRBLR */
 819         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 820
 821         /* RBDQPTR */
 822         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 823                                 sizeof(uec_rx_bd_queues_entry_t) + \
 824                                 sizeof(uec_rx_prefetched_bds_t),
 825                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 826         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 827                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 828
 829         /* Zero it */
 830         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 831                                         sizeof(uec_rx_prefetched_bds_t));
 832         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 833         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 834                  (u32)uec->p_rx_bd_ring);
 835
 836         /* MFLR */
 837         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 838         /* MINFLR */
 839         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 840         /* MAXD1 */
 841         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 842         /* MAXD2 */
 843         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 844         /* ECAM_PTR */
 845         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 846         /* L2QT */
 847         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 848         /* L3QT */
 849         for (i = 0; i < 8; i++) {
 850                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 851         }
 852
 853         /* VLAN_TYPE */
 854         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 855         /* TCI */
 856         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 857
 858         /* Clear PQ2 style address filtering hash table */
 859         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
 860                         uec->p_rx_glbl_pram->addressfiltering;
 861
 862         p_af_pram->iaddr_h = 0;
 863         p_af_pram->iaddr_l = 0;
 864         p_af_pram->gaddr_h = 0;
 865         p_af_pram->gaddr_l = 0;
 866 }
 867
 868 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
 869                                          int thread_tx, int thread_rx)
 870 {
 871         uec_init_cmd_pram_t             *p_init_enet_param;
 872         u32                             init_enet_param_offset;
 873         uec_info_t                      *uec_info;
 874         int                             i;
 875         int                             snum;
 876         u32                             init_enet_offset;
 877         u32                             entry_val;
 878         u32                             command;
 879         u32                             cecr_subblock;
 880
 881         uec_info = uec->uec_info;
 882
 883         /* Allocate init enet command parameter */
 884         uec->init_enet_param_offset = qe_muram_alloc(
 885                                         sizeof(uec_init_cmd_pram_t), 4);
 886         init_enet_param_offset = uec->init_enet_param_offset;
 887         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
 888                                 qe_muram_addr(uec->init_enet_param_offset);
 889
 890         /* Zero init enet command struct */
 891         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
 892
 893         /* Init the command struct */
 894         p_init_enet_param = uec->p_init_enet_param;
 895         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 896         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 897         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 898         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 899         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 900         p_init_enet_param->largestexternallookupkeysize = 0;
 901
 902         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 903                                          << ENET_INIT_PARAM_RGF_SHIFT;
 904         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 905                                          << ENET_INIT_PARAM_TGF_SHIFT;
 906
 907         /* Init Rx global parameter pointer */
 908         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 909                                                  (u32)uec_info->riscRx;
 910
 911         /* Init Rx threads */
 912         for (i = 0; i < (thread_rx + 1); i++) {
 913                 if ((snum = qe_get_snum()) < 0) {
 914                         printf("%s can not get snum\n", __FUNCTION__);
 915                         return -ENOMEM;
 916                 }
 917
 918                 if (i==0) {
 919                         init_enet_offset = 0;
 920                 } else {
 921                         init_enet_offset = qe_muram_alloc(
 922                                         sizeof(uec_thread_rx_pram_t),
 923                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
 924                 }
 925
 926                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 927                                  init_enet_offset | (u32)uec_info->riscRx;
 928                 p_init_enet_param->rxthread[i] = entry_val;
 929         }
 930
 931         /* Init Tx global parameter pointer */
 932         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 933                                          (u32)uec_info->riscTx;
 934
 935         /* Init Tx threads */
 936         for (i = 0; i < thread_tx; i++) {
 937                 if ((snum = qe_get_snum()) < 0) {
 938                         printf("%s can not get snum\n", __FUNCTION__);
 939                         return -ENOMEM;
 940                 }
 941
 942                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
 943                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
 944
 945                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 946                                  init_enet_offset | (u32)uec_info->riscTx;
 947                 p_init_enet_param->txthread[i] = entry_val;
 948         }
 949
 950         __asm__ __volatile__("sync");
 951
 952         /* Issue QE command */
 953         command = QE_INIT_TX_RX;
 954         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 955                                 uec->uec_info->uf_info.ucc_num);
 956         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
 957                                                  init_enet_param_offset);
 958
 959         return 0;
 960 }
 961
 962 static int uec_startup(uec_private_t *uec)
 963 {
 964         uec_info_t                      *uec_info;
 965         ucc_fast_info_t                 *uf_info;
 966         ucc_fast_private_t              *uccf;
 967         ucc_fast_t                      *uf_regs;
 968         uec_t                           *uec_regs;
 969         int                             num_threads_tx;
 970         int                             num_threads_rx;
 971         u32                             utbipar;
 972         enet_interface_e                enet_interface;
 973         u32                             length;
 974         u32                             align;
 975         qe_bd_t                         *bd;
 976         u8                              *buf;
 977         int                             i;
 978
 979         if (!uec || !uec->uec_info) {
 980                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
 981                 return -EINVAL;
 982         }
 983
 984         uec_info = uec->uec_info;
 985         uf_info = &(uec_info->uf_info);
 986
 987         /* Check if Rx BD ring len is illegal */
 988         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
 989                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
 990                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
 991                          __FUNCTION__);
 992                 return -EINVAL;
 993         }
 994
 995         /* Check if Tx BD ring len is illegal */
 996         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
 997                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
 998                          __FUNCTION__);
 999                 return -EINVAL;
1000         }
1001
1002         /* Check if MRBLR is illegal */
1003         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1004                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1005                          __FUNCTION__);
1006                 return -EINVAL;
1007         }
1008
1009         /* Both Rx and Tx are stopped */
1010         uec->grace_stopped_rx = 1;
1011         uec->grace_stopped_tx = 1;
1012
1013         /* Init UCC fast */
1014         if (ucc_fast_init(uf_info, &uccf)) {
1015                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1016                 return -ENOMEM;
1017         }
1018
1019         /* Save uccf */
1020         uec->uccf = uccf;
1021
1022         /* Convert the Tx threads number */
1023         if (uec_convert_threads_num(uec_info->num_threads_tx,
1024                                          &num_threads_tx)) {
1025                 return -EINVAL;
1026         }
1027
1028         /* Convert the Rx threads number */
1029         if (uec_convert_threads_num(uec_info->num_threads_rx,
1030                                          &num_threads_rx)) {
1031                 return -EINVAL;
1032         }
1033
1034         uf_regs = uccf->uf_regs;
1035
1036         /* UEC register is following UCC fast registers */
1037         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1038
1039         /* Save the UEC register pointer to UEC private struct */
1040         uec->uec_regs = uec_regs;
1041
1042         /* Init UPSMR, enable hardware statistics (UCC) */
1043         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1044
1045         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1046         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1047
1048         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1049         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1050
1051         /* Setup MAC interface mode */
1052         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1053
1054         /* Setup MII management base */
1055 #ifndef CONFIG_eTSEC_MDIO_BUS
1056         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1057 #else
1058         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1059 #endif
1060
1061         /* Setup MII master clock source */
1062         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1063
1064         /* Setup UTBIPAR */
1065         utbipar = in_be32(&uec_regs->utbipar);
1066         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1067         enet_interface = uec->uec_info->enet_interface;
1068         if (enet_interface == ENET_1000_TBI ||
1069                  enet_interface == ENET_1000_RTBI) {
1070                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1071                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1072         } else {
1073                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1074                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1075         }
1076
1077         out_be32(&uec_regs->utbipar, utbipar);
1078
1079         /* Allocate Tx BDs */
1080         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1081                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1082                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1083         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1084                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1085                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1086         }
1087
1088         align = UEC_TX_BD_RING_ALIGNMENT;
1089         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1090         if (uec->tx_bd_ring_offset != 0) {
1091                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1092                                                  & ~(align - 1));
1093         }
1094
1095         /* Zero all of Tx BDs */
1096         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1097
1098         /* Allocate Rx BDs */
1099         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1100         align = UEC_RX_BD_RING_ALIGNMENT;
1101         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1102         if (uec->rx_bd_ring_offset != 0) {
1103                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1104                                                          & ~(align - 1));
1105         }
1106
1107         /* Zero all of Rx BDs */
1108         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1109
1110         /* Allocate Rx buffer */
1111         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1112         align = UEC_RX_DATA_BUF_ALIGNMENT;
1113         uec->rx_buf_offset = (u32)malloc(length + align);
1114         if (uec->rx_buf_offset != 0) {
1115                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1116                                                  & ~(align - 1));
1117         }
1118
1119         /* Zero all of the Rx buffer */
1120         memset((void *)(uec->rx_buf_offset), 0, length + align);
1121
1122         /* Init TxBD ring */
1123         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1124         uec->txBd = bd;
1125
1126         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1127                 BD_DATA_CLEAR(bd);
1128                 BD_STATUS_SET(bd, 0);
1129                 BD_LENGTH_SET(bd, 0);
1130                 bd ++;
1131         }
1132         BD_STATUS_SET((--bd), TxBD_WRAP);
1133
1134         /* Init RxBD ring */
1135         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1136         uec->rxBd = bd;
1137         buf = uec->p_rx_buf;
1138         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1139                 BD_DATA_SET(bd, buf);
1140                 BD_LENGTH_SET(bd, 0);
1141                 BD_STATUS_SET(bd, RxBD_EMPTY);
1142                 buf += MAX_RXBUF_LEN;
1143                 bd ++;
1144         }
1145         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1146
1147         /* Init global Tx parameter RAM */
1148         uec_init_tx_parameter(uec, num_threads_tx);
1149
1150         /* Init global Rx parameter RAM */
1151         uec_init_rx_parameter(uec, num_threads_rx);
1152
1153         /* Init ethernet Tx and Rx parameter command */
1154         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1155                                          num_threads_rx)) {
1156                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1157                 return -ENOMEM;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int uec_init(struct eth_device* dev, bd_t *bd)
1164 {
1165         uec_private_t           *uec;
1166         int                     err, i;
1167         struct phy_info         *curphy;
1168
1169         uec = (uec_private_t *)dev->priv;
1170
1171         if (uec->the_first_run == 0) {
1172                 err = init_phy(dev);
1173                 if (err) {
1174                         printf("%s: Cannot initialize PHY, aborting.\n",
1175                                dev->name);
1176                         return err;
1177                 }
1178
1179                 curphy = uec->mii_info->phyinfo;
1180
1181                 if (curphy->config_aneg) {
1182                         err = curphy->config_aneg(uec->mii_info);
1183                         if (err) {
1184                                 printf("%s: Can't negotiate PHY\n", dev->name);
1185                                 return err;
1186                         }
1187                 }
1188
1189                 /* Give PHYs up to 5 sec to report a link */
1190                 i = 50;
1191                 do {
1192                         err = curphy->read_status(uec->mii_info);
1193                         udelay(100000);
1194                 } while (((i-- > 0) && !uec->mii_info->link) || err);
1195
1196                 if (err || i <= 0)
1197                         printf("warning: %s: timeout on PHY link\n", dev->name);
1198
1199                 uec->the_first_run = 1;
1200         }
1201
1202         /* Set up the MAC address */
1203         if (dev->enetaddr[0] & 0x01) {
1204                 printf("%s: MacAddress is multcast address\n",
1205                          __FUNCTION__);
1206                 return -1;
1207         }
1208         uec_set_mac_address(uec, dev->enetaddr);
1209
1210
1211         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1212         if (err) {
1213                 printf("%s: cannot enable UEC device\n", dev->name);
1214                 return -1;
1215         }
1216
1217         phy_change(dev);
1218
1219         return (uec->mii_info->link ? 0 : -1);
1220 }
1221
1222 static void uec_halt(struct eth_device* dev)
1223 {
1224         uec_private_t   *uec = (uec_private_t *)dev->priv;
1225         uec_stop(uec, COMM_DIR_RX_AND_TX);
1226 }
1227
1228 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1229 {
1230         uec_private_t           *uec;
1231         ucc_fast_private_t      *uccf;
1232         volatile qe_bd_t        *bd;
1233         u16                     status;
1234         int                     i;
1235         int                     result = 0;
1236
1237         uec = (uec_private_t *)dev->priv;
1238         uccf = uec->uccf;
1239         bd = uec->txBd;
1240
1241         /* Find an empty TxBD */
1242         for (i = 0; bd->status & TxBD_READY; i++) {
1243                 if (i > 0x100000) {
1244                         printf("%s: tx buffer not ready\n", dev->name);
1245                         return result;
1246                 }
1247         }
1248
1249         /* Init TxBD */
1250         BD_DATA_SET(bd, buf);
1251         BD_LENGTH_SET(bd, len);
1252         status = bd->status;
1253         status &= BD_WRAP;
1254         status |= (TxBD_READY | TxBD_LAST);
1255         BD_STATUS_SET(bd, status);
1256
1257         /* Tell UCC to transmit the buffer */
1258         ucc_fast_transmit_on_demand(uccf);
1259
1260         /* Wait for buffer to be transmitted */
1261         for (i = 0; bd->status & TxBD_READY; i++) {
1262                 if (i > 0x100000) {
1263                         printf("%s: tx error\n", dev->name);
1264                         return result;
1265                 }
1266         }
1267
1268         /* Ok, the buffer be transimitted */
1269         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1270         uec->txBd = bd;
1271         result = 1;
1272
1273         return result;
1274 }
1275
1276 static int uec_recv(struct eth_device* dev)
1277 {
1278         uec_private_t           *uec = dev->priv;
1279         volatile qe_bd_t        *bd;
1280         u16                     status;
1281         u16                     len;
1282         u8                      *data;
1283
1284         bd = uec->rxBd;
1285         status = bd->status;
1286
1287         while (!(status & RxBD_EMPTY)) {
1288                 if (!(status & RxBD_ERROR)) {
1289                         data = BD_DATA(bd);
1290                         len = BD_LENGTH(bd);
1291                         NetReceive(data, len);
1292                 } else {
1293                         printf("%s: Rx error\n", dev->name);
1294                 }
1295                 status &= BD_CLEAN;
1296                 BD_LENGTH_SET(bd, 0);
1297                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1298                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1299                 status = bd->status;
1300         }
1301         uec->rxBd = bd;
1302
1303         return 1;
1304 }
1305
1306 int uec_initialize(int index)
1307 {
1308         struct eth_device       *dev;
1309         int                     i;
1310         uec_private_t           *uec;
1311         uec_info_t              *uec_info;
1312         int                     err;
1313
1314         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1315         if (!dev)
1316                 return 0;
1317         memset(dev, 0, sizeof(struct eth_device));
1318
1319         /* Allocate the UEC private struct */
1320         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1321         if (!uec) {
1322                 return -ENOMEM;
1323         }
1324         memset(uec, 0, sizeof(uec_private_t));
1325
1326         /* Init UEC private struct, they come from board.h */
1327         uec_info = NULL;
1328         if (index == 0) {
1329 #ifdef CONFIG_UEC_ETH1
1330                 uec_info = &eth1_uec_info;
1331 #endif
1332         } else if (index == 1) {
1333 #ifdef CONFIG_UEC_ETH2
1334                 uec_info = &eth2_uec_info;
1335 #endif
1336         } else if (index == 2) {
1337 #ifdef CONFIG_UEC_ETH3
1338                 uec_info = &eth3_uec_info;
1339 #endif
1340         } else if (index == 3) {
1341 #ifdef CONFIG_UEC_ETH4
1342                 uec_info = &eth4_uec_info;
1343 #endif
1344         } else {
1345                 printf("%s: index is illegal.\n", __FUNCTION__);
1346                 return -EINVAL;
1347         }
1348
1349         devlist[index] = dev;
1350
1351         uec->uec_info = uec_info;
1352
1353         sprintf(dev->name, "FSL UEC%d", index);
1354         dev->iobase = 0;
1355         dev->priv = (void *)uec;
1356         dev->init = uec_init;
1357         dev->halt = uec_halt;
1358         dev->send = uec_send;
1359         dev->recv = uec_recv;
1360
1361         /* Clear the ethnet address */
1362         for (i = 0; i < 6; i++)
1363                 dev->enetaddr[i] = 0;
1364
1365         eth_register(dev);
1366
1367         err = uec_startup(uec);
1368         if (err) {
1369                 printf("%s: Cannot configure net device, aborting.",dev->name);
1370                 return err;
1371         }
1372
1373 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1374         && !defined(BITBANGMII)
1375         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1376 #endif
1377
1378         return 1;
1379 }
1380
1381 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1382         && !defined(BITBANGMII)
1383
1384 /*
1385  * Read a MII PHY register.
1386  *
1387  * Returns:
1388  *  0 on success
1389  */
1390 static int uec_miiphy_read(char *devname, unsigned char addr,
1391                             unsigned char reg, unsigned short *value)
1392 {
1393         *value = uec_read_phy_reg(devlist[0], addr, reg);
1394
1395         return 0;
1396 }
1397
1398 /*
1399  * Write a MII PHY register.
1400  *
1401  * Returns:
1402  *  0 on success
1403  */
1404 static int uec_miiphy_write(char *devname, unsigned char addr,
1405                              unsigned char reg, unsigned short value)
1406 {
1407         uec_write_phy_reg(devlist[0], addr, reg, value);
1408
1409         return 0;
1410 }
1411
1412 #endif
1413
1414 #endif /* CONFIG_QE */