drivers/qe/uccf.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on source code of Shlomi Gridish
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include "common.h"
  11 #include "malloc.h"
  12 #include "asm/errno.h"
  13 #include "asm/io.h"
  14 #include "asm/immap_qe.h"
  15 #include "qe.h"
  16 #include "uccf.h"
  17
  18 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
  19 {
  20         out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
  21 }
  22
  23 u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
  24 {
  25         switch (ucc_num) {
  26                 case 0: return QE_CR_SUBBLOCK_UCCFAST1;
  27                 case 1: return QE_CR_SUBBLOCK_UCCFAST2;
  28                 case 2: return QE_CR_SUBBLOCK_UCCFAST3;
  29                 case 3: return QE_CR_SUBBLOCK_UCCFAST4;
  30                 case 4: return QE_CR_SUBBLOCK_UCCFAST5;
  31                 case 5: return QE_CR_SUBBLOCK_UCCFAST6;
  32                 case 6: return QE_CR_SUBBLOCK_UCCFAST7;
  33                 case 7: return QE_CR_SUBBLOCK_UCCFAST8;
  34                 default:        return QE_CR_SUBBLOCK_INVALID;
  35         }
  36 }
  37
  38 static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
  39                                  u8 *reg_num, u8 *shift)
  40 {
  41         switch (ucc_num) {
  42                 case 0: /* UCC1 */
  43                         *p_cmxucr  = &(qe_immr->qmx.cmxucr1);
  44                         *reg_num = 1;
  45                         *shift  = 16;
  46                         break;
  47                 case 2: /* UCC3 */
  48                         *p_cmxucr  = &(qe_immr->qmx.cmxucr1);
  49                         *reg_num = 1;
  50                         *shift  = 0;
  51                         break;
  52                 case 4: /* UCC5 */
  53                         *p_cmxucr  = &(qe_immr->qmx.cmxucr2);
  54                         *reg_num = 2;
  55                         *shift  = 16;
  56                         break;
  57                 case 6: /* UCC7 */
  58                         *p_cmxucr  = &(qe_immr->qmx.cmxucr2);
  59                         *reg_num = 2;
  60                         *shift  = 0;
  61                         break;
  62                 case 1: /* UCC2 */
  63                         *p_cmxucr  = &(qe_immr->qmx.cmxucr3);
  64                         *reg_num = 3;
  65                         *shift  = 16;
  66                         break;
  67                 case 3: /* UCC4 */
  68                         *p_cmxucr  = &(qe_immr->qmx.cmxucr3);
  69                         *reg_num = 3;
  70                         *shift  = 0;
  71                         break;
  72                 case 5: /* UCC6 */
  73                         *p_cmxucr  = &(qe_immr->qmx.cmxucr4);
  74                         *reg_num = 4;
  75                         *shift  = 16;
  76                         break;
  77                 case 7: /* UCC8 */
  78                         *p_cmxucr  = &(qe_immr->qmx.cmxucr4);
  79                         *reg_num = 4;
  80                         *shift  = 0;
  81                         break;
  82                 default:
  83                         break;
  84         }
  85 }
  86
  87 static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
  88 {
  89         volatile u32    *p_cmxucr = NULL;
  90         u8              reg_num = 0;
  91         u8              shift = 0;
  92         u32             clockBits;
  93         u32             clockMask;
  94         int             source = -1;
  95
  96         /* check if the UCC number is in range. */
  97         if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
  98                 return -EINVAL;
  99
 100         if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
 101                 printf("%s: bad comm mode type passed\n", __FUNCTION__);
 102                 return -EINVAL;
 103         }
 104
 105         ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
 106
 107         switch (reg_num) {
 108                 case 1:
 109                         switch (clock) {
 110                                 case QE_BRG1:   source = 1; break;
 111                                 case QE_BRG2:   source = 2; break;
 112                                 case QE_BRG7:   source = 3; break;
 113                                 case QE_BRG8:   source = 4; break;
 114                                 case QE_CLK9:   source = 5; break;
 115                                 case QE_CLK10:  source = 6; break;
 116                                 case QE_CLK11:  source = 7; break;
 117                                 case QE_CLK12:  source = 8; break;
 118                                 case QE_CLK15:  source = 9; break;
 119                                 case QE_CLK16:  source = 10; break;
 120                                 default:        source = -1; break;
 121                         }
 122                         break;
 123                 case 2:
 124                         switch (clock) {
 125                                 case QE_BRG5:   source = 1; break;
 126                                 case QE_BRG6:   source = 2; break;
 127                                 case QE_BRG7:   source = 3; break;
 128                                 case QE_BRG8:   source = 4; break;
 129                                 case QE_CLK13:  source = 5; break;
 130                                 case QE_CLK14:  source = 6; break;
 131                                 case QE_CLK19:  source = 7; break;
 132                                 case QE_CLK20:  source = 8; break;
 133                                 case QE_CLK15:  source = 9; break;
 134                                 case QE_CLK16:  source = 10; break;
 135                                 default:        source = -1; break;
 136                         }
 137                         break;
 138                 case 3:
 139                         switch (clock) {
 140                                 case QE_BRG9:   source = 1; break;
 141                                 case QE_BRG10:  source = 2; break;
 142                                 case QE_BRG15:  source = 3; break;
 143                                 case QE_BRG16:  source = 4; break;
 144                                 case QE_CLK3:   source = 5; break;
 145                                 case QE_CLK4:   source = 6; break;
 146                                 case QE_CLK17:  source = 7; break;
 147                                 case QE_CLK18:  source = 8; break;
 148                                 case QE_CLK7:   source = 9; break;
 149                                 case QE_CLK8:   source = 10; break;
 150                                 case QE_CLK16:  source = 11; break;
 151                                 default:        source = -1; break;
 152                         }
 153                         break;
 154                 case 4:
 155                         switch (clock) {
 156                                 case QE_BRG13:  source = 1; break;
 157                                 case QE_BRG14:  source = 2; break;
 158                                 case QE_BRG15:  source = 3; break;
 159                                 case QE_BRG16:  source = 4; break;
 160                                 case QE_CLK5:   source = 5; break;
 161                                 case QE_CLK6:   source = 6; break;
 162                                 case QE_CLK21:  source = 7; break;
 163                                 case QE_CLK22:  source = 8; break;
 164                                 case QE_CLK7:   source = 9; break;
 165                                 case QE_CLK8:   source = 10; break;
 166                                 case QE_CLK16:  source = 11; break;
 167                                 default:        source = -1; break;
 168                         }
 169                         break;
 170                 default:
 171                         source = -1;
 172                         break;
 173         }
 174
 175         if (source == -1) {
 176                 printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
 177                 return -ENOENT;
 178         }
 179
 180         clockBits = (u32) source;
 181         clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
 182         if (mode == COMM_DIR_RX) {
 183                 clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
 184                 clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
 185         }
 186         clockBits <<= shift;
 187         clockMask <<= shift;
 188
 189         out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
 190
 191         return 0;
 192 }
 193
 194 static uint ucc_get_reg_baseaddr(int ucc_num)
 195 {
 196         uint base = 0;
 197
 198         /* check if the UCC number is in range */
 199         if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
 200                 printf("%s: the UCC num not in ranges\n", __FUNCTION__);
 201                 return 0;
 202         }
 203
 204         switch (ucc_num) {
 205                 case 0: base = 0x00002000; break;
 206                 case 1: base = 0x00003000; break;
 207                 case 2: base = 0x00002200; break;
 208                 case 3: base = 0x00003200; break;
 209                 case 4: base = 0x00002400; break;
 210                 case 5: base = 0x00003400; break;
 211                 case 6: base = 0x00002600; break;
 212                 case 7: base = 0x00003600; break;
 213                 default: break;
 214         }
 215
 216         base = (uint)qe_immr + base;
 217         return base;
 218 }
 219
 220 void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
 221 {
 222         ucc_fast_t      *uf_regs;
 223         u32             gumr;
 224
 225         uf_regs = uccf->uf_regs;
 226
 227         /* Enable reception and/or transmission on this UCC. */
 228         gumr = in_be32(&uf_regs->gumr);
 229         if (mode & COMM_DIR_TX) {
 230                 gumr |= UCC_FAST_GUMR_ENT;
 231                 uccf->enabled_tx = 1;
 232         }
 233         if (mode & COMM_DIR_RX) {
 234                 gumr |= UCC_FAST_GUMR_ENR;
 235                 uccf->enabled_rx = 1;
 236         }
 237         out_be32(&uf_regs->gumr, gumr);
 238 }
 239
 240 void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
 241 {
 242         ucc_fast_t      *uf_regs;
 243         u32             gumr;
 244
 245         uf_regs = uccf->uf_regs;
 246
 247         /* Disable reception and/or transmission on this UCC. */
 248         gumr = in_be32(&uf_regs->gumr);
 249         if (mode & COMM_DIR_TX) {
 250                 gumr &= ~UCC_FAST_GUMR_ENT;
 251                 uccf->enabled_tx = 0;
 252         }
 253         if (mode & COMM_DIR_RX) {
 254                 gumr &= ~UCC_FAST_GUMR_ENR;
 255                 uccf->enabled_rx = 0;
 256         }
 257         out_be32(&uf_regs->gumr, gumr);
 258 }
 259
 260 int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t  **uccf_ret)
 261 {
 262         ucc_fast_private_t      *uccf;
 263         ucc_fast_t              *uf_regs;
 264
 265         if (!uf_info)
 266                 return -EINVAL;
 267
 268         if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
 269                 printf("%s: Illagal UCC number!\n", __FUNCTION__);
 270                 return -EINVAL;
 271         }
 272
 273         uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
 274         if (!uccf) {
 275                 printf("%s: No memory for UCC fast data structure!\n",
 276                          __FUNCTION__);
 277                 return -ENOMEM;
 278         }
 279         memset(uccf, 0, sizeof(ucc_fast_private_t));
 280
 281         /* Save fast UCC structure */
 282         uccf->uf_info   = uf_info;
 283         uccf->uf_regs   = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
 284
 285         if (uccf->uf_regs == NULL) {
 286                 printf("%s: No memory map for UCC fast controller!\n",
 287                          __FUNCTION__);
 288                 return -ENOMEM;
 289         }
 290
 291         uccf->enabled_tx        = 0;
 292         uccf->enabled_rx        = 0;
 293
 294         uf_regs                 = uccf->uf_regs;
 295         uccf->p_ucce            = (u32 *) &(uf_regs->ucce);
 296         uccf->p_uccm            = (u32 *) &(uf_regs->uccm);
 297
 298         /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
 299         out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
 300                                  | UCC_GUEMR_MODE_FAST_TX);
 301
 302         /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
 303         out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
 304
 305         /* Set the Giga ethernet VFIFO stuff */
 306         if (uf_info->eth_type == GIGA_ETH) {
 307                 /* Allocate memory for Tx Virtual Fifo */
 308                 uccf->ucc_fast_tx_virtual_fifo_base_offset =
 309                 qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
 310                                  UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 311
 312                 /* Allocate memory for Rx Virtual Fifo */
 313                 uccf->ucc_fast_rx_virtual_fifo_base_offset =
 314                 qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
 315                                  UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
 316                                 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 317
 318                 /* utfb, urfb are offsets from MURAM base */
 319                 out_be32(&uf_regs->utfb,
 320                          uccf->ucc_fast_tx_virtual_fifo_base_offset);
 321                 out_be32(&uf_regs->urfb,
 322                          uccf->ucc_fast_rx_virtual_fifo_base_offset);
 323
 324                 /* Set Virtual Fifo registers */
 325                 out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
 326                 out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
 327                 out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
 328                 out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
 329                 out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
 330                 out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
 331         }
 332
 333         /* Set the Fast ethernet VFIFO stuff */
 334         if (uf_info->eth_type == FAST_ETH) {
 335                 /* Allocate memory for Tx Virtual Fifo */
 336                 uccf->ucc_fast_tx_virtual_fifo_base_offset =
 337                 qe_muram_alloc(UCC_GETH_UTFS_INIT,
 338                                  UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 339
 340                 /* Allocate memory for Rx Virtual Fifo */
 341                 uccf->ucc_fast_rx_virtual_fifo_base_offset =
 342                 qe_muram_alloc(UCC_GETH_URFS_INIT +
 343                                  UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
 344                                 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
 345
 346                 /* utfb, urfb are offsets from MURAM base */
 347                 out_be32(&uf_regs->utfb,
 348                          uccf->ucc_fast_tx_virtual_fifo_base_offset);
 349                 out_be32(&uf_regs->urfb,
 350                          uccf->ucc_fast_rx_virtual_fifo_base_offset);
 351
 352                 /* Set Virtual Fifo registers */
 353                 out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
 354                 out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
 355                 out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
 356                 out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
 357                 out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
 358                 out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
 359         }
 360
 361         /* Rx clock routing */
 362         if (uf_info->rx_clock != QE_CLK_NONE) {
 363                 if (ucc_set_clk_src(uf_info->ucc_num,
 364                          uf_info->rx_clock, COMM_DIR_RX)) {
 365                         printf("%s: Illegal value for parameter 'RxClock'.\n",
 366                                  __FUNCTION__);
 367                         return -EINVAL;
 368                 }
 369         }
 370
 371         /* Tx clock routing */
 372         if (uf_info->tx_clock != QE_CLK_NONE) {
 373                 if (ucc_set_clk_src(uf_info->ucc_num,
 374                          uf_info->tx_clock, COMM_DIR_TX)) {
 375                         printf("%s: Illegal value for parameter 'TxClock'.\n",
 376                                  __FUNCTION__);
 377                         return -EINVAL;
 378                 }
 379         }
 380
 381         /* Clear interrupt mask register to disable all of interrupts */
 382         out_be32(&uf_regs->uccm, 0x0);
 383
 384         /* Writing '1' to clear all of envents */
 385         out_be32(&uf_regs->ucce, 0xffffffff);
 386
 387         *uccf_ret = uccf;
 388         return 0;
 389 }