2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include "asm/errno.h"
26 #include "asm/immap_qe.h"
29 #if defined(CONFIG_QE)
30 qe_map_t *qe_immr = NULL;
31 static qe_snum_t snums[QE_NUM_OF_SNUM];
33 DECLARE_GLOBAL_DATA_PTR;
35 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
39 if (cmd == QE_RESET) {
40 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
42 out_be32(&qe_immr->cp.cecdr, cmd_data);
43 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
44 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
46 /* Wait for the QE_CR_FLG to clear */
48 cecr = in_be32(&qe_immr->cp.cecr);
49 } while (cecr & QE_CR_FLG);
54 uint qe_muram_alloc(uint size, uint align)
60 align_mask = align - 1;
61 savebase = gd->mp_alloc_base;
63 if ((off = (gd->mp_alloc_base & align_mask)) != 0)
64 gd->mp_alloc_base += (align - off);
66 if ((off = size & align_mask) != 0)
67 size += (align - off);
69 if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
70 gd->mp_alloc_base = savebase;
71 printf("%s: ran out of ram.\n", __FUNCTION__);
74 retloc = gd->mp_alloc_base;
75 gd->mp_alloc_base += size;
77 memset((void *)&qe_immr->muram[retloc], 0, size);
79 __asm__ __volatile__("sync");
84 void *qe_muram_addr(uint offset)
86 return (void *)&qe_immr->muram[offset];
89 static void qe_sdma_init(void)
92 uint sdma_buffer_base;
94 p = (volatile sdma_t *)&qe_immr->sdma;
96 /* All of DMA transaction in bus 1 */
97 out_be32(&p->sdaqr, 0);
98 out_be32(&p->sdaqmr, 0);
100 /* Allocate 2KB temporary buffer for sdma */
101 sdma_buffer_base = qe_muram_alloc(2048, 4096);
102 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
104 /* Clear sdma status */
105 out_be32(&p->sdsr, 0x03000000);
107 /* Enable global mode on bus 1, and 2KB buffer size */
108 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
111 static u8 thread_snum[QE_NUM_OF_SNUM] = {
112 0x04, 0x05, 0x0c, 0x0d,
113 0x14, 0x15, 0x1c, 0x1d,
114 0x24, 0x25, 0x2c, 0x2d,
115 0x34, 0x35, 0x88, 0x89,
116 0x98, 0x99, 0xa8, 0xa9,
117 0xb8, 0xb9, 0xc8, 0xc9,
118 0xd8, 0xd9, 0xe8, 0xe9
121 static void qe_snums_init(void)
125 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
126 snums[i].state = QE_SNUM_STATE_FREE;
127 snums[i].num = thread_snum[i];
131 int qe_get_snum(void)
136 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
137 if (snums[i].state == QE_SNUM_STATE_FREE) {
138 snums[i].state = QE_SNUM_STATE_USED;
147 void qe_put_snum(u8 snum)
151 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
152 if (snums[i].num == snum) {
153 snums[i].state = QE_SNUM_STATE_FREE;
159 void qe_init(uint qe_base)
161 /* Init the QE IMMR base */
162 qe_immr = (qe_map_t *)qe_base;
164 gd->mp_alloc_base = QE_DATAONLY_BASE;
165 gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
173 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
174 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
177 void qe_assign_page(uint snum, uint para_ram_base)
181 out_be32(&qe_immr->cp.cecdr, para_ram_base);
182 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
183 | QE_CR_FLG | QE_ASSIGN_PAGE);
185 /* Wait for the QE_CR_FLG to clear */
187 cecr = in_be32(&qe_immr->cp.cecr);
188 } while (cecr & QE_CR_FLG );
194 * brg: 0~15 as BRG1~BRG16
196 * BRG input clock comes from the BRGCLK (internal clock generated from
197 the QE clock, it is one-half of the QE clock), If need the clock source
198 from CLKn pin, we have te change the function.
201 #define BRG_CLK (gd->brg_clk)
203 int qe_set_brg(uint brg, uint rate)
209 if (brg >= QE_NUM_OF_BRGS)
211 bp = (uint *)&qe_immr->brg.brgc1;
214 divisor = (BRG_CLK / rate);
215 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
220 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
221 __asm__ __volatile__("sync");
224 *bp |= QE_BRGC_DIV16;
225 __asm__ __volatile__("sync");
231 /* Set ethernet MII clock master
233 int qe_set_mii_clk_src(int ucc_num)
237 /* check if the UCC number is in range. */
238 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
239 printf("%s: ucc num not in ranges\n", __FUNCTION__);
243 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
244 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
245 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
246 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
251 #endif /* CONFIG_QE */