1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
12 #include <linux/errno.h>
14 #include <linux/immap_qe.h>
17 #include <u-boot/crc.h>
19 #ifdef CONFIG_ARCH_LS1021A
20 #include <asm/arch/immap_ls102xa.h>
23 #include <asm/armv8/mmu.h>
24 #include <asm/arch/cpu.h>
27 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
31 static qe_snum_t snums[QE_NUM_OF_SNUM];
34 DECLARE_GLOBAL_DATA_PTR;
36 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
40 if (cmd == QE_RESET) {
41 out_be32(&qe_immr->cp.cecr, (u32)(cmd | QE_CR_FLG));
43 out_be32(&qe_immr->cp.cecdr, cmd_data);
44 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
45 ((u32)mcn << QE_CR_PROTOCOL_SHIFT) | cmd));
47 /* Wait for the QE_CR_FLG to clear */
49 cecr = in_be32(&qe_immr->cp.cecr);
50 } while (cecr & QE_CR_FLG);
54 uint qe_muram_alloc(uint size, uint align)
60 align_mask = align - 1;
61 savebase = gd->arch.mp_alloc_base;
63 off = gd->arch.mp_alloc_base & align_mask;
65 gd->arch.mp_alloc_base += (align - off);
67 off = size & align_mask;
69 size += (align - off);
71 if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
72 gd->arch.mp_alloc_base = savebase;
73 printf("%s: ran out of ram.\n", __func__);
76 retloc = gd->arch.mp_alloc_base;
77 gd->arch.mp_alloc_base += size;
79 memset((void *)&qe_immr->muram[retloc], 0, size);
81 __asm__ __volatile__("sync");
87 void *qe_muram_addr(uint offset)
89 return (void *)&qe_immr->muram[offset];
93 static void qe_sdma_init(void)
96 uint sdma_buffer_base;
98 p = (sdma_t *)&qe_immr->sdma;
100 /* All of DMA transaction in bus 1 */
101 out_be32(&p->sdaqr, 0);
102 out_be32(&p->sdaqmr, 0);
104 /* Allocate 2KB temporary buffer for sdma */
105 sdma_buffer_base = qe_muram_alloc(2048, 4096);
106 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
108 /* Clear sdma status */
109 out_be32(&p->sdsr, 0x03000000);
111 /* Enable global mode on bus 1, and 2KB buffer size */
112 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
115 /* This table is a list of the serial numbers of the Threads, taken from the
116 * "SNUM Table" chart in the QE Reference Manual. The order is not important,
117 * we just need to know what the SNUMs are for the threads.
119 static u8 thread_snum[] = {
120 /* Evthreads 16-29 are not supported in MPC8309 */
121 #if !defined(CONFIG_ARCH_MPC8309)
122 0x04, 0x05, 0x0c, 0x0d,
123 0x14, 0x15, 0x1c, 0x1d,
124 0x24, 0x25, 0x2c, 0x2d,
127 0x88, 0x89, 0x98, 0x99,
128 0xa8, 0xa9, 0xb8, 0xb9,
129 0xc8, 0xc9, 0xd8, 0xd9,
130 0xe8, 0xe9, 0x08, 0x09,
131 0x18, 0x19, 0x28, 0x29,
132 0x38, 0x39, 0x48, 0x49,
133 0x58, 0x59, 0x68, 0x69,
134 0x78, 0x79, 0x80, 0x81
137 static void qe_snums_init(void)
141 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
142 snums[i].state = QE_SNUM_STATE_FREE;
143 snums[i].num = thread_snum[i];
147 int qe_get_snum(void)
152 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
153 if (snums[i].state == QE_SNUM_STATE_FREE) {
154 snums[i].state = QE_SNUM_STATE_USED;
163 void qe_put_snum(u8 snum)
167 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
168 if (snums[i].num == snum) {
169 snums[i].state = QE_SNUM_STATE_FREE;
175 #ifdef CONFIG_TFABOOT
176 void qe_init(uint qe_base)
178 enum boot_src src = get_boot_src();
180 /* Init the QE IMMR base */
181 qe_immr = (qe_map_t *)qe_base;
183 if (src == BOOT_SOURCE_IFC_NOR) {
185 * Upload microcode to IRAM for those SOCs
186 * which do not have ROM in QE.
188 qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
189 CONFIG_SYS_FSL_IFC_BASE));
191 /* enable the microcode in IRAM */
192 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
195 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
196 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
202 void qe_init(uint qe_base)
204 /* Init the QE IMMR base */
205 qe_immr = (qe_map_t *)qe_base;
207 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
209 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
211 qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
213 /* enable the microcode in IRAM */
214 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
217 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
218 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
227 #ifdef CONFIG_TFABOOT
230 enum boot_src src = get_boot_src();
232 qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
234 void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
236 if (src == BOOT_SOURCE_IFC_NOR)
237 addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
238 CONFIG_SYS_FSL_IFC_BASE);
240 if (src == BOOT_SOURCE_QSPI_NOR)
241 addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
242 CONFIG_SYS_FSL_QSPI_BASE);
244 if (src == BOOT_SOURCE_SD_MMC) {
245 int dev = CONFIG_SYS_MMC_ENV_DEV;
246 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
247 u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
249 if (mmc_initialize(gd->bd)) {
250 printf("%s: mmc_initialize() failed\n", __func__);
253 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
254 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
258 printf("\nMMC cannot find device for ucode\n");
260 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
263 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
267 if (!u_qe_upload_firmware(addr))
268 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
269 if (src == BOOT_SOURCE_SD_MMC)
275 qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
277 void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
278 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
279 int dev = CONFIG_SYS_MMC_ENV_DEV;
280 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
281 u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
283 if (mmc_initialize(gd->bd)) {
284 printf("%s: mmc_initialize() failed\n", __func__);
287 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
288 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
291 printf("\nMMC cannot find device for ucode\n");
293 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
296 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
300 if (!u_qe_upload_firmware(addr))
301 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
302 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
310 void u_qe_resume(void)
314 qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
315 u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
316 out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
322 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
323 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
327 void qe_assign_page(uint snum, uint para_ram_base)
331 out_be32(&qe_immr->cp.cecdr, para_ram_base);
332 out_be32(&qe_immr->cp.cecr, ((u32)snum << QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
333 | QE_CR_FLG | QE_ASSIGN_PAGE);
335 /* Wait for the QE_CR_FLG to clear */
337 cecr = in_be32(&qe_immr->cp.cecr);
338 } while (cecr & QE_CR_FLG);
343 * brg: 0~15 as BRG1~BRG16
345 * BRG input clock comes from the BRGCLK (internal clock generated from
346 * the QE clock, it is one-half of the QE clock), If need the clock source
347 * from CLKn pin, we have te change the function.
350 #define BRG_CLK (gd->arch.brg_clk)
353 int qe_set_brg(uint brg, uint rate)
360 if (brg >= QE_NUM_OF_BRGS)
363 bp = (uint *)&qe_immr->brg.brgc1;
366 divisor = (BRG_CLK / rate);
367 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
375 * *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
376 * __asm__ __volatile__("sync");
379 val = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
381 val |= QE_BRGC_DIV16;
389 /* Set ethernet MII clock master */
390 int qe_set_mii_clk_src(int ucc_num)
394 /* check if the UCC number is in range. */
395 if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
396 printf("%s: ucc num not in ranges\n", __func__);
400 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
401 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
402 cmxgcr |= (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
403 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
408 /* Firmware information stored here for qe_get_firmware_info() */
409 static struct qe_firmware_info qe_firmware_info;
412 * Set to 1 if QE firmware has been uploaded, and therefore
413 * qe_firmware_info contains valid data.
415 static int qe_firmware_uploaded;
418 * Upload a QE microcode
420 * This function is a worker function for qe_upload_firmware(). It does
421 * the actual uploading of the microcode.
423 static void qe_upload_microcode(const void *base,
424 const struct qe_microcode *ucode)
426 const u32 *code = base + be32_to_cpu(ucode->code_offset);
429 if (ucode->major || ucode->minor || ucode->revision)
430 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
431 (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
432 (u16)ucode->revision);
434 printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
436 /* Use auto-increment */
437 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
438 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
440 for (i = 0; i < be32_to_cpu(ucode->count); i++)
441 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
445 * Upload a microcode to the I-RAM at a specific address.
447 * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
448 * information on QE microcode uploading.
450 * Currently, only version 1 is supported, so the 'version' field must be
453 * The SOC model and revision are not validated, they are only displayed for
454 * informational purposes.
456 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
457 * all of the microcode structures, minus the CRC.
459 * 'length' is the size that the structure says it is, including the CRC.
461 int qe_upload_firmware(const struct qe_firmware *firmware)
466 size_t calc_size = sizeof(struct qe_firmware);
468 const struct qe_header *hdr;
469 #ifdef CONFIG_DEEP_SLEEP
470 #ifdef CONFIG_ARCH_LS1021A
471 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
473 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
477 printf("Invalid address\n");
481 hdr = &firmware->header;
482 length = be32_to_cpu(hdr->length);
484 /* Check the magic */
485 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
486 (hdr->magic[2] != 'F')) {
487 printf("QE microcode not found\n");
488 #ifdef CONFIG_DEEP_SLEEP
489 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
494 /* Check the version */
495 if (hdr->version != 1) {
496 printf("Unsupported version\n");
500 /* Validate some of the fields */
501 if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
502 printf("Invalid data\n");
506 /* Validate the length and check if there's a CRC */
507 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
509 for (i = 0; i < firmware->count; i++)
511 * For situations where the second RISC uses the same microcode
512 * as the first, the 'code_offset' and 'count' fields will be
513 * zero, so it's okay to add those.
515 calc_size += sizeof(u32) *
516 be32_to_cpu(firmware->microcode[i].count);
518 /* Validate the length */
519 if (length != calc_size + sizeof(u32)) {
520 printf("Invalid length\n");
525 * Validate the CRC. We would normally call crc32_no_comp(), but that
526 * function isn't available unless you turn on JFFS support.
528 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
529 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
530 printf("Firmware CRC is invalid\n");
535 * If the microcode calls for it, split the I-RAM.
537 if (!firmware->split) {
538 out_be16(&qe_immr->cp.cercr,
539 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
542 if (firmware->soc.model)
543 printf("Firmware '%s' for %u V%u.%u\n",
544 firmware->id, be16_to_cpu(firmware->soc.model),
545 firmware->soc.major, firmware->soc.minor);
547 printf("Firmware '%s'\n", firmware->id);
550 * The QE only supports one microcode per RISC, so clear out all the
551 * saved microcode information and put in the new.
553 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
554 strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
555 qe_firmware_info.extended_modes = firmware->extended_modes;
556 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
557 sizeof(firmware->vtraps));
558 qe_firmware_uploaded = 1;
560 /* Loop through each microcode. */
561 for (i = 0; i < firmware->count; i++) {
562 const struct qe_microcode *ucode = &firmware->microcode[i];
564 /* Upload a microcode if it's present */
565 if (ucode->code_offset)
566 qe_upload_microcode(firmware, ucode);
568 /* Program the traps for this processor */
569 for (j = 0; j < 16; j++) {
570 u32 trap = be32_to_cpu(ucode->traps[j]);
573 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
577 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
585 * Upload a microcode to the I-RAM at a specific address.
587 * See Documentation/powerpc/qe_firmware.rst in the Linux kernel tree for
588 * information on QE microcode uploading.
590 * Currently, only version 1 is supported, so the 'version' field must be
593 * The SOC model and revision are not validated, they are only displayed for
594 * informational purposes.
596 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
597 * all of the microcode structures, minus the CRC.
599 * 'length' is the size that the structure says it is, including the CRC.
601 int u_qe_upload_firmware(const struct qe_firmware *firmware)
606 size_t calc_size = sizeof(struct qe_firmware);
608 const struct qe_header *hdr;
609 #ifdef CONFIG_DEEP_SLEEP
610 #ifdef CONFIG_ARCH_LS1021A
611 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
613 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
617 printf("Invalid address\n");
621 hdr = &firmware->header;
622 length = be32_to_cpu(hdr->length);
624 /* Check the magic */
625 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
626 (hdr->magic[2] != 'F')) {
627 printf("Not a microcode\n");
628 #ifdef CONFIG_DEEP_SLEEP
629 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
634 /* Check the version */
635 if (hdr->version != 1) {
636 printf("Unsupported version\n");
640 /* Validate some of the fields */
641 if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
642 printf("Invalid data\n");
646 /* Validate the length and check if there's a CRC */
647 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
649 for (i = 0; i < firmware->count; i++)
651 * For situations where the second RISC uses the same microcode
652 * as the first, the 'code_offset' and 'count' fields will be
653 * zero, so it's okay to add those.
655 calc_size += sizeof(u32) *
656 be32_to_cpu(firmware->microcode[i].count);
658 /* Validate the length */
659 if (length != calc_size + sizeof(u32)) {
660 printf("Invalid length\n");
665 * Validate the CRC. We would normally call crc32_no_comp(), but that
666 * function isn't available unless you turn on JFFS support.
668 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
669 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
670 printf("Firmware CRC is invalid\n");
675 * If the microcode calls for it, split the I-RAM.
677 if (!firmware->split) {
678 out_be16(&qe_immr->cp.cercr,
679 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
682 if (firmware->soc.model)
683 printf("Firmware '%s' for %u V%u.%u\n",
684 firmware->id, be16_to_cpu(firmware->soc.model),
685 firmware->soc.major, firmware->soc.minor);
687 printf("Firmware '%s'\n", firmware->id);
689 /* Loop through each microcode. */
690 for (i = 0; i < firmware->count; i++) {
691 const struct qe_microcode *ucode = &firmware->microcode[i];
693 /* Upload a microcode if it's present */
694 if (ucode->code_offset)
695 qe_upload_microcode(firmware, ucode);
697 /* Program the traps for this processor */
698 for (j = 0; j < 16; j++) {
699 u32 trap = be32_to_cpu(ucode->traps[j]);
702 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
706 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
714 int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
718 const struct qe_header *hdr;
720 #ifdef CONFIG_DEEP_SLEEP
722 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
724 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
731 hdr = &firmware->header;
733 /* Check the magic */
734 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
735 (hdr->magic[2] != 'F')) {
736 #ifdef CONFIG_DEEP_SLEEP
737 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
743 * If the microcode calls for it, split the I-RAM.
745 if (!firmware->split) {
746 out_be16(&qe_immrr->cp.cercr,
747 in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
750 /* Loop through each microcode. */
751 for (i = 0; i < firmware->count; i++) {
752 const struct qe_microcode *ucode = &firmware->microcode[i];
754 /* Upload a microcode if it's present */
755 if (!ucode->code_offset)
758 code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
760 /* Use auto-increment */
761 out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
762 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
764 for (i = 0; i < be32_to_cpu(ucode->count); i++)
765 out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
767 /* Program the traps for this processor */
768 for (j = 0; j < 16; j++) {
769 u32 trap = be32_to_cpu(ucode->traps[j]);
772 out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
776 out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
783 struct qe_firmware_info *qe_get_firmware_info(void)
785 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
788 static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
793 return cmd_usage(cmdtp);
795 if (strcmp(argv[1], "fw") == 0) {
796 addr = simple_strtoul(argv[2], NULL, 16);
799 printf("Invalid address\n");
804 * If a length was supplied, compare that with the 'length'
809 ulong length = simple_strtoul(argv[3], NULL, 16);
810 struct qe_firmware *firmware = (void *)addr;
812 if (length != be32_to_cpu(firmware->header.length)) {
813 printf("Length mismatch\n");
818 return qe_upload_firmware((const struct qe_firmware *)addr);
821 return cmd_usage(cmdtp);
826 "QUICC Engine commands",
827 "fw <addr> [<length>] - Upload firmware binary at address <addr> to the QE,\n"
828 "\twith optional length <length> verification."