2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
30 qe_map_t *qe_immr = NULL;
31 static qe_snum_t snums[QE_NUM_OF_SNUM];
33 DECLARE_GLOBAL_DATA_PTR;
35 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
39 if (cmd == QE_RESET) {
40 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
42 out_be32(&qe_immr->cp.cecdr, cmd_data);
43 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
44 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
46 /* Wait for the QE_CR_FLG to clear */
48 cecr = in_be32(&qe_immr->cp.cecr);
49 } while (cecr & QE_CR_FLG);
54 uint qe_muram_alloc(uint size, uint align)
60 align_mask = align - 1;
61 savebase = gd->arch.mp_alloc_base;
63 off = gd->arch.mp_alloc_base & align_mask;
65 gd->arch.mp_alloc_base += (align - off);
67 if ((off = size & align_mask) != 0)
68 size += (align - off);
70 if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
71 gd->arch.mp_alloc_base = savebase;
72 printf("%s: ran out of ram.\n", __FUNCTION__);
75 retloc = gd->arch.mp_alloc_base;
76 gd->arch.mp_alloc_base += size;
78 memset((void *)&qe_immr->muram[retloc], 0, size);
80 __asm__ __volatile__("sync");
85 void *qe_muram_addr(uint offset)
87 return (void *)&qe_immr->muram[offset];
90 static void qe_sdma_init(void)
93 uint sdma_buffer_base;
95 p = (volatile sdma_t *)&qe_immr->sdma;
97 /* All of DMA transaction in bus 1 */
98 out_be32(&p->sdaqr, 0);
99 out_be32(&p->sdaqmr, 0);
101 /* Allocate 2KB temporary buffer for sdma */
102 sdma_buffer_base = qe_muram_alloc(2048, 4096);
103 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
105 /* Clear sdma status */
106 out_be32(&p->sdsr, 0x03000000);
108 /* Enable global mode on bus 1, and 2KB buffer size */
109 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
112 /* This table is a list of the serial numbers of the Threads, taken from the
113 * "SNUM Table" chart in the QE Reference Manual. The order is not important,
114 * we just need to know what the SNUMs are for the threads.
116 static u8 thread_snum[] = {
117 /* Evthreads 16-29 are not supported in MPC8309 */
118 #if !defined(CONFIG_MPC8309)
119 0x04, 0x05, 0x0c, 0x0d,
120 0x14, 0x15, 0x1c, 0x1d,
121 0x24, 0x25, 0x2c, 0x2d,
124 0x88, 0x89, 0x98, 0x99,
125 0xa8, 0xa9, 0xb8, 0xb9,
126 0xc8, 0xc9, 0xd8, 0xd9,
127 0xe8, 0xe9, 0x08, 0x09,
128 0x18, 0x19, 0x28, 0x29,
129 0x38, 0x39, 0x48, 0x49,
130 0x58, 0x59, 0x68, 0x69,
131 0x78, 0x79, 0x80, 0x81
134 static void qe_snums_init(void)
138 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
139 snums[i].state = QE_SNUM_STATE_FREE;
140 snums[i].num = thread_snum[i];
144 int qe_get_snum(void)
149 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
150 if (snums[i].state == QE_SNUM_STATE_FREE) {
151 snums[i].state = QE_SNUM_STATE_USED;
160 void qe_put_snum(u8 snum)
164 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
165 if (snums[i].num == snum) {
166 snums[i].state = QE_SNUM_STATE_FREE;
172 void qe_init(uint qe_base)
174 /* Init the QE IMMR base */
175 qe_immr = (qe_map_t *)qe_base;
177 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
179 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
181 qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
183 /* enable the microcode in IRAM */
184 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
187 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
188 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
196 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
197 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
200 void qe_assign_page(uint snum, uint para_ram_base)
204 out_be32(&qe_immr->cp.cecdr, para_ram_base);
205 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
206 | QE_CR_FLG | QE_ASSIGN_PAGE);
208 /* Wait for the QE_CR_FLG to clear */
210 cecr = in_be32(&qe_immr->cp.cecr);
211 } while (cecr & QE_CR_FLG );
217 * brg: 0~15 as BRG1~BRG16
219 * BRG input clock comes from the BRGCLK (internal clock generated from
220 the QE clock, it is one-half of the QE clock), If need the clock source
221 from CLKn pin, we have te change the function.
224 #define BRG_CLK (gd->arch.brg_clk)
226 int qe_set_brg(uint brg, uint rate)
232 if (brg >= QE_NUM_OF_BRGS)
234 bp = (uint *)&qe_immr->brg.brgc1;
237 divisor = (BRG_CLK / rate);
238 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
243 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
244 __asm__ __volatile__("sync");
247 *bp |= QE_BRGC_DIV16;
248 __asm__ __volatile__("sync");
254 /* Set ethernet MII clock master
256 int qe_set_mii_clk_src(int ucc_num)
260 /* check if the UCC number is in range. */
261 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
262 printf("%s: ucc num not in ranges\n", __FUNCTION__);
266 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
267 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
268 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
269 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
274 /* Firmware information stored here for qe_get_firmware_info() */
275 static struct qe_firmware_info qe_firmware_info;
278 * Set to 1 if QE firmware has been uploaded, and therefore
279 * qe_firmware_info contains valid data.
281 static int qe_firmware_uploaded;
284 * Upload a QE microcode
286 * This function is a worker function for qe_upload_firmware(). It does
287 * the actual uploading of the microcode.
289 static void qe_upload_microcode(const void *base,
290 const struct qe_microcode *ucode)
292 const u32 *code = base + be32_to_cpu(ucode->code_offset);
295 if (ucode->major || ucode->minor || ucode->revision)
296 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
297 ucode->id, ucode->major, ucode->minor, ucode->revision);
299 printf("QE: uploading microcode '%s'\n", ucode->id);
301 /* Use auto-increment */
302 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
303 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
305 for (i = 0; i < be32_to_cpu(ucode->count); i++)
306 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
310 * Upload a microcode to the I-RAM at a specific address.
312 * See docs/README.qe_firmware for information on QE microcode uploading.
314 * Currently, only version 1 is supported, so the 'version' field must be
317 * The SOC model and revision are not validated, they are only displayed for
318 * informational purposes.
320 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
321 * all of the microcode structures, minus the CRC.
323 * 'length' is the size that the structure says it is, including the CRC.
325 int qe_upload_firmware(const struct qe_firmware *firmware)
330 size_t calc_size = sizeof(struct qe_firmware);
332 const struct qe_header *hdr;
335 printf("Invalid address\n");
339 hdr = &firmware->header;
340 length = be32_to_cpu(hdr->length);
342 /* Check the magic */
343 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
344 (hdr->magic[2] != 'F')) {
345 printf("Not a microcode\n");
349 /* Check the version */
350 if (hdr->version != 1) {
351 printf("Unsupported version\n");
355 /* Validate some of the fields */
356 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
357 printf("Invalid data\n");
361 /* Validate the length and check if there's a CRC */
362 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
364 for (i = 0; i < firmware->count; i++)
366 * For situations where the second RISC uses the same microcode
367 * as the first, the 'code_offset' and 'count' fields will be
368 * zero, so it's okay to add those.
370 calc_size += sizeof(u32) *
371 be32_to_cpu(firmware->microcode[i].count);
373 /* Validate the length */
374 if (length != calc_size + sizeof(u32)) {
375 printf("Invalid length\n");
380 * Validate the CRC. We would normally call crc32_no_comp(), but that
381 * function isn't available unless you turn on JFFS support.
383 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
384 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
385 printf("Firmware CRC is invalid\n");
390 * If the microcode calls for it, split the I-RAM.
392 if (!firmware->split) {
393 out_be16(&qe_immr->cp.cercr,
394 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
397 if (firmware->soc.model)
398 printf("Firmware '%s' for %u V%u.%u\n",
399 firmware->id, be16_to_cpu(firmware->soc.model),
400 firmware->soc.major, firmware->soc.minor);
402 printf("Firmware '%s'\n", firmware->id);
405 * The QE only supports one microcode per RISC, so clear out all the
406 * saved microcode information and put in the new.
408 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
409 strcpy(qe_firmware_info.id, (char *)firmware->id);
410 qe_firmware_info.extended_modes = firmware->extended_modes;
411 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
412 sizeof(firmware->vtraps));
413 qe_firmware_uploaded = 1;
415 /* Loop through each microcode. */
416 for (i = 0; i < firmware->count; i++) {
417 const struct qe_microcode *ucode = &firmware->microcode[i];
419 /* Upload a microcode if it's present */
420 if (ucode->code_offset)
421 qe_upload_microcode(firmware, ucode);
423 /* Program the traps for this processor */
424 for (j = 0; j < 16; j++) {
425 u32 trap = be32_to_cpu(ucode->traps[j]);
428 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
432 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
438 struct qe_firmware_info *qe_get_firmware_info(void)
440 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
443 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
448 return cmd_usage(cmdtp);
450 if (strcmp(argv[1], "fw") == 0) {
451 addr = simple_strtoul(argv[2], NULL, 16);
454 printf("Invalid address\n");
459 * If a length was supplied, compare that with the 'length'
464 ulong length = simple_strtoul(argv[3], NULL, 16);
465 struct qe_firmware *firmware = (void *) addr;
467 if (length != be32_to_cpu(firmware->header.length)) {
468 printf("Length mismatch\n");
473 return qe_upload_firmware((const struct qe_firmware *) addr);
476 return cmd_usage(cmdtp);
481 "QUICC Engine commands",
482 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
484 "\twith optional length <length> verification."