drivers/pwm/sunxi_pwm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <pwm.h>
  11 #include <regmap.h>
  12 #include <syscon.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/pwm.h>
  16 #include <power/regulator.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #define OSC_24MHZ 24000000
  21
  22 struct sunxi_pwm_priv {
  23         struct sunxi_pwm *regs;
  24         bool invert;
  25         u32 prescaler;
  26 };
  27
  28 static const u32 prescaler_table[] = {
  29         120,    /* 0000 */
  30         180,    /* 0001 */
  31         240,    /* 0010 */
  32         360,    /* 0011 */
  33         480,    /* 0100 */
  34         0,      /* 0101 */
  35         0,      /* 0110 */
  36         0,      /* 0111 */
  37         12000,  /* 1000 */
  38         24000,  /* 1001 */
  39         36000,  /* 1010 */
  40         48000,  /* 1011 */
  41         72000,  /* 1100 */
  42         0,      /* 1101 */
  43         0,      /* 1110 */
  44         1,      /* 1111 */
  45 };
  46
  47 static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
  48                                 bool polarity)
  49 {
  50         struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  51
  52         debug("%s: polarity=%u\n", __func__, polarity);
  53         priv->invert = polarity;
  54
  55         return 0;
  56 }
  57
  58 static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
  59                                 uint period_ns, uint duty_ns)
  60 {
  61         struct sunxi_pwm_priv *priv = dev_get_priv(dev);
  62         struct sunxi_pwm *regs = priv->regs;
  63         int best_prescaler = 0;
  64         u32 v, best_period = 0, duty;
  65         u64 best_scaled_freq = 0;
  66         const u32 nsecs_per_sec = 1000000000U;
  67
  68         debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  69
  70         for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
  71              prescaler++) {
  72                 u32 period = 0;
  73                 u64 scaled_freq = 0;
  74                 if (!prescaler_table[prescaler])
  75                         continue;
  76                 scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
  77                 period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
  78                 if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
  79                     best_period < period) {
  80                         best_period = period;
  81                         best_scaled_freq = scaled_freq;
  82                         best_prescaler = prescaler;
  83                 }
  84         }
  85
  86         if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
  87                 debug("%s: failed to find prescaler value\n", __func__);
  88                 return -EINVAL;
  89         }
  90
  91         duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
  92
  93         if (priv->prescaler != best_prescaler) {
  94                 /* Mask clock to update prescaler */
  95                 v = readl(&regs->ctrl);
  96                 v &= ~SUNXI_PWM_CTRL_CLK_GATE;
  97                 writel(v, &regs->ctrl);
  98                 v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
  99                 v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
 100                 writel(v, &regs->ctrl);
 101                 v |= SUNXI_PWM_CTRL_CLK_GATE;
 102                 writel(v, &regs->ctrl);
 103                 priv->prescaler = best_prescaler;
 104         }
 105
 106         writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
 107                SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
 108
 109         debug("%s: prescaler: %d, period: %d, duty: %d\n",
 110               __func__, priv->prescaler,
 111               best_period, duty);
 112
 113         return 0;
 114 }
 115
 116 static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 117 {
 118         struct sunxi_pwm_priv *priv = dev_get_priv(dev);
 119         struct sunxi_pwm *regs = priv->regs;
 120         u32 v;
 121
 122         debug("%s: Enable '%s'\n", __func__, dev->name);
 123
 124         v = readl(&regs->ctrl);
 125         if (!enable) {
 126                 v &= ~SUNXI_PWM_CTRL_ENABLE0;
 127                 writel(v, &regs->ctrl);
 128                 return 0;
 129         }
 130
 131         if (priv->invert)
 132                 v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
 133         else
 134                 v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
 135         v |= SUNXI_PWM_CTRL_ENABLE0;
 136         writel(v, &regs->ctrl);
 137
 138         return 0;
 139 }
 140
 141 static int sunxi_pwm_of_to_plat(struct udevice *dev)
 142 {
 143         struct sunxi_pwm_priv *priv = dev_get_priv(dev);
 144
 145         priv->regs = dev_read_addr_ptr(dev);
 146
 147         return 0;
 148 }
 149
 150 static int sunxi_pwm_probe(struct udevice *dev)
 151 {
 152         return 0;
 153 }
 154
 155 static const struct pwm_ops sunxi_pwm_ops = {
 156         .set_invert     = sunxi_pwm_set_invert,
 157         .set_config     = sunxi_pwm_set_config,
 158         .set_enable     = sunxi_pwm_set_enable,
 159 };
 160
 161 static const struct udevice_id sunxi_pwm_ids[] = {
 162         { .compatible = "allwinner,sun5i-a13-pwm" },
 163         { .compatible = "allwinner,sun50i-a64-pwm" },
 164         { }
 165 };
 166
 167 U_BOOT_DRIVER(sunxi_pwm) = {
 168         .name   = "sunxi_pwm",
 169         .id     = UCLASS_PWM,
 170         .of_match = sunxi_pwm_ids,
 171         .ops    = &sunxi_pwm_ops,
 172         .of_to_plat     = sunxi_pwm_of_to_plat,
 173         .probe          = sunxi_pwm_probe,
 174         .priv_auto      = sizeof(struct sunxi_pwm_priv),
 175 };