drivers/pwm/rk_pwm.c

   1 /*
   2  * Copyright (c) 2016 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <pwm.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/grf_rk3288.h>
  18 #include <asm/arch/pwm.h>
  19 #include <asm/arch/hardware.h>
  20 #include <power/regulator.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk_pwm_priv {
  25         struct rk3288_pwm *regs;
  26         struct rk3288_grf *grf;
  27         ulong freq;
  28 };
  29
  30 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  31                              uint duty_ns)
  32 {
  33         struct rk_pwm_priv *priv = dev_get_priv(dev);
  34         struct rk3288_pwm *regs = priv->regs;
  35         unsigned long period, duty;
  36
  37         debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  38         writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
  39                 PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
  40                 RK_PWM_DISABLE,
  41                 &regs->ctrl);
  42
  43         period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
  44         duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
  45
  46         writel(period, &regs->period_hpr);
  47         writel(duty, &regs->duty_lpr);
  48         debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  49
  50         return 0;
  51 }
  52
  53 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  54 {
  55         struct rk_pwm_priv *priv = dev_get_priv(dev);
  56         struct rk3288_pwm *regs = priv->regs;
  57
  58         debug("%s: Enable '%s'\n", __func__, dev->name);
  59         clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
  60
  61         return 0;
  62 }
  63
  64 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  65 {
  66         struct rk_pwm_priv *priv = dev_get_priv(dev);
  67         struct regmap *map;
  68
  69         priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
  70         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
  71         if (IS_ERR(map))
  72                 return PTR_ERR(map);
  73         priv->grf = regmap_get_range(map, 0);
  74
  75         return 0;
  76 }
  77
  78 static int rk_pwm_probe(struct udevice *dev)
  79 {
  80         struct rk_pwm_priv *priv = dev_get_priv(dev);
  81         struct clk clk;
  82         int ret = 0;
  83
  84         rk_setreg(&priv->grf->soc_con2, 1 << 0);
  85
  86         ret = clk_get_by_index(dev, 0, &clk);
  87         if (ret < 0) {
  88                 debug("%s get clock fail!\n", __func__);
  89                 return -EINVAL;
  90         }
  91         priv->freq = clk_get_rate(&clk);
  92
  93         return 0;
  94 }
  95
  96 static const struct pwm_ops rk_pwm_ops = {
  97         .set_config     = rk_pwm_set_config,
  98         .set_enable     = rk_pwm_set_enable,
  99 };
 100
 101 static const struct udevice_id rk_pwm_ids[] = {
 102         { .compatible = "rockchip,rk3288-pwm" },
 103         { }
 104 };
 105
 106 U_BOOT_DRIVER(rk_pwm) = {
 107         .name   = "rk_pwm",
 108         .id     = UCLASS_PWM,
 109         .of_match = rk_pwm_ids,
 110         .ops    = &rk_pwm_ops,
 111         .ofdata_to_platdata     = rk_pwm_ofdata_to_platdata,
 112         .probe          = rk_pwm_probe,
 113         .priv_auto_alloc_size   = sizeof(struct rk_pwm_priv),
 114 };