drivers/pwm/rk_pwm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <pwm.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-rockchip/pwm.h>
  18 #include <linux/bitops.h>
  19 #include <power/regulator.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct rockchip_pwm_data {
  24         struct rockchip_pwm_regs regs;
  25         unsigned int prescaler;
  26         bool supports_polarity;
  27         bool supports_lock;
  28         u32 enable_conf;
  29         u32 enable_conf_mask;
  30 };
  31
  32 struct rk_pwm_priv {
  33         fdt_addr_t base;
  34         ulong freq;
  35         u32 conf_polarity;
  36         const struct rockchip_pwm_data *data;
  37 };
  38
  39 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  40 {
  41         struct rk_pwm_priv *priv = dev_get_priv(dev);
  42
  43         if (!priv->data->supports_polarity) {
  44                 debug("%s: Do not support polarity\n", __func__);
  45                 return 0;
  46         }
  47
  48         debug("%s: polarity=%u\n", __func__, polarity);
  49         if (polarity)
  50                 priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
  51         else
  52                 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  53
  54         return 0;
  55 }
  56
  57 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  58                              uint duty_ns)
  59 {
  60         struct rk_pwm_priv *priv = dev_get_priv(dev);
  61         const struct rockchip_pwm_regs *regs = &priv->data->regs;
  62         unsigned long period, duty;
  63         u32 ctrl;
  64
  65         debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  66
  67         ctrl = readl(priv->base + regs->ctrl);
  68         /*
  69          * Lock the period and duty of previous configuration, then
  70          * change the duty and period, that would not be effective.
  71          */
  72         if (priv->data->supports_lock) {
  73                 ctrl |= PWM_LOCK;
  74                 writel(ctrl, priv->base + regs->ctrl);
  75         }
  76
  77         period = lldiv((uint64_t)priv->freq * period_ns,
  78                        priv->data->prescaler * 1000000000);
  79         duty = lldiv((uint64_t)priv->freq * duty_ns,
  80                      priv->data->prescaler * 1000000000);
  81
  82         writel(period, priv->base + regs->period);
  83         writel(duty, priv->base + regs->duty);
  84
  85         if (priv->data->supports_polarity) {
  86                 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
  87                 ctrl |= priv->conf_polarity;
  88         }
  89
  90         /*
  91          * Unlock and set polarity at the same time,
  92          * the configuration of duty, period and polarity
  93          * would be effective together at next period.
  94          */
  95         if (priv->data->supports_lock)
  96                 ctrl &= ~PWM_LOCK;
  97         writel(ctrl, priv->base + regs->ctrl);
  98
  99         debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
 100
 101         return 0;
 102 }
 103
 104 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 105 {
 106         struct rk_pwm_priv *priv = dev_get_priv(dev);
 107         const struct rockchip_pwm_regs *regs = &priv->data->regs;
 108         u32 ctrl;
 109
 110         debug("%s: Enable '%s'\n", __func__, dev->name);
 111
 112         ctrl = readl(priv->base + regs->ctrl);
 113         ctrl &= ~priv->data->enable_conf_mask;
 114
 115         if (enable)
 116                 ctrl |= priv->data->enable_conf;
 117         else
 118                 ctrl &= ~priv->data->enable_conf;
 119
 120         writel(ctrl, priv->base + regs->ctrl);
 121
 122         return 0;
 123 }
 124
 125 static int rk_pwm_of_to_plat(struct udevice *dev)
 126 {
 127         struct rk_pwm_priv *priv = dev_get_priv(dev);
 128
 129         priv->base = dev_read_addr(dev);
 130
 131         return 0;
 132 }
 133
 134 static int rk_pwm_probe(struct udevice *dev)
 135 {
 136         struct rk_pwm_priv *priv = dev_get_priv(dev);
 137         struct clk clk;
 138         int ret = 0;
 139
 140         ret = clk_get_by_index(dev, 0, &clk);
 141         if (ret < 0) {
 142                 debug("%s get clock fail!\n", __func__);
 143                 return -EINVAL;
 144         }
 145
 146         priv->freq = clk_get_rate(&clk);
 147         priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
 148
 149         if (priv->data->supports_polarity)
 150                 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
 151
 152         return 0;
 153 }
 154
 155 static const struct pwm_ops rk_pwm_ops = {
 156         .set_invert     = rk_pwm_set_invert,
 157         .set_config     = rk_pwm_set_config,
 158         .set_enable     = rk_pwm_set_enable,
 159 };
 160
 161 static const struct rockchip_pwm_data pwm_data_v1 = {
 162         .regs = {
 163                 .duty = 0x04,
 164                 .period = 0x08,
 165                 .cntr = 0x00,
 166                 .ctrl = 0x0c,
 167         },
 168         .prescaler = 2,
 169         .supports_polarity = false,
 170         .supports_lock = false,
 171         .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
 172         .enable_conf_mask = BIT(1) | BIT(3),
 173 };
 174
 175 static const struct rockchip_pwm_data pwm_data_v2 = {
 176         .regs = {
 177                 .duty = 0x08,
 178                 .period = 0x04,
 179                 .cntr = 0x00,
 180                 .ctrl = 0x0c,
 181         },
 182         .prescaler = 1,
 183         .supports_polarity = true,
 184         .supports_lock = false,
 185         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
 186                        PWM_CONTINUOUS,
 187         .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
 188 };
 189
 190 static const struct rockchip_pwm_data pwm_data_v3 = {
 191         .regs = {
 192                 .duty = 0x08,
 193                 .period = 0x04,
 194                 .cntr = 0x00,
 195                 .ctrl = 0x0c,
 196         },
 197         .prescaler = 1,
 198         .supports_polarity = true,
 199         .supports_lock = true,
 200         .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
 201                        PWM_CONTINUOUS,
 202         .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
 203 };
 204
 205 static const struct udevice_id rk_pwm_ids[] = {
 206         { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
 207         { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
 208         { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
 209         { }
 210 };
 211
 212 U_BOOT_DRIVER(rk_pwm) = {
 213         .name   = "rk_pwm",
 214         .id     = UCLASS_PWM,
 215         .of_match = rk_pwm_ids,
 216         .ops    = &rk_pwm_ops,
 217         .of_to_plat     = rk_pwm_of_to_plat,
 218         .probe          = rk_pwm_probe,
 219         .priv_auto      = sizeof(struct rk_pwm_priv),
 220 };