1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <asm/global_data.h>
17 #include <asm/arch-rockchip/pwm.h>
18 #include <linux/bitops.h>
19 #include <power/regulator.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct rockchip_pwm_data {
24 struct rockchip_pwm_regs regs;
25 unsigned int prescaler;
26 bool supports_polarity;
36 const struct rockchip_pwm_data *data;
39 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
41 struct rk_pwm_priv *priv = dev_get_priv(dev);
43 if (!priv->data->supports_polarity) {
44 debug("%s: Do not support polarity\n", __func__);
48 debug("%s: polarity=%u\n", __func__, polarity);
50 priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
52 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
57 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
60 struct rk_pwm_priv *priv = dev_get_priv(dev);
61 const struct rockchip_pwm_regs *regs = &priv->data->regs;
62 unsigned long period, duty;
65 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
67 ctrl = readl(priv->base + regs->ctrl);
69 * Lock the period and duty of previous configuration, then
70 * change the duty and period, that would not be effective.
72 if (priv->data->supports_lock) {
74 writel(ctrl, priv->base + regs->ctrl);
77 period = lldiv((uint64_t)priv->freq * period_ns,
78 priv->data->prescaler * 1000000000);
79 duty = lldiv((uint64_t)priv->freq * duty_ns,
80 priv->data->prescaler * 1000000000);
82 writel(period, priv->base + regs->period);
83 writel(duty, priv->base + regs->duty);
85 if (priv->data->supports_polarity) {
86 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
87 ctrl |= priv->conf_polarity;
91 * Unlock and set polarity at the same time,
92 * the configuration of duty, period and polarity
93 * would be effective together at next period.
95 if (priv->data->supports_lock)
97 writel(ctrl, priv->base + regs->ctrl);
99 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
104 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
106 struct rk_pwm_priv *priv = dev_get_priv(dev);
107 const struct rockchip_pwm_regs *regs = &priv->data->regs;
110 debug("%s: Enable '%s'\n", __func__, dev->name);
112 ctrl = readl(priv->base + regs->ctrl);
113 ctrl &= ~priv->data->enable_conf_mask;
116 ctrl |= priv->data->enable_conf;
118 ctrl &= ~priv->data->enable_conf;
120 writel(ctrl, priv->base + regs->ctrl);
125 static int rk_pwm_of_to_plat(struct udevice *dev)
127 struct rk_pwm_priv *priv = dev_get_priv(dev);
129 priv->base = dev_read_addr(dev);
134 static int rk_pwm_probe(struct udevice *dev)
136 struct rk_pwm_priv *priv = dev_get_priv(dev);
140 ret = clk_get_by_index(dev, 0, &clk);
142 debug("%s get clock fail!\n", __func__);
146 priv->freq = clk_get_rate(&clk);
147 priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
149 if (priv->data->supports_polarity)
150 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
155 static const struct pwm_ops rk_pwm_ops = {
156 .set_invert = rk_pwm_set_invert,
157 .set_config = rk_pwm_set_config,
158 .set_enable = rk_pwm_set_enable,
161 static const struct rockchip_pwm_data pwm_data_v1 = {
169 .supports_polarity = false,
170 .supports_lock = false,
171 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
172 .enable_conf_mask = BIT(1) | BIT(3),
175 static const struct rockchip_pwm_data pwm_data_v2 = {
183 .supports_polarity = true,
184 .supports_lock = false,
185 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
187 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
190 static const struct rockchip_pwm_data pwm_data_v3 = {
198 .supports_polarity = true,
199 .supports_lock = true,
200 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
202 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
205 static const struct udevice_id rk_pwm_ids[] = {
206 { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
207 { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
208 { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
212 U_BOOT_DRIVER(rk_pwm) = {
215 .of_match = rk_pwm_ids,
217 .of_to_plat = rk_pwm_of_to_plat,
218 .probe = rk_pwm_probe,
219 .priv_auto = sizeof(struct rk_pwm_priv),