4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
24 #include <linux/err.h>
25 #include <linux/clk.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pwm.h>
28 #include <linux/of_device.h>
29 #include <linux/pinctrl/consumer.h>
31 #include "pwm-tipwmss.h"
33 /* ECAP registers and bits definitions */
39 #define ECCTL2_APWM_POL_LOW BIT(10)
40 #define ECCTL2_APWM_MODE BIT(9)
41 #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
42 #define ECCTL2_TSCTR_FREERUN BIT(4)
44 struct ecap_pwm_chip {
46 unsigned int clk_rate;
47 void __iomem *mmio_base;
50 static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
52 return container_of(chip, struct ecap_pwm_chip, chip);
56 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
57 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
59 static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
60 int duty_ns, int period_ns)
62 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
64 unsigned long period_cycles, duty_cycles;
67 if (period_ns > NSEC_PER_SEC)
72 do_div(c, NSEC_PER_SEC);
73 period_cycles = (unsigned long)c;
75 if (period_cycles < 1) {
81 do_div(c, NSEC_PER_SEC);
82 duty_cycles = (unsigned long)c;
85 pm_runtime_get_sync(pc->chip.dev);
87 reg_val = readw(pc->mmio_base + ECCTL2);
89 /* Configure APWM mode & disable sync option */
90 reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
92 writew(reg_val, pc->mmio_base + ECCTL2);
94 if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
95 /* Update active registers if not running */
96 writel(duty_cycles, pc->mmio_base + CAP2);
97 writel(period_cycles, pc->mmio_base + CAP1);
100 * Update shadow registers to configure period and
101 * compare values. This helps current PWM period to
102 * complete on reconfiguring
104 writel(duty_cycles, pc->mmio_base + CAP4);
105 writel(period_cycles, pc->mmio_base + CAP3);
108 if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
109 reg_val = readw(pc->mmio_base + ECCTL2);
110 /* Disable APWM mode to put APWM output Low */
111 reg_val &= ~ECCTL2_APWM_MODE;
112 writew(reg_val, pc->mmio_base + ECCTL2);
115 pm_runtime_put_sync(pc->chip.dev);
119 static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
120 enum pwm_polarity polarity)
122 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
123 unsigned short reg_val;
125 pm_runtime_get_sync(pc->chip.dev);
126 reg_val = readw(pc->mmio_base + ECCTL2);
127 if (polarity == PWM_POLARITY_INVERSED)
128 /* Duty cycle defines LOW period of PWM */
129 reg_val |= ECCTL2_APWM_POL_LOW;
131 /* Duty cycle defines HIGH period of PWM */
132 reg_val &= ~ECCTL2_APWM_POL_LOW;
134 writew(reg_val, pc->mmio_base + ECCTL2);
135 pm_runtime_put_sync(pc->chip.dev);
139 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
141 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
142 unsigned int reg_val;
144 /* Leave clock enabled on enabling PWM */
145 pm_runtime_get_sync(pc->chip.dev);
148 * Enable 'Free run Time stamp counter mode' to start counter
149 * and 'APWM mode' to enable APWM output
151 reg_val = readw(pc->mmio_base + ECCTL2);
152 reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
153 writew(reg_val, pc->mmio_base + ECCTL2);
157 static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
159 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
160 unsigned int reg_val;
163 * Disable 'Free run Time stamp counter mode' to stop counter
164 * and 'APWM mode' to put APWM output to low
166 reg_val = readw(pc->mmio_base + ECCTL2);
167 reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
168 writew(reg_val, pc->mmio_base + ECCTL2);
170 /* Disable clock on PWM disable */
171 pm_runtime_put_sync(pc->chip.dev);
174 static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
176 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
177 dev_warn(chip->dev, "Removing PWM device without disabling\n");
178 pm_runtime_put_sync(chip->dev);
182 static const struct pwm_ops ecap_pwm_ops = {
183 .free = ecap_pwm_free,
184 .config = ecap_pwm_config,
185 .set_polarity = ecap_pwm_set_polarity,
186 .enable = ecap_pwm_enable,
187 .disable = ecap_pwm_disable,
188 .owner = THIS_MODULE,
191 static const struct of_device_id ecap_of_match[] = {
192 { .compatible = "ti,am33xx-ecap" },
195 MODULE_DEVICE_TABLE(of, ecap_of_match);
197 static int ecap_pwm_probe(struct platform_device *pdev)
202 struct ecap_pwm_chip *pc;
204 struct pinctrl *pinctrl;
206 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
208 dev_warn(&pdev->dev, "unable to select pin group\n");
210 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
212 dev_err(&pdev->dev, "failed to allocate memory\n");
216 clk = devm_clk_get(&pdev->dev, "fck");
218 dev_err(&pdev->dev, "failed to get clock\n");
222 pc->clk_rate = clk_get_rate(clk);
224 dev_err(&pdev->dev, "failed to get clock rate\n");
228 pc->chip.dev = &pdev->dev;
229 pc->chip.ops = &ecap_pwm_ops;
230 pc->chip.of_xlate = of_pwm_xlate_with_flags;
231 pc->chip.of_pwm_n_cells = 3;
235 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
237 dev_err(&pdev->dev, "no memory resource defined\n");
241 pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
243 return -EADDRNOTAVAIL;
245 ret = pwmchip_add(&pc->chip);
247 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
251 pm_runtime_enable(&pdev->dev);
252 pm_runtime_get_sync(&pdev->dev);
254 status = pwmss_submodule_state_change(pdev->dev.parent,
256 if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
257 dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
259 goto pwmss_clk_failure;
262 pm_runtime_put_sync(&pdev->dev);
264 platform_set_drvdata(pdev, pc);
268 pm_runtime_put_sync(&pdev->dev);
269 pm_runtime_disable(&pdev->dev);
270 pwmchip_remove(&pc->chip);
274 static int ecap_pwm_remove(struct platform_device *pdev)
276 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
278 pm_runtime_get_sync(&pdev->dev);
280 * Due to hardware misbehaviour, acknowledge of the stop_req
281 * is missing. Hence checking of the status bit skipped.
283 pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
284 pm_runtime_put_sync(&pdev->dev);
286 pm_runtime_put_sync(&pdev->dev);
287 pm_runtime_disable(&pdev->dev);
288 return pwmchip_remove(&pc->chip);
291 static struct platform_driver ecap_pwm_driver = {
294 .owner = THIS_MODULE,
295 .of_match_table = ecap_of_match,
297 .probe = ecap_pwm_probe,
298 .remove = ecap_pwm_remove,
301 module_platform_driver(ecap_pwm_driver);
303 MODULE_DESCRIPTION("ECAP PWM driver");
304 MODULE_AUTHOR("Texas Instruments");
305 MODULE_LICENSE("GPL");