Merge tag 'for-6.2-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[platform/kernel/linux-starfive.git] / drivers / pwm / pwm-sunplus.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * PWM device driver for SUNPLUS SP7021 SoC
4  *
5  * Links:
6  *   Reference Manual:
7  *   https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
8  *
9  *   Reference Manual(PWM module):
10  *   https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
11  *
12  * Limitations:
13  * - Only supports normal polarity.
14  * - It output low when PWM channel disabled.
15  * - When the parameters change, current running period will not be completed
16  *     and run new settings immediately.
17  * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
18  *     done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
19  *
20  * Author: Hammer Hsieh <hammerh0314@gmail.com>
21  */
22 #include <linux/bitfield.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/pwm.h>
29
30 #define SP7021_PWM_MODE0                0x000
31 #define SP7021_PWM_MODE0_PWMEN(ch)      BIT(ch)
32 #define SP7021_PWM_MODE0_BYPASS(ch)     BIT(8 + (ch))
33 #define SP7021_PWM_MODE1                0x004
34 #define SP7021_PWM_MODE1_CNT_EN(ch)     BIT(ch)
35 #define SP7021_PWM_FREQ(ch)             (0x008 + 4 * (ch))
36 #define SP7021_PWM_FREQ_MAX             GENMASK(15, 0)
37 #define SP7021_PWM_DUTY(ch)             (0x018 + 4 * (ch))
38 #define SP7021_PWM_DUTY_DD_SEL(ch)      FIELD_PREP(GENMASK(9, 8), ch)
39 #define SP7021_PWM_DUTY_MAX             GENMASK(7, 0)
40 #define SP7021_PWM_DUTY_MASK            SP7021_PWM_DUTY_MAX
41 #define SP7021_PWM_FREQ_SCALER          256
42 #define SP7021_PWM_NUM                  4
43
44 struct sunplus_pwm {
45         struct pwm_chip chip;
46         void __iomem *base;
47         struct clk *clk;
48 };
49
50 static inline struct sunplus_pwm *to_sunplus_pwm(struct pwm_chip *chip)
51 {
52         return container_of(chip, struct sunplus_pwm, chip);
53 }
54
55 static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
56                              const struct pwm_state *state)
57 {
58         struct sunplus_pwm *priv = to_sunplus_pwm(chip);
59         u32 dd_freq, duty, mode0, mode1;
60         u64 clk_rate;
61
62         if (state->polarity != pwm->state.polarity)
63                 return -EINVAL;
64
65         if (!state->enabled) {
66                 /* disable pwm channel output */
67                 mode0 = readl(priv->base + SP7021_PWM_MODE0);
68                 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
69                 writel(mode0, priv->base + SP7021_PWM_MODE0);
70                 /* disable pwm channel clk source */
71                 mode1 = readl(priv->base + SP7021_PWM_MODE1);
72                 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
73                 writel(mode1, priv->base + SP7021_PWM_MODE1);
74                 return 0;
75         }
76
77         clk_rate = clk_get_rate(priv->clk);
78
79         /*
80          * The following calculations might overflow if clk is bigger
81          * than 256 GHz. In practise it's 202.5MHz, so this limitation
82          * is only theoretic.
83          */
84         if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC)
85                 return -EINVAL;
86
87         /*
88          * With clk_rate limited above we have dd_freq <= state->period,
89          * so this cannot overflow.
90          */
91         dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
92                                 * NSEC_PER_SEC);
93
94         if (dd_freq == 0)
95                 return -EINVAL;
96
97         if (dd_freq > SP7021_PWM_FREQ_MAX)
98                 dd_freq = SP7021_PWM_FREQ_MAX;
99
100         writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
101
102         /* cal and set pwm duty */
103         mode0 = readl(priv->base + SP7021_PWM_MODE0);
104         mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
105         mode1 = readl(priv->base + SP7021_PWM_MODE1);
106         mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
107         if (state->duty_cycle == state->period) {
108                 /* PWM channel output = high */
109                 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
110                 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX;
111         } else {
112                 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
113                 /*
114                  * duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow.
115                  */
116                 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
117                                            (u64)dd_freq * NSEC_PER_SEC);
118                 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty;
119         }
120         writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
121         writel(mode1, priv->base + SP7021_PWM_MODE1);
122         writel(mode0, priv->base + SP7021_PWM_MODE0);
123
124         return 0;
125 }
126
127 static int sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
128                                  struct pwm_state *state)
129 {
130         struct sunplus_pwm *priv = to_sunplus_pwm(chip);
131         u32 mode0, dd_freq, duty;
132         u64 clk_rate;
133
134         mode0 = readl(priv->base + SP7021_PWM_MODE0);
135
136         if (mode0 & BIT(pwm->hwpwm)) {
137                 clk_rate = clk_get_rate(priv->clk);
138                 dd_freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
139                 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
140                 duty = FIELD_GET(SP7021_PWM_DUTY_MASK, duty);
141                 /*
142                  * dd_freq 16 bits, SP7021_PWM_FREQ_SCALER 8 bits
143                  * NSEC_PER_SEC 30 bits, won't overflow.
144                  */
145                 state->period = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)SP7021_PWM_FREQ_SCALER
146                                                 * NSEC_PER_SEC, clk_rate);
147                 /*
148                  * dd_freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow.
149                  */
150                 state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,
151                                                        clk_rate);
152                 state->enabled = true;
153         } else {
154                 state->enabled = false;
155         }
156
157         state->polarity = PWM_POLARITY_NORMAL;
158
159         return 0;
160 }
161
162 static const struct pwm_ops sunplus_pwm_ops = {
163         .apply = sunplus_pwm_apply,
164         .get_state = sunplus_pwm_get_state,
165         .owner = THIS_MODULE,
166 };
167
168 static void sunplus_pwm_clk_release(void *data)
169 {
170         struct clk *clk = data;
171
172         clk_disable_unprepare(clk);
173 }
174
175 static int sunplus_pwm_probe(struct platform_device *pdev)
176 {
177         struct device *dev = &pdev->dev;
178         struct sunplus_pwm *priv;
179         int ret;
180
181         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
182         if (!priv)
183                 return -ENOMEM;
184
185         priv->base = devm_platform_ioremap_resource(pdev, 0);
186         if (IS_ERR(priv->base))
187                 return PTR_ERR(priv->base);
188
189         priv->clk = devm_clk_get(dev, NULL);
190         if (IS_ERR(priv->clk))
191                 return dev_err_probe(dev, PTR_ERR(priv->clk),
192                                      "get pwm clock failed\n");
193
194         ret = clk_prepare_enable(priv->clk);
195         if (ret < 0) {
196                 dev_err(dev, "failed to enable clock: %d\n", ret);
197                 return ret;
198         }
199
200         ret = devm_add_action_or_reset(dev, sunplus_pwm_clk_release, priv->clk);
201         if (ret < 0) {
202                 dev_err(dev, "failed to release clock: %d\n", ret);
203                 return ret;
204         }
205
206         priv->chip.dev = dev;
207         priv->chip.ops = &sunplus_pwm_ops;
208         priv->chip.npwm = SP7021_PWM_NUM;
209
210         ret = devm_pwmchip_add(dev, &priv->chip);
211         if (ret < 0)
212                 return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n");
213
214         return 0;
215 }
216
217 static const struct of_device_id sunplus_pwm_of_match[] = {
218         { .compatible = "sunplus,sp7021-pwm", },
219         {}
220 };
221 MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match);
222
223 static struct platform_driver sunplus_pwm_driver = {
224         .probe          = sunplus_pwm_probe,
225         .driver         = {
226                 .name   = "sunplus-pwm",
227                 .of_match_table = sunplus_pwm_of_match,
228         },
229 };
230 module_platform_driver(sunplus_pwm_driver);
231
232 MODULE_DESCRIPTION("Sunplus SoC PWM Driver");
233 MODULE_AUTHOR("Hammer Hsieh <hammerh0314@gmail.com>");
234 MODULE_LICENSE("GPL");