drivers/pwm/pwm-sunplus.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PWM device driver for SUNPLUS SP7021 SoC
   4  *
   5  * Links:
   6  *   Reference Manual:
   7  *   https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
   8  *
   9  *   Reference Manual(PWM module):
  10  *   https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
  11  *
  12  * Limitations:
  13  * - Only supports normal polarity.
  14  * - It output low when PWM channel disabled.
  15  * - When the parameters change, current running period will not be completed
  16  *     and run new settings immediately.
  17  * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
  18  *     done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY.
  19  *
  20  * Author: Hammer Hsieh <hammerh0314@gmail.com>
  21  */
  22 #include <linux/bitfield.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mod_devicetable.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pwm.h>
  30
  31 #define SP7021_PWM_MODE0                0x000
  32 #define SP7021_PWM_MODE0_PWMEN(ch)      BIT(ch)
  33 #define SP7021_PWM_MODE0_BYPASS(ch)     BIT(8 + (ch))
  34 #define SP7021_PWM_MODE1                0x004
  35 #define SP7021_PWM_MODE1_CNT_EN(ch)     BIT(ch)
  36 #define SP7021_PWM_FREQ(ch)             (0x008 + 4 * (ch))
  37 #define SP7021_PWM_FREQ_MAX             GENMASK(15, 0)
  38 #define SP7021_PWM_DUTY(ch)             (0x018 + 4 * (ch))
  39 #define SP7021_PWM_DUTY_DD_SEL(ch)      FIELD_PREP(GENMASK(9, 8), ch)
  40 #define SP7021_PWM_DUTY_MAX             GENMASK(7, 0)
  41 #define SP7021_PWM_DUTY_MASK            SP7021_PWM_DUTY_MAX
  42 #define SP7021_PWM_FREQ_SCALER          256
  43 #define SP7021_PWM_NUM                  4
  44
  45 struct sunplus_pwm {
  46         struct pwm_chip chip;
  47         void __iomem *base;
  48         struct clk *clk;
  49 };
  50
  51 static inline struct sunplus_pwm *to_sunplus_pwm(struct pwm_chip *chip)
  52 {
  53         return container_of(chip, struct sunplus_pwm, chip);
  54 }
  55
  56 static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  57                              const struct pwm_state *state)
  58 {
  59         struct sunplus_pwm *priv = to_sunplus_pwm(chip);
  60         u32 dd_freq, duty, mode0, mode1;
  61         u64 clk_rate;
  62
  63         if (state->polarity != pwm->state.polarity)
  64                 return -EINVAL;
  65
  66         if (!state->enabled) {
  67                 /* disable pwm channel output */
  68                 mode0 = readl(priv->base + SP7021_PWM_MODE0);
  69                 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
  70                 writel(mode0, priv->base + SP7021_PWM_MODE0);
  71                 /* disable pwm channel clk source */
  72                 mode1 = readl(priv->base + SP7021_PWM_MODE1);
  73                 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
  74                 writel(mode1, priv->base + SP7021_PWM_MODE1);
  75                 return 0;
  76         }
  77
  78         clk_rate = clk_get_rate(priv->clk);
  79
  80         /*
  81          * The following calculations might overflow if clk is bigger
  82          * than 256 GHz. In practise it's 202.5MHz, so this limitation
  83          * is only theoretic.
  84          */
  85         if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC)
  86                 return -EINVAL;
  87
  88         /*
  89          * With clk_rate limited above we have dd_freq <= state->period,
  90          * so this cannot overflow.
  91          */
  92         dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER
  93                                 * NSEC_PER_SEC);
  94
  95         if (dd_freq == 0)
  96                 return -EINVAL;
  97
  98         if (dd_freq > SP7021_PWM_FREQ_MAX)
  99                 dd_freq = SP7021_PWM_FREQ_MAX;
 100
 101         writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
 102
 103         /* cal and set pwm duty */
 104         mode0 = readl(priv->base + SP7021_PWM_MODE0);
 105         mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);
 106         mode1 = readl(priv->base + SP7021_PWM_MODE1);
 107         mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);
 108         if (state->duty_cycle == state->period) {
 109                 /* PWM channel output = high */
 110                 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
 111                 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX;
 112         } else {
 113                 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);
 114                 /*
 115                  * duty_ns <= period_ns 27 bits, clk_rate 28 bits, won't overflow.
 116                  */
 117                 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
 118                                            (u64)dd_freq * NSEC_PER_SEC);
 119                 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty;
 120         }
 121         writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
 122         writel(mode1, priv->base + SP7021_PWM_MODE1);
 123         writel(mode0, priv->base + SP7021_PWM_MODE0);
 124
 125         return 0;
 126 }
 127
 128 static int sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 129                                  struct pwm_state *state)
 130 {
 131         struct sunplus_pwm *priv = to_sunplus_pwm(chip);
 132         u32 mode0, dd_freq, duty;
 133         u64 clk_rate;
 134
 135         mode0 = readl(priv->base + SP7021_PWM_MODE0);
 136
 137         if (mode0 & BIT(pwm->hwpwm)) {
 138                 clk_rate = clk_get_rate(priv->clk);
 139                 dd_freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
 140                 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
 141                 duty = FIELD_GET(SP7021_PWM_DUTY_MASK, duty);
 142                 /*
 143                  * dd_freq 16 bits, SP7021_PWM_FREQ_SCALER 8 bits
 144                  * NSEC_PER_SEC 30 bits, won't overflow.
 145                  */
 146                 state->period = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)SP7021_PWM_FREQ_SCALER
 147                                                 * NSEC_PER_SEC, clk_rate);
 148                 /*
 149                  * dd_freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow.
 150                  */
 151                 state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,
 152                                                        clk_rate);
 153                 state->enabled = true;
 154         } else {
 155                 state->enabled = false;
 156         }
 157
 158         state->polarity = PWM_POLARITY_NORMAL;
 159
 160         return 0;
 161 }
 162
 163 static const struct pwm_ops sunplus_pwm_ops = {
 164         .apply = sunplus_pwm_apply,
 165         .get_state = sunplus_pwm_get_state,
 166         .owner = THIS_MODULE,
 167 };
 168
 169 static void sunplus_pwm_clk_release(void *data)
 170 {
 171         struct clk *clk = data;
 172
 173         clk_disable_unprepare(clk);
 174 }
 175
 176 static int sunplus_pwm_probe(struct platform_device *pdev)
 177 {
 178         struct device *dev = &pdev->dev;
 179         struct sunplus_pwm *priv;
 180         int ret;
 181
 182         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 183         if (!priv)
 184                 return -ENOMEM;
 185
 186         priv->base = devm_platform_ioremap_resource(pdev, 0);
 187         if (IS_ERR(priv->base))
 188                 return PTR_ERR(priv->base);
 189
 190         priv->clk = devm_clk_get(dev, NULL);
 191         if (IS_ERR(priv->clk))
 192                 return dev_err_probe(dev, PTR_ERR(priv->clk),
 193                                      "get pwm clock failed\n");
 194
 195         ret = clk_prepare_enable(priv->clk);
 196         if (ret < 0) {
 197                 dev_err(dev, "failed to enable clock: %d\n", ret);
 198                 return ret;
 199         }
 200
 201         ret = devm_add_action_or_reset(dev, sunplus_pwm_clk_release, priv->clk);
 202         if (ret < 0) {
 203                 dev_err(dev, "failed to release clock: %d\n", ret);
 204                 return ret;
 205         }
 206
 207         priv->chip.dev = dev;
 208         priv->chip.ops = &sunplus_pwm_ops;
 209         priv->chip.npwm = SP7021_PWM_NUM;
 210
 211         ret = devm_pwmchip_add(dev, &priv->chip);
 212         if (ret < 0)
 213                 return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n");
 214
 215         return 0;
 216 }
 217
 218 static const struct of_device_id sunplus_pwm_of_match[] = {
 219         { .compatible = "sunplus,sp7021-pwm", },
 220         {}
 221 };
 222 MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match);
 223
 224 static struct platform_driver sunplus_pwm_driver = {
 225         .probe          = sunplus_pwm_probe,
 226         .driver         = {
 227                 .name   = "sunplus-pwm",
 228                 .of_match_table = sunplus_pwm_of_match,
 229         },
 230 };
 231 module_platform_driver(sunplus_pwm_driver);
 232
 233 MODULE_DESCRIPTION("Sunplus SoC PWM Driver");
 234 MODULE_AUTHOR("Hammer Hsieh <hammerh0314@gmail.com>");
 235 MODULE_LICENSE("GPL");