1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2016
5 * Author: Gerald Baeza <gerald.baeza@st.com>
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
11 #include <linux/bitfield.h>
12 #include <linux/mfd/stm32-timers.h>
13 #include <linux/module.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
19 #define CCMR_CHANNEL_SHIFT 8
20 #define CCMR_CHANNEL_MASK 0xFF
21 #define MAX_BREAKINPUT 2
23 struct stm32_breakinput {
31 struct mutex lock; /* protect pwm config/enable */
33 struct regmap *regmap;
35 bool have_complementary_output;
36 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
37 unsigned int num_breakinputs;
38 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
41 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
43 return container_of(chip, struct stm32_pwm, chip);
46 static u32 active_channels(struct stm32_pwm *dev)
50 regmap_read(dev->regmap, TIM_CCER, &ccer);
52 return ccer & TIM_CCER_CCXE;
55 static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
59 return regmap_write(dev->regmap, TIM_CCR1, value);
61 return regmap_write(dev->regmap, TIM_CCR2, value);
63 return regmap_write(dev->regmap, TIM_CCR3, value);
65 return regmap_write(dev->regmap, TIM_CCR4, value);
70 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
71 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
72 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
73 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
76 * Capture using PWM input mode:
78 * TI[1, 2, 3 or 4]: ........._| |________|
85 * COUNTER: ______XXXXX . . . |_XXX
90 * CCR1/CCR3: tx..........t0...........t2
91 * CCR2/CCR4: tx..............t1.........
93 * DMA burst transfer: | |
95 * DMA buffer: { t0, tx } { t2, t1 }
98 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
99 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
100 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
101 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
102 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
106 * - Duty cycle = t1 - t0
108 static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm,
109 unsigned long tmo_ms, u32 *raw_prd,
112 struct device *parent = priv->chip.dev->parent;
113 enum stm32_timers_dmas dma_id;
117 /* Ensure registers have been updated, enable counter and capture */
118 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
119 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
121 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
125 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
128 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
129 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
130 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
131 * or { CCR3, CCR4 }, { CCR3, CCR4 }
133 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
138 /* Period: t2 - t0 (take care of counter overflow) */
139 if (priv->capture[0] <= priv->capture[2])
140 *raw_prd = priv->capture[2] - priv->capture[0];
142 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
144 /* Duty cycle capture requires at least two capture units */
145 if (pwm->chip->npwm < 2)
147 else if (priv->capture[0] <= priv->capture[3])
148 *raw_dty = priv->capture[3] - priv->capture[0];
150 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
152 if (*raw_dty > *raw_prd) {
154 * Race beetween PWM input and DMA: it may happen
155 * falling edge triggers new capture on TI2/4 before DMA
156 * had a chance to read CCR2/4. It means capture[1]
157 * contains period + duty_cycle. So, subtract period.
159 *raw_dty -= *raw_prd;
163 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
164 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
169 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
170 struct pwm_capture *result, unsigned long tmo_ms)
172 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
173 unsigned long long prd, div, dty;
175 unsigned int psc = 0, icpsc, scale;
176 u32 raw_prd = 0, raw_dty = 0;
179 mutex_lock(&priv->lock);
181 if (active_channels(priv)) {
186 ret = clk_enable(priv->clk);
188 dev_err(priv->chip.dev, "failed to enable counter clock\n");
192 rate = clk_get_rate(priv->clk);
198 /* prescaler: fit timeout window provided by upper layer */
199 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
200 do_div(div, MSEC_PER_SEC);
202 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
205 do_div(div, psc + 1);
207 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
208 regmap_write(priv->regmap, TIM_PSC, psc);
210 /* Reset input selector to its default input and disable slave mode */
211 regmap_write(priv->regmap, TIM_TISEL, 0x0);
212 regmap_write(priv->regmap, TIM_SMCR, 0x0);
214 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
215 regmap_update_bits(priv->regmap,
216 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
217 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
218 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
219 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
221 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
222 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
223 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
224 TIM_CCER_CC2P : TIM_CCER_CC4P);
226 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
231 * Got a capture. Try to improve accuracy at high rates:
232 * - decrease counter clock prescaler, scale up to max rate.
233 * - use input prescaler, capture once every /2 /4 or /8 edges.
236 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
238 scale = max_arr / min(max_arr, raw_prd);
240 scale = priv->max_arr; /* bellow resolution, use max scale */
243 if (psc && scale > 1) {
244 /* 2nd measure with new scale */
246 regmap_write(priv->regmap, TIM_PSC, psc);
247 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd,
253 /* Compute intermediate period not to exceed timeout at low rates */
254 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
257 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
258 /* input prescaler: also keep arbitrary margin */
259 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
261 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
268 /* Last chance to improve period accuracy, using input prescaler */
269 regmap_update_bits(priv->regmap,
270 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
271 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
272 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
273 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
275 ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty);
279 if (raw_dty >= (raw_prd >> icpsc)) {
281 * We may fall here using input prescaler, when input
282 * capture starts on high side (before falling edge).
283 * Example with icpsc to capture on each 4 events:
285 * start 1st capture 2nd capture
287 * ___ _____ _____ _____ _____ ____
288 * TI1..4 |__| |__| |__| |__| |__|
290 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
291 * icpsc2/4: 0 1 2 3 0
293 * CCR1/3 ......t0..............................t2
294 * CCR2/4 ..t1..............................t1'...
296 * Capture0: .<----------------------------->.
297 * Capture1: .<-------------------------->. .
299 * Period: .<------> . .
303 * - Period = Capture0 / icpsc
304 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
306 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
310 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
311 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
312 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
313 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
315 regmap_write(priv->regmap, TIM_CCER, 0);
316 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
317 regmap_write(priv->regmap, TIM_PSC, 0);
319 clk_disable(priv->clk);
321 mutex_unlock(&priv->lock);
326 static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
327 int duty_ns, int period_ns)
329 unsigned long long prd, div, dty;
330 unsigned int prescaler = 0;
331 u32 ccmr, mask, shift;
333 /* Period and prescaler values depends on clock rate */
334 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
336 do_div(div, NSEC_PER_SEC);
339 while (div > priv->max_arr) {
342 do_div(div, prescaler + 1);
347 if (prescaler > MAX_TIM_PSC)
351 * All channels share the same prescaler and counter so when two
352 * channels are active at the same time we can't change them
354 if (active_channels(priv) & ~(1 << ch * 4)) {
357 regmap_read(priv->regmap, TIM_PSC, &psc);
358 regmap_read(priv->regmap, TIM_ARR, &arr);
360 if ((psc != prescaler) || (arr != prd - 1))
364 regmap_write(priv->regmap, TIM_PSC, prescaler);
365 regmap_write(priv->regmap, TIM_ARR, prd - 1);
366 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
368 /* Calculate the duty cycles */
370 do_div(dty, period_ns);
372 write_ccrx(priv, ch, dty);
374 /* Configure output mode */
375 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
376 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
377 mask = CCMR_CHANNEL_MASK << shift;
380 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
382 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
384 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
389 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
390 enum pwm_polarity polarity)
394 mask = TIM_CCER_CC1P << (ch * 4);
395 if (priv->have_complementary_output)
396 mask |= TIM_CCER_CC1NP << (ch * 4);
398 regmap_update_bits(priv->regmap, TIM_CCER, mask,
399 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
404 static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
409 ret = clk_enable(priv->clk);
414 mask = TIM_CCER_CC1E << (ch * 4);
415 if (priv->have_complementary_output)
416 mask |= TIM_CCER_CC1NE << (ch * 4);
418 regmap_set_bits(priv->regmap, TIM_CCER, mask);
420 /* Make sure that registers are updated */
421 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
423 /* Enable controller */
424 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
429 static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
433 /* Disable channel */
434 mask = TIM_CCER_CC1E << (ch * 4);
435 if (priv->have_complementary_output)
436 mask |= TIM_CCER_CC1NE << (ch * 4);
438 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
440 /* When all channels are disabled, we can disable the controller */
441 if (!active_channels(priv))
442 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
444 clk_disable(priv->clk);
447 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
448 const struct pwm_state *state)
451 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
454 enabled = pwm->state.enabled;
456 if (enabled && !state->enabled) {
457 stm32_pwm_disable(priv, pwm->hwpwm);
461 if (state->polarity != pwm->state.polarity)
462 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
464 ret = stm32_pwm_config(priv, pwm->hwpwm,
465 state->duty_cycle, state->period);
469 if (!enabled && state->enabled)
470 ret = stm32_pwm_enable(priv, pwm->hwpwm);
475 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
476 const struct pwm_state *state)
478 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
481 /* protect common prescaler for all active channels */
482 mutex_lock(&priv->lock);
483 ret = stm32_pwm_apply(chip, pwm, state);
484 mutex_unlock(&priv->lock);
489 static const struct pwm_ops stm32pwm_ops = {
490 .owner = THIS_MODULE,
491 .apply = stm32_pwm_apply_locked,
492 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
495 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
496 const struct stm32_breakinput *bi)
498 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
499 u32 bke = TIM_BDTR_BKE(bi->index);
500 u32 bkp = TIM_BDTR_BKP(bi->index);
501 u32 bkf = TIM_BDTR_BKF(bi->index);
502 u32 mask = bkf | bkp | bke;
505 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
510 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
512 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
514 return (bdtr & bke) ? 0 : -EINVAL;
517 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
522 for (i = 0; i < priv->num_breakinputs; i++) {
523 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
531 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
532 struct device_node *np)
534 int nb, ret, array_size;
537 nb = of_property_count_elems_of_size(np, "st,breakinput",
538 sizeof(struct stm32_breakinput));
541 * Because "st,breakinput" parameter is optional do not make probe
542 * failed if it doesn't exist.
547 if (nb > MAX_BREAKINPUT)
550 priv->num_breakinputs = nb;
551 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
552 ret = of_property_read_u32_array(np, "st,breakinput",
553 (u32 *)priv->breakinputs, array_size);
557 for (i = 0; i < priv->num_breakinputs; i++) {
558 if (priv->breakinputs[i].index > 1 ||
559 priv->breakinputs[i].level > 1 ||
560 priv->breakinputs[i].filter > 15)
564 return stm32_pwm_apply_breakinputs(priv);
567 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
572 * If complementary bit doesn't exist writing 1 will have no
573 * effect so we can detect it.
575 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
576 regmap_read(priv->regmap, TIM_CCER, &ccer);
577 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
579 priv->have_complementary_output = (ccer != 0);
582 static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
588 * If channels enable bits don't exist writing 1 will have no
589 * effect so we can detect and count them.
591 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
592 regmap_read(priv->regmap, TIM_CCER, &ccer);
593 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);
595 if (ccer & TIM_CCER_CC1E)
598 if (ccer & TIM_CCER_CC2E)
601 if (ccer & TIM_CCER_CC3E)
604 if (ccer & TIM_CCER_CC4E)
610 static int stm32_pwm_probe(struct platform_device *pdev)
612 struct device *dev = &pdev->dev;
613 struct device_node *np = dev->of_node;
614 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
615 struct stm32_pwm *priv;
618 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
622 mutex_init(&priv->lock);
623 priv->regmap = ddata->regmap;
624 priv->clk = ddata->clk;
625 priv->max_arr = ddata->max_arr;
627 if (!priv->regmap || !priv->clk)
630 ret = stm32_pwm_probe_breakinputs(priv, np);
634 stm32_pwm_detect_complementary(priv);
636 priv->chip.dev = dev;
637 priv->chip.ops = &stm32pwm_ops;
638 priv->chip.npwm = stm32_pwm_detect_channels(priv);
640 ret = pwmchip_add(&priv->chip);
644 platform_set_drvdata(pdev, priv);
649 static void stm32_pwm_remove(struct platform_device *pdev)
651 struct stm32_pwm *priv = platform_get_drvdata(pdev);
653 pwmchip_remove(&priv->chip);
656 static int __maybe_unused stm32_pwm_suspend(struct device *dev)
658 struct stm32_pwm *priv = dev_get_drvdata(dev);
662 /* Look for active channels */
663 ccer = active_channels(priv);
665 for (i = 0; i < priv->chip.npwm; i++) {
666 mask = TIM_CCER_CC1E << (i * 4);
668 dev_err(dev, "PWM %u still in use by consumer %s\n",
669 i, priv->chip.pwms[i].label);
674 return pinctrl_pm_select_sleep_state(dev);
677 static int __maybe_unused stm32_pwm_resume(struct device *dev)
679 struct stm32_pwm *priv = dev_get_drvdata(dev);
682 ret = pinctrl_pm_select_default_state(dev);
686 /* restore breakinput registers that may have been lost in low power */
687 return stm32_pwm_apply_breakinputs(priv);
690 static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
692 static const struct of_device_id stm32_pwm_of_match[] = {
693 { .compatible = "st,stm32-pwm", },
696 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
698 static struct platform_driver stm32_pwm_driver = {
699 .probe = stm32_pwm_probe,
700 .remove_new = stm32_pwm_remove,
703 .of_match_table = stm32_pwm_of_match,
704 .pm = &stm32_pwm_pm_ops,
707 module_platform_driver(stm32_pwm_driver);
709 MODULE_ALIAS("platform:stm32-pwm");
710 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
711 MODULE_LICENSE("GPL v2");