drivers/pwm/pwm-rz-mtu3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RZ/G2L MTU3a PWM Timer driver
   4  *
   5  * Copyright (C) 2023 Renesas Electronics Corporation
   6  *
   7  * Hardware manual for this IP can be found here
   8  * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en
   9  *
  10  * Limitations:
  11  * - When PWM is disabled, the output is driven to Hi-Z.
  12  * - While the hardware supports both polarities, the driver (for now)
  13  *   only handles normal polarity.
  14  * - HW uses one counter and two match components to configure duty_cycle
  15  *   and period.
  16  * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
  17  *   operations. (The channels are MTU{0..4, 6, 7}.)
  18  * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
  19  *   2 IOs.
  20  * - Each IO is modelled as an independent PWM channel.
  21  * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
  22  *   corresponding HW channel as there are difference in number of IOs
  23  *   between HW channels.
  24  */
  25
  26 #include <linux/bitfield.h>
  27 #include <linux/clk.h>
  28 #include <linux/limits.h>
  29 #include <linux/mfd/rz-mtu3.h>
  30 #include <linux/module.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/pwm.h>
  34 #include <linux/time.h>
  35
  36 #define RZ_MTU3_MAX_PWM_CHANNELS        12
  37 #define RZ_MTU3_MAX_HW_CHANNELS         7
  38
  39 /**
  40  * struct rz_mtu3_channel_io_map - MTU3 pwm channel map
  41  *
  42  * @base_pwm_number: First PWM of a channel
  43  * @num_channel_ios: number of IOs on the HW channel.
  44  */
  45 struct rz_mtu3_channel_io_map {
  46         u8 base_pwm_number;
  47         u8 num_channel_ios;
  48 };
  49
  50 /**
  51  * struct rz_mtu3_pwm_channel - MTU3 pwm channel data
  52  *
  53  * @mtu: MTU3 channel data
  54  * @map: MTU3 pwm channel map
  55  */
  56 struct rz_mtu3_pwm_channel {
  57         struct rz_mtu3_channel *mtu;
  58         const struct rz_mtu3_channel_io_map *map;
  59 };
  60
  61 /**
  62  * struct rz_mtu3_pwm_chip - MTU3 pwm private data
  63  *
  64  * @chip: MTU3 pwm chip data
  65  * @clk: MTU3 module clock
  66  * @lock: Lock to prevent concurrent access for usage count
  67  * @rate: MTU3 clock rate
  68  * @user_count: MTU3 usage count
  69  * @enable_count: MTU3 enable count
  70  * @prescale: MTU3 prescale
  71  * @channel_data: MTU3 pwm channel data
  72  */
  73
  74 struct rz_mtu3_pwm_chip {
  75         struct pwm_chip chip;
  76         struct clk *clk;
  77         struct mutex lock;
  78         unsigned long rate;
  79         u32 user_count[RZ_MTU3_MAX_HW_CHANNELS];
  80         u32 enable_count[RZ_MTU3_MAX_HW_CHANNELS];
  81         u8 prescale[RZ_MTU3_MAX_HW_CHANNELS];
  82         struct rz_mtu3_pwm_channel channel_data[RZ_MTU3_MAX_HW_CHANNELS];
  83 };
  84
  85 /*
  86  * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1
  87  * and MTU2 channel is 1 compared to 2 on others.
  88  */
  89 static const struct rz_mtu3_channel_io_map channel_map[] = {
  90         { 0, 2 }, { 2, 1 }, { 3, 1 }, { 4, 2 }, { 6, 2 }, { 8, 2 }, { 10, 2 }
  91 };
  92
  93 static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip)
  94 {
  95         return container_of(chip, struct rz_mtu3_pwm_chip, chip);
  96 }
  97
  98 static void rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel *priv,
  99                                            u16 reg_pv_offset, u16 *pv_val,
 100                                            u16 reg_dc_offset, u16 *dc_val)
 101 {
 102         *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset);
 103         *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset);
 104 }
 105
 106 static void rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel *priv,
 107                                             u16 reg_pv_offset, u16 pv_val,
 108                                             u16 reg_dc_offset, u16 dc_val)
 109 {
 110         rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val);
 111         rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val);
 112 }
 113
 114 static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3,
 115                                          u64 period_cycles)
 116 {
 117         u32 prescaled_period_cycles;
 118         u8 prescale;
 119
 120         /*
 121          * Supported prescale values are 1, 4, 16 and 64.
 122          * TODO: Support prescale values 2, 8, 32, 256 and 1024.
 123          */
 124         prescaled_period_cycles = period_cycles >> 16;
 125         if (prescaled_period_cycles >= 16)
 126                 prescale = 3;
 127         else
 128                 prescale = (fls(prescaled_period_cycles) + 1) / 2;
 129
 130         return prescale;
 131 }
 132
 133 static struct rz_mtu3_pwm_channel *
 134 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm)
 135 {
 136         struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data;
 137         unsigned int ch;
 138
 139         for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) {
 140                 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm)
 141                         break;
 142         }
 143
 144         return priv;
 145 }
 146
 147 static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
 148                                       u32 hwpwm)
 149 {
 150         struct rz_mtu3_pwm_channel *priv;
 151         bool is_channel_en;
 152         u8 val;
 153
 154         priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm);
 155         is_channel_en = rz_mtu3_is_enabled(priv->mtu);
 156         if (!is_channel_en)
 157                 return false;
 158
 159         if (priv->map->base_pwm_number == hwpwm)
 160                 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH);
 161         else
 162                 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL);
 163
 164         return val & RZ_MTU3_TIOR_IOA;
 165 }
 166
 167 static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 168 {
 169         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
 170         struct rz_mtu3_pwm_channel *priv;
 171         bool is_mtu3_channel_available;
 172         u32 ch;
 173
 174         priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 175         ch = priv - rz_mtu3_pwm->channel_data;
 176
 177         mutex_lock(&rz_mtu3_pwm->lock);
 178         /*
 179          * Each channel must be requested only once, so if the channel
 180          * serves two PWMs and the other is already requested, skip over
 181          * rz_mtu3_request_channel()
 182          */
 183         if (!rz_mtu3_pwm->user_count[ch]) {
 184                 is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu);
 185                 if (!is_mtu3_channel_available) {
 186                         mutex_unlock(&rz_mtu3_pwm->lock);
 187                         return -EBUSY;
 188                 }
 189         }
 190
 191         rz_mtu3_pwm->user_count[ch]++;
 192         mutex_unlock(&rz_mtu3_pwm->lock);
 193
 194         return 0;
 195 }
 196
 197 static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 198 {
 199         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
 200         struct rz_mtu3_pwm_channel *priv;
 201         u32 ch;
 202
 203         priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 204         ch = priv - rz_mtu3_pwm->channel_data;
 205
 206         mutex_lock(&rz_mtu3_pwm->lock);
 207         rz_mtu3_pwm->user_count[ch]--;
 208         if (!rz_mtu3_pwm->user_count[ch])
 209                 rz_mtu3_release_channel(priv->mtu);
 210
 211         mutex_unlock(&rz_mtu3_pwm->lock);
 212 }
 213
 214 static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
 215                               struct pwm_device *pwm)
 216 {
 217         struct rz_mtu3_pwm_channel *priv;
 218         u32 ch;
 219         u8 val;
 220         int rc;
 221
 222         rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev);
 223         if (rc)
 224                 return rc;
 225
 226         priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 227         ch = priv - rz_mtu3_pwm->channel_data;
 228         val = RZ_MTU3_TIOR_OC_IOB_TOGGLE | RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH;
 229
 230         rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1);
 231         if (priv->map->base_pwm_number == pwm->hwpwm)
 232                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val);
 233         else
 234                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val);
 235
 236         mutex_lock(&rz_mtu3_pwm->lock);
 237         if (!rz_mtu3_pwm->enable_count[ch])
 238                 rz_mtu3_enable(priv->mtu);
 239
 240         rz_mtu3_pwm->enable_count[ch]++;
 241         mutex_unlock(&rz_mtu3_pwm->lock);
 242
 243         return 0;
 244 }
 245
 246 static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm,
 247                                 struct pwm_device *pwm)
 248 {
 249         struct rz_mtu3_pwm_channel *priv;
 250         u32 ch;
 251
 252         priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 253         ch = priv - rz_mtu3_pwm->channel_data;
 254
 255         /* Disable output pins of MTU3 channel */
 256         if (priv->map->base_pwm_number == pwm->hwpwm)
 257                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN);
 258         else
 259                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN);
 260
 261         mutex_lock(&rz_mtu3_pwm->lock);
 262         rz_mtu3_pwm->enable_count[ch]--;
 263         if (!rz_mtu3_pwm->enable_count[ch])
 264                 rz_mtu3_disable(priv->mtu);
 265
 266         mutex_unlock(&rz_mtu3_pwm->lock);
 267
 268         pm_runtime_put_sync(rz_mtu3_pwm->chip.dev);
 269 }
 270
 271 static int rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 272                                  struct pwm_state *state)
 273 {
 274         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
 275         int rc;
 276
 277         rc = pm_runtime_resume_and_get(chip->dev);
 278         if (rc)
 279                 return rc;
 280
 281         state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm);
 282         if (state->enabled) {
 283                 struct rz_mtu3_pwm_channel *priv;
 284                 u8 prescale, val;
 285                 u16 dc, pv;
 286                 u64 tmp;
 287
 288                 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 289                 if (priv->map->base_pwm_number == pwm->hwpwm)
 290                         rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv,
 291                                                        RZ_MTU3_TGRB, &dc);
 292                 else
 293                         rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv,
 294                                                        RZ_MTU3_TGRD, &dc);
 295
 296                 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR);
 297                 prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val);
 298
 299                 /* With prescale <= 7 and pv <= 0xffff this doesn't overflow. */
 300                 tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale);
 301                 state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
 302                 tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale);
 303                 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
 304
 305                 if (state->duty_cycle > state->period)
 306                         state->duty_cycle = state->period;
 307         }
 308
 309         state->polarity = PWM_POLARITY_NORMAL;
 310         pm_runtime_put(chip->dev);
 311
 312         return 0;
 313 }
 314
 315 static u16 rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
 316 {
 317         return min(period_or_duty_cycle >> (2 * prescale), (u64)U16_MAX);
 318 }
 319
 320 static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 321                               const struct pwm_state *state)
 322 {
 323         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
 324         struct rz_mtu3_pwm_channel *priv;
 325         u64 period_cycles;
 326         u64 duty_cycles;
 327         u8 prescale;
 328         u16 pv, dc;
 329         u8 val;
 330         u32 ch;
 331
 332         priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm);
 333         ch = priv - rz_mtu3_pwm->channel_data;
 334
 335         period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate,
 336                                         NSEC_PER_SEC);
 337         prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles);
 338
 339         /*
 340          * Prescalar is shared by multiple channels, so prescale can
 341          * NOT be modified when there are multiple channels in use with
 342          * different settings. Modify prescalar if other PWM is off or handle
 343          * it, if current prescale value is less than the one we want to set.
 344          */
 345         if (rz_mtu3_pwm->enable_count[ch] > 1) {
 346                 if (rz_mtu3_pwm->prescale[ch] > prescale)
 347                         return -EBUSY;
 348
 349                 prescale = rz_mtu3_pwm->prescale[ch];
 350         }
 351
 352         pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale);
 353
 354         duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate,
 355                                       NSEC_PER_SEC);
 356         dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale);
 357
 358         /*
 359          * If the PWM channel is disabled, make sure to turn on the clock
 360          * before writing the register.
 361          */
 362         if (!pwm->state.enabled) {
 363                 int rc;
 364
 365                 rc = pm_runtime_resume_and_get(chip->dev);
 366                 if (rc)
 367                         return rc;
 368         }
 369
 370         val = RZ_MTU3_TCR_CKEG_RISING | prescale;
 371
 372         /* Counter must be stopped while updating TCR register */
 373         if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch])
 374                 rz_mtu3_disable(priv->mtu);
 375
 376         if (priv->map->base_pwm_number == pwm->hwpwm) {
 377                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
 378                                       RZ_MTU3_TCR_CCLR_TGRA | val);
 379                 rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv,
 380                                                 RZ_MTU3_TGRB, dc);
 381         } else {
 382                 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,
 383                                       RZ_MTU3_TCR_CCLR_TGRC | val);
 384                 rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv,
 385                                                 RZ_MTU3_TGRD, dc);
 386         }
 387
 388         if (rz_mtu3_pwm->prescale[ch] != prescale) {
 389                 /*
 390                  * Prescalar is shared by multiple channels, we cache the
 391                  * prescalar value from first enabled channel and use the same
 392                  * value for both channels.
 393                  */
 394                 rz_mtu3_pwm->prescale[ch] = prescale;
 395
 396                 if (rz_mtu3_pwm->enable_count[ch])
 397                         rz_mtu3_enable(priv->mtu);
 398         }
 399
 400         /* If the PWM is not enabled, turn the clock off again to save power. */
 401         if (!pwm->state.enabled)
 402                 pm_runtime_put(chip->dev);
 403
 404         return 0;
 405 }
 406
 407 static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 408                              const struct pwm_state *state)
 409 {
 410         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip);
 411         bool enabled = pwm->state.enabled;
 412         int ret;
 413
 414         if (state->polarity != PWM_POLARITY_NORMAL)
 415                 return -EINVAL;
 416
 417         if (!state->enabled) {
 418                 if (enabled)
 419                         rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm);
 420
 421                 return 0;
 422         }
 423
 424         mutex_lock(&rz_mtu3_pwm->lock);
 425         ret = rz_mtu3_pwm_config(chip, pwm, state);
 426         mutex_unlock(&rz_mtu3_pwm->lock);
 427         if (ret)
 428                 return ret;
 429
 430         if (!enabled)
 431                 ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm);
 432
 433         return ret;
 434 }
 435
 436 static const struct pwm_ops rz_mtu3_pwm_ops = {
 437         .request = rz_mtu3_pwm_request,
 438         .free = rz_mtu3_pwm_free,
 439         .get_state = rz_mtu3_pwm_get_state,
 440         .apply = rz_mtu3_pwm_apply,
 441         .owner = THIS_MODULE,
 442 };
 443
 444 static int rz_mtu3_pwm_pm_runtime_suspend(struct device *dev)
 445 {
 446         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
 447
 448         clk_disable_unprepare(rz_mtu3_pwm->clk);
 449
 450         return 0;
 451 }
 452
 453 static int rz_mtu3_pwm_pm_runtime_resume(struct device *dev)
 454 {
 455         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev);
 456
 457         return clk_prepare_enable(rz_mtu3_pwm->clk);
 458 }
 459
 460 static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_pwm_pm_ops,
 461                                  rz_mtu3_pwm_pm_runtime_suspend,
 462                                  rz_mtu3_pwm_pm_runtime_resume, NULL);
 463
 464 static void rz_mtu3_pwm_pm_disable(void *data)
 465 {
 466         struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data;
 467
 468         clk_rate_exclusive_put(rz_mtu3_pwm->clk);
 469         pm_runtime_disable(rz_mtu3_pwm->chip.dev);
 470         pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev);
 471 }
 472
 473 static int rz_mtu3_pwm_probe(struct platform_device *pdev)
 474 {
 475         struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent);
 476         struct rz_mtu3_pwm_chip *rz_mtu3_pwm;
 477         struct device *dev = &pdev->dev;
 478         unsigned int i, j = 0;
 479         int ret;
 480
 481         rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL);
 482         if (!rz_mtu3_pwm)
 483                 return -ENOMEM;
 484
 485         rz_mtu3_pwm->clk = parent_ddata->clk;
 486
 487         for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
 488                 if (i == RZ_MTU3_CHAN_5 || i == RZ_MTU3_CHAN_8)
 489                         continue;
 490
 491                 rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i];
 492                 rz_mtu3_pwm->channel_data[j].mtu->dev = dev;
 493                 rz_mtu3_pwm->channel_data[j].map = &channel_map[j];
 494                 j++;
 495         }
 496
 497         mutex_init(&rz_mtu3_pwm->lock);
 498         platform_set_drvdata(pdev, rz_mtu3_pwm);
 499         ret = clk_prepare_enable(rz_mtu3_pwm->clk);
 500         if (ret)
 501                 return dev_err_probe(dev, ret, "Clock enable failed\n");
 502
 503         clk_rate_exclusive_get(rz_mtu3_pwm->clk);
 504
 505         rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk);
 506         /*
 507          * Refuse clk rates > 1 GHz to prevent overflow later for computing
 508          * period and duty cycle.
 509          */
 510         if (rz_mtu3_pwm->rate > NSEC_PER_SEC) {
 511                 ret = -EINVAL;
 512                 clk_rate_exclusive_put(rz_mtu3_pwm->clk);
 513                 goto disable_clock;
 514         }
 515
 516         pm_runtime_set_active(&pdev->dev);
 517         pm_runtime_enable(&pdev->dev);
 518         rz_mtu3_pwm->chip.dev = &pdev->dev;
 519         ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable,
 520                                        rz_mtu3_pwm);
 521         if (ret < 0)
 522                 return ret;
 523
 524         rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops;
 525         rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS;
 526         ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip);
 527         if (ret)
 528                 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
 529
 530         pm_runtime_idle(&pdev->dev);
 531
 532         return 0;
 533
 534 disable_clock:
 535         clk_disable_unprepare(rz_mtu3_pwm->clk);
 536         return ret;
 537 }
 538
 539 static struct platform_driver rz_mtu3_pwm_driver = {
 540         .driver = {
 541                 .name = "pwm-rz-mtu3",
 542                 .pm = pm_ptr(&rz_mtu3_pwm_pm_ops),
 543         },
 544         .probe = rz_mtu3_pwm_probe,
 545 };
 546 module_platform_driver(rz_mtu3_pwm_driver);
 547
 548 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
 549 MODULE_ALIAS("platform:pwm-rz-mtu3");
 550 MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a PWM Timer Driver");
 551 MODULE_LICENSE("GPL");