1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
5 * Author: Sam Shih <sam.shih@mediatek.com>
13 #include <linux/bitops.h>
16 /* PWM registers and bits definitions */
21 #define PWMWAVENUM 0x28
22 #define PWMDWIDTH 0x2c
23 #define PWM45DWIDTH_FIXUP 0x30
25 #define PWM45THRES_FIXUP 0x34
27 #define PWM_CLK_DIV_MAX 7
30 #define NSEC_PER_SEC 1000000000L
32 enum mtk_pwm_reg_ver {
37 static const unsigned int mtk_pwm_reg_offset_v1[] = {
38 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
41 static const unsigned int mtk_pwm_reg_offset_v2[] = {
42 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
46 unsigned int num_pwms;
48 enum mtk_pwm_reg_ver reg_ver;
55 struct clk pwm_clks[MAX_PWM_NUM];
56 const struct mtk_pwm_soc *soc;
59 static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
61 struct mtk_pwm_priv *priv = dev_get_priv(dev);
64 switch (priv->soc->reg_ver) {
66 offset = mtk_pwm_reg_offset_v2[channel];
70 offset = mtk_pwm_reg_offset_v1[channel];
73 writel(val, priv->base + offset + reg);
76 static int mtk_pwm_set_config(struct udevice *dev, uint channel,
77 uint period_ns, uint duty_ns)
79 struct mtk_pwm_priv *priv = dev_get_priv(dev);
80 u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty,
81 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
85 clk_enable(&priv->top_clk);
86 clk_enable(&priv->main_clk);
87 /* Using resolution in picosecond gets accuracy higher */
88 resolution = (u64)NSEC_PER_SEC * 1000;
89 do_div(resolution, clk_get_rate(&priv->pwm_clks[channel]));
90 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
91 while (cnt_period > 8191) {
94 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
96 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) {
99 resolution = (u64)NSEC_PER_SEC * 1000 * 1625;
101 clk_get_rate(&priv->pwm_clks[channel]));
102 cnt_period = DIV_ROUND_CLOSEST_ULL(
103 (u64)period_ns * 1000, resolution);
104 clk_enable(&priv->pwm_clks[channel]);
107 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) {
108 printf("pwm period %u not supported\n", period_ns);
111 if (priv->soc->pwm45_fixup && channel > 2) {
113 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
114 * from the other PWMs on MT7623.
116 reg_width = PWM45DWIDTH_FIXUP;
117 reg_thres = PWM45THRES_FIXUP;
119 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
121 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv);
123 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv);
124 mtk_pwm_w32(dev, channel, reg_width, cnt_period);
125 mtk_pwm_w32(dev, channel, reg_thres, cnt_duty);
130 static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
132 struct mtk_pwm_priv *priv = dev_get_priv(dev);
135 val = readl(priv->base);
139 val &= ~BIT(channel);
140 writel(val, priv->base);
145 static int mtk_pwm_probe(struct udevice *dev)
147 struct mtk_pwm_priv *priv = dev_get_priv(dev);
151 priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev);
152 priv->base = dev_read_addr_ptr(dev);
155 ret = clk_get_by_name(dev, "top", &priv->top_clk);
158 ret = clk_get_by_name(dev, "main", &priv->main_clk);
161 for (i = 0; i < priv->soc->num_pwms; i++) {
164 snprintf(name, sizeof(name), "pwm%d", i + 1);
165 ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]);
173 static const struct pwm_ops mtk_pwm_ops = {
174 .set_config = mtk_pwm_set_config,
175 .set_enable = mtk_pwm_set_enable,
178 static const struct mtk_pwm_soc mt7622_data = {
180 .pwm45_fixup = false,
181 .reg_ver = PWM_REG_V1,
184 static const struct mtk_pwm_soc mt7623_data = {
187 .reg_ver = PWM_REG_V1,
190 static const struct mtk_pwm_soc mt7629_data = {
192 .pwm45_fixup = false,
193 .reg_ver = PWM_REG_V1,
196 static const struct mtk_pwm_soc mt7981_data = {
198 .pwm45_fixup = false,
199 .reg_ver = PWM_REG_V2,
202 static const struct mtk_pwm_soc mt7986_data = {
204 .pwm45_fixup = false,
205 .reg_ver = PWM_REG_V1,
208 static const struct udevice_id mtk_pwm_ids[] = {
209 { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
210 { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
211 { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
212 { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
213 { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
217 U_BOOT_DRIVER(mtk_pwm) = {
220 .of_match = mtk_pwm_ids,
222 .probe = mtk_pwm_probe,
223 .priv_auto = sizeof(struct mtk_pwm_priv),