drivers/pwm/pwm-mtk-disp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * MediaTek display pulse-width-modulation controller driver.
   4  * Copyright (c) 2015 MediaTek Inc.
   5  * Author: YH Huang <yh.huang@mediatek.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/err.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pwm.h>
  17 #include <linux/slab.h>
  18
  19 #define DISP_PWM_EN             0x00
  20
  21 #define PWM_CLKDIV_SHIFT        16
  22 #define PWM_CLKDIV_MAX          0x3ff
  23 #define PWM_CLKDIV_MASK         (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
  24
  25 #define PWM_PERIOD_BIT_WIDTH    12
  26 #define PWM_PERIOD_MASK         ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
  27
  28 #define PWM_HIGH_WIDTH_SHIFT    16
  29 #define PWM_HIGH_WIDTH_MASK     (0x1fff << PWM_HIGH_WIDTH_SHIFT)
  30
  31 struct mtk_pwm_data {
  32         u32 enable_mask;
  33         unsigned int con0;
  34         u32 con0_sel;
  35         unsigned int con1;
  36
  37         bool has_commit;
  38         unsigned int commit;
  39         unsigned int commit_mask;
  40
  41         unsigned int bls_debug;
  42         u32 bls_debug_mask;
  43 };
  44
  45 struct mtk_disp_pwm {
  46         struct pwm_chip chip;
  47         const struct mtk_pwm_data *data;
  48         struct clk *clk_main;
  49         struct clk *clk_mm;
  50         void __iomem *base;
  51         bool enabled;
  52 };
  53
  54 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
  55 {
  56         return container_of(chip, struct mtk_disp_pwm, chip);
  57 }
  58
  59 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
  60                                      u32 mask, u32 data)
  61 {
  62         void __iomem *address = mdp->base + offset;
  63         u32 value;
  64
  65         value = readl(address);
  66         value &= ~mask;
  67         value |= data;
  68         writel(value, address);
  69 }
  70
  71 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  72                               const struct pwm_state *state)
  73 {
  74         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  75         u32 clk_div, period, high_width, value;
  76         u64 div, rate;
  77         int err;
  78
  79         if (state->polarity != PWM_POLARITY_NORMAL)
  80                 return -EINVAL;
  81
  82         if (!state->enabled) {
  83                 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
  84                                          0x0);
  85
  86                 if (mdp->enabled) {
  87                         clk_disable_unprepare(mdp->clk_mm);
  88                         clk_disable_unprepare(mdp->clk_main);
  89                 }
  90
  91                 mdp->enabled = false;
  92                 return 0;
  93         }
  94
  95         if (!mdp->enabled) {
  96                 err = clk_prepare_enable(mdp->clk_main);
  97                 if (err < 0) {
  98                         dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
  99                                 ERR_PTR(err));
 100                         return err;
 101                 }
 102
 103                 err = clk_prepare_enable(mdp->clk_mm);
 104                 if (err < 0) {
 105                         dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
 106                                 ERR_PTR(err));
 107                         clk_disable_unprepare(mdp->clk_main);
 108                         return err;
 109                 }
 110         }
 111
 112         /*
 113          * Find period, high_width and clk_div to suit duty_ns and period_ns.
 114          * Calculate proper div value to keep period value in the bound.
 115          *
 116          * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
 117          * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
 118          *
 119          * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
 120          * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
 121          */
 122         rate = clk_get_rate(mdp->clk_main);
 123         clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
 124                           PWM_PERIOD_BIT_WIDTH;
 125         if (clk_div > PWM_CLKDIV_MAX) {
 126                 if (!mdp->enabled) {
 127                         clk_disable_unprepare(mdp->clk_mm);
 128                         clk_disable_unprepare(mdp->clk_main);
 129                 }
 130                 return -EINVAL;
 131         }
 132
 133         div = NSEC_PER_SEC * (clk_div + 1);
 134         period = mul_u64_u64_div_u64(state->period, rate, div);
 135         if (period > 0)
 136                 period--;
 137
 138         high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
 139         value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
 140
 141         if (mdp->data->bls_debug && !mdp->data->has_commit) {
 142                 /*
 143                  * For MT2701, disable double buffer before writing register
 144                  * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
 145                  */
 146                 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
 147                                          mdp->data->bls_debug_mask,
 148                                          mdp->data->bls_debug_mask);
 149                 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 150                                          mdp->data->con0_sel,
 151                                          mdp->data->con0_sel);
 152         }
 153
 154         mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 155                                  PWM_CLKDIV_MASK,
 156                                  clk_div << PWM_CLKDIV_SHIFT);
 157         mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
 158                                  PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
 159                                  value);
 160
 161         if (mdp->data->has_commit) {
 162                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 163                                          mdp->data->commit_mask,
 164                                          mdp->data->commit_mask);
 165                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 166                                          mdp->data->commit_mask,
 167                                          0x0);
 168         }
 169
 170         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
 171                                  mdp->data->enable_mask);
 172         mdp->enabled = true;
 173
 174         return 0;
 175 }
 176
 177 static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
 178                                   struct pwm_device *pwm,
 179                                   struct pwm_state *state)
 180 {
 181         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 182         u64 rate, period, high_width;
 183         u32 clk_div, pwm_en, con0, con1;
 184         int err;
 185
 186         err = clk_prepare_enable(mdp->clk_main);
 187         if (err < 0) {
 188                 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
 189                 return err;
 190         }
 191
 192         err = clk_prepare_enable(mdp->clk_mm);
 193         if (err < 0) {
 194                 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
 195                 clk_disable_unprepare(mdp->clk_main);
 196                 return err;
 197         }
 198
 199         /*
 200          * Apply DISP_PWM_DEBUG settings to choose whether to enable or disable
 201          * registers double buffer and manual commit to working register before
 202          * performing any read/write operation
 203          */
 204         if (mdp->data->bls_debug)
 205                 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
 206                                          mdp->data->bls_debug_mask,
 207                                          mdp->data->bls_debug_mask);
 208
 209         rate = clk_get_rate(mdp->clk_main);
 210         con0 = readl(mdp->base + mdp->data->con0);
 211         con1 = readl(mdp->base + mdp->data->con1);
 212         pwm_en = readl(mdp->base + DISP_PWM_EN);
 213         state->enabled = !!(pwm_en & mdp->data->enable_mask);
 214         clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
 215         period = FIELD_GET(PWM_PERIOD_MASK, con1);
 216         /*
 217          * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
 218          * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
 219          */
 220         state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
 221         high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
 222         state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
 223                                                rate);
 224         state->polarity = PWM_POLARITY_NORMAL;
 225         clk_disable_unprepare(mdp->clk_mm);
 226         clk_disable_unprepare(mdp->clk_main);
 227
 228         return 0;
 229 }
 230
 231 static const struct pwm_ops mtk_disp_pwm_ops = {
 232         .apply = mtk_disp_pwm_apply,
 233         .get_state = mtk_disp_pwm_get_state,
 234         .owner = THIS_MODULE,
 235 };
 236
 237 static int mtk_disp_pwm_probe(struct platform_device *pdev)
 238 {
 239         struct mtk_disp_pwm *mdp;
 240         int ret;
 241
 242         mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
 243         if (!mdp)
 244                 return -ENOMEM;
 245
 246         mdp->data = of_device_get_match_data(&pdev->dev);
 247
 248         mdp->base = devm_platform_ioremap_resource(pdev, 0);
 249         if (IS_ERR(mdp->base))
 250                 return PTR_ERR(mdp->base);
 251
 252         mdp->clk_main = devm_clk_get(&pdev->dev, "main");
 253         if (IS_ERR(mdp->clk_main))
 254                 return PTR_ERR(mdp->clk_main);
 255
 256         mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
 257         if (IS_ERR(mdp->clk_mm))
 258                 return PTR_ERR(mdp->clk_mm);
 259
 260         mdp->chip.dev = &pdev->dev;
 261         mdp->chip.ops = &mtk_disp_pwm_ops;
 262         mdp->chip.npwm = 1;
 263
 264         ret = pwmchip_add(&mdp->chip);
 265         if (ret < 0) {
 266                 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
 267                 return ret;
 268         }
 269
 270         platform_set_drvdata(pdev, mdp);
 271
 272         return 0;
 273 }
 274
 275 static void mtk_disp_pwm_remove(struct platform_device *pdev)
 276 {
 277         struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
 278
 279         pwmchip_remove(&mdp->chip);
 280 }
 281
 282 static const struct mtk_pwm_data mt2701_pwm_data = {
 283         .enable_mask = BIT(16),
 284         .con0 = 0xa8,
 285         .con0_sel = 0x2,
 286         .con1 = 0xac,
 287         .has_commit = false,
 288         .bls_debug = 0xb0,
 289         .bls_debug_mask = 0x3,
 290 };
 291
 292 static const struct mtk_pwm_data mt8173_pwm_data = {
 293         .enable_mask = BIT(0),
 294         .con0 = 0x10,
 295         .con0_sel = 0x0,
 296         .con1 = 0x14,
 297         .has_commit = true,
 298         .commit = 0x8,
 299         .commit_mask = 0x1,
 300 };
 301
 302 static const struct mtk_pwm_data mt8183_pwm_data = {
 303         .enable_mask = BIT(0),
 304         .con0 = 0x18,
 305         .con0_sel = 0x0,
 306         .con1 = 0x1c,
 307         .has_commit = false,
 308         .bls_debug = 0x80,
 309         .bls_debug_mask = 0x3,
 310 };
 311
 312 static const struct of_device_id mtk_disp_pwm_of_match[] = {
 313         { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
 314         { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
 315         { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
 316         { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
 317         { }
 318 };
 319 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
 320
 321 static struct platform_driver mtk_disp_pwm_driver = {
 322         .driver = {
 323                 .name = "mediatek-disp-pwm",
 324                 .of_match_table = mtk_disp_pwm_of_match,
 325         },
 326         .probe = mtk_disp_pwm_probe,
 327         .remove_new = mtk_disp_pwm_remove,
 328 };
 329 module_platform_driver(mtk_disp_pwm_driver);
 330
 331 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
 332 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
 333 MODULE_LICENSE("GPL v2");