drivers/pwm/pwm-meson.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * PWM controller driver for Amlogic Meson SoCs.
   4  *
   5  * This PWM is only a set of Gates, Dividers and Counters:
   6  * PWM output is achieved by calculating a clock that permits calculating
   7  * two periods (low and high). The counter then has to be set to switch after
   8  * N cycles for the first half period.
   9  * The hardware has no "polarity" setting. This driver reverses the period
  10  * cycles (the low length is inverted with the high length) for
  11  * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
  12  * from the hardware.
  13  * Setting the duty cycle will disable and re-enable the PWM output.
  14  * Disabling the PWM stops the output immediately (without waiting for the
  15  * current period to complete first).
  16  *
  17  * The public S912 (GXM) datasheet contains some documentation for this PWM
  18  * controller starting on page 543:
  19  * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
  20  * An updated version of this IP block is found in S922X (G12B) SoCs. The
  21  * datasheet contains the description for this IP block revision starting at
  22  * page 1084:
  23  * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
  24  *
  25  * Copyright (c) 2016 BayLibre, SAS.
  26  * Author: Neil Armstrong <narmstrong@baylibre.com>
  27  * Copyright (C) 2014 Amlogic, Inc.
  28  */
  29
  30 #include <linux/bitfield.h>
  31 #include <linux/bits.h>
  32 #include <linux/clk.h>
  33 #include <linux/clk-provider.h>
  34 #include <linux/err.h>
  35 #include <linux/io.h>
  36 #include <linux/kernel.h>
  37 #include <linux/math64.h>
  38 #include <linux/module.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/pwm.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #define REG_PWM_A               0x0
  47 #define REG_PWM_B               0x4
  48 #define PWM_LOW_MASK            GENMASK(15, 0)
  49 #define PWM_HIGH_MASK           GENMASK(31, 16)
  50
  51 #define REG_MISC_AB             0x8
  52 #define MISC_B_CLK_EN_SHIFT     23
  53 #define MISC_A_CLK_EN_SHIFT     15
  54 #define MISC_CLK_DIV_WIDTH      7
  55 #define MISC_B_CLK_DIV_SHIFT    16
  56 #define MISC_A_CLK_DIV_SHIFT    8
  57 #define MISC_B_CLK_SEL_SHIFT    6
  58 #define MISC_A_CLK_SEL_SHIFT    4
  59 #define MISC_CLK_SEL_MASK       0x3
  60 #define MISC_B_EN               BIT(1)
  61 #define MISC_A_EN               BIT(0)
  62
  63 #define MESON_NUM_PWMS          2
  64 #define MESON_MAX_MUX_PARENTS   4
  65
  66 static struct meson_pwm_channel_data {
  67         u8              reg_offset;
  68         u8              clk_sel_shift;
  69         u8              clk_div_shift;
  70         u8              clk_en_shift;
  71         u32             pwm_en_mask;
  72 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
  73         {
  74                 .reg_offset     = REG_PWM_A,
  75                 .clk_sel_shift  = MISC_A_CLK_SEL_SHIFT,
  76                 .clk_div_shift  = MISC_A_CLK_DIV_SHIFT,
  77                 .clk_en_shift   = MISC_A_CLK_EN_SHIFT,
  78                 .pwm_en_mask    = MISC_A_EN,
  79         },
  80         {
  81                 .reg_offset     = REG_PWM_B,
  82                 .clk_sel_shift  = MISC_B_CLK_SEL_SHIFT,
  83                 .clk_div_shift  = MISC_B_CLK_DIV_SHIFT,
  84                 .clk_en_shift   = MISC_B_CLK_EN_SHIFT,
  85                 .pwm_en_mask    = MISC_B_EN,
  86         }
  87 };
  88
  89 struct meson_pwm_channel {
  90         unsigned long rate;
  91         unsigned int hi;
  92         unsigned int lo;
  93
  94         struct clk_mux mux;
  95         struct clk_divider div;
  96         struct clk_gate gate;
  97         struct clk *clk;
  98 };
  99
 100 struct meson_pwm_data {
 101         const char * const *parent_names;
 102         unsigned int num_parents;
 103 };
 104
 105 struct meson_pwm {
 106         struct pwm_chip chip;
 107         const struct meson_pwm_data *data;
 108         struct meson_pwm_channel channels[MESON_NUM_PWMS];
 109         void __iomem *base;
 110         /*
 111          * Protects register (write) access to the REG_MISC_AB register
 112          * that is shared between the two PWMs.
 113          */
 114         spinlock_t lock;
 115 };
 116
 117 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
 118 {
 119         return container_of(chip, struct meson_pwm, chip);
 120 }
 121
 122 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 123 {
 124         struct meson_pwm *meson = to_meson_pwm(chip);
 125         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 126         struct device *dev = chip->dev;
 127         int err;
 128
 129         err = clk_prepare_enable(channel->clk);
 130         if (err < 0) {
 131                 dev_err(dev, "failed to enable clock %s: %d\n",
 132                         __clk_get_name(channel->clk), err);
 133                 return err;
 134         }
 135
 136         return 0;
 137 }
 138
 139 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 140 {
 141         struct meson_pwm *meson = to_meson_pwm(chip);
 142         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 143
 144         clk_disable_unprepare(channel->clk);
 145 }
 146
 147 static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
 148                           const struct pwm_state *state)
 149 {
 150         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 151         unsigned int cnt, duty_cnt;
 152         unsigned long fin_freq;
 153         u64 duty, period, freq;
 154
 155         duty = state->duty_cycle;
 156         period = state->period;
 157
 158         /*
 159          * Note this is wrong. The result is an output wave that isn't really
 160          * inverted and so is wrongly identified by .get_state as normal.
 161          * Fixing this needs some care however as some machines might rely on
 162          * this.
 163          */
 164         if (state->polarity == PWM_POLARITY_INVERSED)
 165                 duty = period - duty;
 166
 167         freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
 168         if (freq > ULONG_MAX)
 169                 freq = ULONG_MAX;
 170
 171         fin_freq = clk_round_rate(channel->clk, freq);
 172         if (fin_freq == 0) {
 173                 dev_err(meson->chip.dev, "invalid source clock frequency\n");
 174                 return -EINVAL;
 175         }
 176
 177         dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
 178
 179         cnt = div_u64(fin_freq * period, NSEC_PER_SEC);
 180         if (cnt > 0xffff) {
 181                 dev_err(meson->chip.dev, "unable to get period cnt\n");
 182                 return -EINVAL;
 183         }
 184
 185         dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt);
 186
 187         if (duty == period) {
 188                 channel->hi = cnt;
 189                 channel->lo = 0;
 190         } else if (duty == 0) {
 191                 channel->hi = 0;
 192                 channel->lo = cnt;
 193         } else {
 194                 duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC);
 195
 196                 dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
 197
 198                 channel->hi = duty_cnt;
 199                 channel->lo = cnt - duty_cnt;
 200         }
 201
 202         channel->rate = fin_freq;
 203
 204         return 0;
 205 }
 206
 207 static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
 208 {
 209         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 210         struct meson_pwm_channel_data *channel_data;
 211         unsigned long flags;
 212         u32 value;
 213         int err;
 214
 215         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 216
 217         err = clk_set_rate(channel->clk, channel->rate);
 218         if (err)
 219                 dev_err(meson->chip.dev, "setting clock rate failed\n");
 220
 221         spin_lock_irqsave(&meson->lock, flags);
 222
 223         value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
 224                 FIELD_PREP(PWM_LOW_MASK, channel->lo);
 225         writel(value, meson->base + channel_data->reg_offset);
 226
 227         value = readl(meson->base + REG_MISC_AB);
 228         value |= channel_data->pwm_en_mask;
 229         writel(value, meson->base + REG_MISC_AB);
 230
 231         spin_unlock_irqrestore(&meson->lock, flags);
 232 }
 233
 234 static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
 235 {
 236         unsigned long flags;
 237         u32 value;
 238
 239         spin_lock_irqsave(&meson->lock, flags);
 240
 241         value = readl(meson->base + REG_MISC_AB);
 242         value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
 243         writel(value, meson->base + REG_MISC_AB);
 244
 245         spin_unlock_irqrestore(&meson->lock, flags);
 246 }
 247
 248 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 249                            const struct pwm_state *state)
 250 {
 251         struct meson_pwm *meson = to_meson_pwm(chip);
 252         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 253         int err = 0;
 254
 255         if (!state->enabled) {
 256                 if (state->polarity == PWM_POLARITY_INVERSED) {
 257                         /*
 258                          * This IP block revision doesn't have an "always high"
 259                          * setting which we can use for "inverted disabled".
 260                          * Instead we achieve this by setting mux parent with
 261                          * highest rate and minimum divider value, resulting
 262                          * in the shortest possible duration for one "count"
 263                          * and "period == duty_cycle". This results in a signal
 264                          * which is LOW for one "count", while being HIGH for
 265                          * the rest of the (so the signal is HIGH for slightly
 266                          * less than 100% of the period, but this is the best
 267                          * we can achieve).
 268                          */
 269                         channel->rate = ULONG_MAX;
 270                         channel->hi = ~0;
 271                         channel->lo = 0;
 272
 273                         meson_pwm_enable(meson, pwm);
 274                 } else {
 275                         meson_pwm_disable(meson, pwm);
 276                 }
 277         } else {
 278                 err = meson_pwm_calc(meson, pwm, state);
 279                 if (err < 0)
 280                         return err;
 281
 282                 meson_pwm_enable(meson, pwm);
 283         }
 284
 285         return 0;
 286 }
 287
 288 static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
 289                                u32 cnt)
 290 {
 291         struct meson_pwm *meson = to_meson_pwm(chip);
 292         struct meson_pwm_channel *channel;
 293         unsigned long fin_freq;
 294
 295         /* to_meson_pwm() can only be used after .get_state() is called */
 296         channel = &meson->channels[pwm->hwpwm];
 297
 298         fin_freq = clk_get_rate(channel->clk);
 299         if (fin_freq == 0)
 300                 return 0;
 301
 302         return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
 303 }
 304
 305 static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 306                                struct pwm_state *state)
 307 {
 308         struct meson_pwm *meson = to_meson_pwm(chip);
 309         struct meson_pwm_channel_data *channel_data;
 310         struct meson_pwm_channel *channel;
 311         u32 value;
 312
 313         if (!state)
 314                 return 0;
 315
 316         channel = &meson->channels[pwm->hwpwm];
 317         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 318
 319         value = readl(meson->base + REG_MISC_AB);
 320         state->enabled = value & channel_data->pwm_en_mask;
 321
 322         value = readl(meson->base + channel_data->reg_offset);
 323         channel->lo = FIELD_GET(PWM_LOW_MASK, value);
 324         channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
 325
 326         state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
 327         state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
 328
 329         state->polarity = PWM_POLARITY_NORMAL;
 330
 331         return 0;
 332 }
 333
 334 static const struct pwm_ops meson_pwm_ops = {
 335         .request = meson_pwm_request,
 336         .free = meson_pwm_free,
 337         .apply = meson_pwm_apply,
 338         .get_state = meson_pwm_get_state,
 339         .owner = THIS_MODULE,
 340 };
 341
 342 static const char * const pwm_meson8b_parent_names[] = {
 343         "xtal", NULL, "fclk_div4", "fclk_div3"
 344 };
 345
 346 static const struct meson_pwm_data pwm_meson8b_data = {
 347         .parent_names = pwm_meson8b_parent_names,
 348         .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
 349 };
 350
 351 /*
 352  * Only the 2 first inputs of the GXBB AO PWMs are valid
 353  * The last 2 are grounded
 354  */
 355 static const char * const pwm_gxbb_ao_parent_names[] = {
 356         "xtal", "clk81"
 357 };
 358
 359 static const struct meson_pwm_data pwm_gxbb_ao_data = {
 360         .parent_names = pwm_gxbb_ao_parent_names,
 361         .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
 362 };
 363
 364 static const char * const pwm_axg_ee_parent_names[] = {
 365         "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
 366 };
 367
 368 static const struct meson_pwm_data pwm_axg_ee_data = {
 369         .parent_names = pwm_axg_ee_parent_names,
 370         .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
 371 };
 372
 373 static const char * const pwm_axg_ao_parent_names[] = {
 374         "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5"
 375 };
 376
 377 static const struct meson_pwm_data pwm_axg_ao_data = {
 378         .parent_names = pwm_axg_ao_parent_names,
 379         .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
 380 };
 381
 382 static const char * const pwm_g12a_ao_ab_parent_names[] = {
 383         "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5"
 384 };
 385
 386 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
 387         .parent_names = pwm_g12a_ao_ab_parent_names,
 388         .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
 389 };
 390
 391 static const char * const pwm_g12a_ao_cd_parent_names[] = {
 392         "xtal", "g12a_ao_clk81",
 393 };
 394
 395 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
 396         .parent_names = pwm_g12a_ao_cd_parent_names,
 397         .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
 398 };
 399
 400 static const struct of_device_id meson_pwm_matches[] = {
 401         {
 402                 .compatible = "amlogic,meson8b-pwm",
 403                 .data = &pwm_meson8b_data
 404         },
 405         {
 406                 .compatible = "amlogic,meson-gxbb-pwm",
 407                 .data = &pwm_meson8b_data
 408         },
 409         {
 410                 .compatible = "amlogic,meson-gxbb-ao-pwm",
 411                 .data = &pwm_gxbb_ao_data
 412         },
 413         {
 414                 .compatible = "amlogic,meson-axg-ee-pwm",
 415                 .data = &pwm_axg_ee_data
 416         },
 417         {
 418                 .compatible = "amlogic,meson-axg-ao-pwm",
 419                 .data = &pwm_axg_ao_data
 420         },
 421         {
 422                 .compatible = "amlogic,meson-g12a-ee-pwm",
 423                 .data = &pwm_meson8b_data
 424         },
 425         {
 426                 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
 427                 .data = &pwm_g12a_ao_ab_data
 428         },
 429         {
 430                 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
 431                 .data = &pwm_g12a_ao_cd_data
 432         },
 433         {},
 434 };
 435 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
 436
 437 static int meson_pwm_init_channels(struct meson_pwm *meson)
 438 {
 439         struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {};
 440         struct device *dev = meson->chip.dev;
 441         unsigned int i;
 442         char name[255];
 443         int err;
 444
 445         for (i = 0; i < meson->data->num_parents; i++) {
 446                 mux_parent_data[i].index = -1;
 447                 mux_parent_data[i].name = meson->data->parent_names[i];
 448         }
 449
 450         for (i = 0; i < meson->chip.npwm; i++) {
 451                 struct meson_pwm_channel *channel = &meson->channels[i];
 452                 struct clk_parent_data div_parent = {}, gate_parent = {};
 453                 struct clk_init_data init = {};
 454
 455                 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
 456
 457                 init.name = name;
 458                 init.ops = &clk_mux_ops;
 459                 init.flags = 0;
 460                 init.parent_data = mux_parent_data;
 461                 init.num_parents = meson->data->num_parents;
 462
 463                 channel->mux.reg = meson->base + REG_MISC_AB;
 464                 channel->mux.shift =
 465                                 meson_pwm_per_channel_data[i].clk_sel_shift;
 466                 channel->mux.mask = MISC_CLK_SEL_MASK;
 467                 channel->mux.flags = 0;
 468                 channel->mux.lock = &meson->lock;
 469                 channel->mux.table = NULL;
 470                 channel->mux.hw.init = &init;
 471
 472                 err = devm_clk_hw_register(dev, &channel->mux.hw);
 473                 if (err) {
 474                         dev_err(dev, "failed to register %s: %d\n", name, err);
 475                         return err;
 476                 }
 477
 478                 snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i);
 479
 480                 init.name = name;
 481                 init.ops = &clk_divider_ops;
 482                 init.flags = CLK_SET_RATE_PARENT;
 483                 div_parent.index = -1;
 484                 div_parent.hw = &channel->mux.hw;
 485                 init.parent_data = &div_parent;
 486                 init.num_parents = 1;
 487
 488                 channel->div.reg = meson->base + REG_MISC_AB;
 489                 channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
 490                 channel->div.width = MISC_CLK_DIV_WIDTH;
 491                 channel->div.hw.init = &init;
 492                 channel->div.flags = 0;
 493                 channel->div.lock = &meson->lock;
 494
 495                 err = devm_clk_hw_register(dev, &channel->div.hw);
 496                 if (err) {
 497                         dev_err(dev, "failed to register %s: %d\n", name, err);
 498                         return err;
 499                 }
 500
 501                 snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i);
 502
 503                 init.name = name;
 504                 init.ops = &clk_gate_ops;
 505                 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
 506                 gate_parent.index = -1;
 507                 gate_parent.hw = &channel->div.hw;
 508                 init.parent_data = &gate_parent;
 509                 init.num_parents = 1;
 510
 511                 channel->gate.reg = meson->base + REG_MISC_AB;
 512                 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
 513                 channel->gate.hw.init = &init;
 514                 channel->gate.flags = 0;
 515                 channel->gate.lock = &meson->lock;
 516
 517                 err = devm_clk_hw_register(dev, &channel->gate.hw);
 518                 if (err) {
 519                         dev_err(dev, "failed to register %s: %d\n", name, err);
 520                         return err;
 521                 }
 522
 523                 channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
 524                 if (IS_ERR(channel->clk)) {
 525                         err = PTR_ERR(channel->clk);
 526                         dev_err(dev, "failed to register %s: %d\n", name, err);
 527                         return err;
 528                 }
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int meson_pwm_probe(struct platform_device *pdev)
 535 {
 536         struct meson_pwm *meson;
 537         int err;
 538
 539         meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
 540         if (!meson)
 541                 return -ENOMEM;
 542
 543         meson->base = devm_platform_ioremap_resource(pdev, 0);
 544         if (IS_ERR(meson->base))
 545                 return PTR_ERR(meson->base);
 546
 547         spin_lock_init(&meson->lock);
 548         meson->chip.dev = &pdev->dev;
 549         meson->chip.ops = &meson_pwm_ops;
 550         meson->chip.npwm = MESON_NUM_PWMS;
 551
 552         meson->data = of_device_get_match_data(&pdev->dev);
 553
 554         err = meson_pwm_init_channels(meson);
 555         if (err < 0)
 556                 return err;
 557
 558         err = devm_pwmchip_add(&pdev->dev, &meson->chip);
 559         if (err < 0) {
 560                 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
 561                 return err;
 562         }
 563
 564         return 0;
 565 }
 566
 567 static struct platform_driver meson_pwm_driver = {
 568         .driver = {
 569                 .name = "meson-pwm",
 570                 .of_match_table = meson_pwm_matches,
 571         },
 572         .probe = meson_pwm_probe,
 573 };
 574 module_platform_driver(meson_pwm_driver);
 575
 576 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
 577 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 578 MODULE_LICENSE("Dual BSD/GPL");