drivers/pwm/pwm-meson.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * PWM controller driver for Amlogic Meson SoCs.
   4  *
   5  * This PWM is only a set of Gates, Dividers and Counters:
   6  * PWM output is achieved by calculating a clock that permits calculating
   7  * two periods (low and high). The counter then has to be set to switch after
   8  * N cycles for the first half period.
   9  * The hardware has no "polarity" setting. This driver reverses the period
  10  * cycles (the low length is inverted with the high length) for
  11  * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
  12  * from the hardware.
  13  * Setting the duty cycle will disable and re-enable the PWM output.
  14  * Disabling the PWM stops the output immediately (without waiting for the
  15  * current period to complete first).
  16  *
  17  * The public S912 (GXM) datasheet contains some documentation for this PWM
  18  * controller starting on page 543:
  19  * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
  20  * An updated version of this IP block is found in S922X (G12B) SoCs. The
  21  * datasheet contains the description for this IP block revision starting at
  22  * page 1084:
  23  * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
  24  *
  25  * Copyright (c) 2016 BayLibre, SAS.
  26  * Author: Neil Armstrong <narmstrong@baylibre.com>
  27  * Copyright (C) 2014 Amlogic, Inc.
  28  */
  29
  30 #include <linux/bitfield.h>
  31 #include <linux/bits.h>
  32 #include <linux/clk.h>
  33 #include <linux/clk-provider.h>
  34 #include <linux/err.h>
  35 #include <linux/io.h>
  36 #include <linux/kernel.h>
  37 #include <linux/math64.h>
  38 #include <linux/module.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/pwm.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #define REG_PWM_A               0x0
  47 #define REG_PWM_B               0x4
  48 #define PWM_LOW_MASK            GENMASK(15, 0)
  49 #define PWM_HIGH_MASK           GENMASK(31, 16)
  50
  51 #define REG_MISC_AB             0x8
  52 #define MISC_B_CLK_EN           BIT(23)
  53 #define MISC_A_CLK_EN           BIT(15)
  54 #define MISC_CLK_DIV_MASK       0x7f
  55 #define MISC_B_CLK_DIV_SHIFT    16
  56 #define MISC_A_CLK_DIV_SHIFT    8
  57 #define MISC_B_CLK_SEL_SHIFT    6
  58 #define MISC_A_CLK_SEL_SHIFT    4
  59 #define MISC_CLK_SEL_MASK       0x3
  60 #define MISC_B_EN               BIT(1)
  61 #define MISC_A_EN               BIT(0)
  62
  63 #define MESON_NUM_PWMS          2
  64
  65 static struct meson_pwm_channel_data {
  66         u8              reg_offset;
  67         u8              clk_sel_shift;
  68         u8              clk_div_shift;
  69         u32             clk_en_mask;
  70         u32             pwm_en_mask;
  71 } meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
  72         {
  73                 .reg_offset     = REG_PWM_A,
  74                 .clk_sel_shift  = MISC_A_CLK_SEL_SHIFT,
  75                 .clk_div_shift  = MISC_A_CLK_DIV_SHIFT,
  76                 .clk_en_mask    = MISC_A_CLK_EN,
  77                 .pwm_en_mask    = MISC_A_EN,
  78         },
  79         {
  80                 .reg_offset     = REG_PWM_B,
  81                 .clk_sel_shift  = MISC_B_CLK_SEL_SHIFT,
  82                 .clk_div_shift  = MISC_B_CLK_DIV_SHIFT,
  83                 .clk_en_mask    = MISC_B_CLK_EN,
  84                 .pwm_en_mask    = MISC_B_EN,
  85         }
  86 };
  87
  88 struct meson_pwm_channel {
  89         unsigned int hi;
  90         unsigned int lo;
  91         u8 pre_div;
  92
  93         struct clk *clk_parent;
  94         struct clk_mux mux;
  95         struct clk *clk;
  96 };
  97
  98 struct meson_pwm_data {
  99         const char * const *parent_names;
 100         unsigned int num_parents;
 101 };
 102
 103 struct meson_pwm {
 104         struct pwm_chip chip;
 105         const struct meson_pwm_data *data;
 106         struct meson_pwm_channel channels[MESON_NUM_PWMS];
 107         void __iomem *base;
 108         /*
 109          * Protects register (write) access to the REG_MISC_AB register
 110          * that is shared between the two PWMs.
 111          */
 112         spinlock_t lock;
 113 };
 114
 115 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
 116 {
 117         return container_of(chip, struct meson_pwm, chip);
 118 }
 119
 120 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
 121 {
 122         struct meson_pwm *meson = to_meson_pwm(chip);
 123         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 124         struct device *dev = chip->dev;
 125         int err;
 126
 127         if (channel->clk_parent) {
 128                 err = clk_set_parent(channel->clk, channel->clk_parent);
 129                 if (err < 0) {
 130                         dev_err(dev, "failed to set parent %s for %s: %d\n",
 131                                 __clk_get_name(channel->clk_parent),
 132                                 __clk_get_name(channel->clk), err);
 133                         return err;
 134                 }
 135         }
 136
 137         err = clk_prepare_enable(channel->clk);
 138         if (err < 0) {
 139                 dev_err(dev, "failed to enable clock %s: %d\n",
 140                         __clk_get_name(channel->clk), err);
 141                 return err;
 142         }
 143
 144         return 0;
 145 }
 146
 147 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 148 {
 149         struct meson_pwm *meson = to_meson_pwm(chip);
 150         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 151
 152         clk_disable_unprepare(channel->clk);
 153 }
 154
 155 static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
 156                           const struct pwm_state *state)
 157 {
 158         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 159         unsigned int duty, period, pre_div, cnt, duty_cnt;
 160         unsigned long fin_freq;
 161
 162         duty = state->duty_cycle;
 163         period = state->period;
 164
 165         /*
 166          * Note this is wrong. The result is an output wave that isn't really
 167          * inverted and so is wrongly identified by .get_state as normal.
 168          * Fixing this needs some care however as some machines might rely on
 169          * this.
 170          */
 171         if (state->polarity == PWM_POLARITY_INVERSED)
 172                 duty = period - duty;
 173
 174         fin_freq = clk_get_rate(channel->clk);
 175         if (fin_freq == 0) {
 176                 dev_err(meson->chip.dev, "invalid source clock frequency\n");
 177                 return -EINVAL;
 178         }
 179
 180         dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
 181
 182         pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
 183         if (pre_div > MISC_CLK_DIV_MASK) {
 184                 dev_err(meson->chip.dev, "unable to get period pre_div\n");
 185                 return -EINVAL;
 186         }
 187
 188         cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
 189         if (cnt > 0xffff) {
 190                 dev_err(meson->chip.dev, "unable to get period cnt\n");
 191                 return -EINVAL;
 192         }
 193
 194         dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
 195                 pre_div, cnt);
 196
 197         if (duty == period) {
 198                 channel->pre_div = pre_div;
 199                 channel->hi = cnt;
 200                 channel->lo = 0;
 201         } else if (duty == 0) {
 202                 channel->pre_div = pre_div;
 203                 channel->hi = 0;
 204                 channel->lo = cnt;
 205         } else {
 206                 /* Then check is we can have the duty with the same pre_div */
 207                 duty_cnt = div64_u64(fin_freq * (u64)duty,
 208                                      NSEC_PER_SEC * (pre_div + 1));
 209                 if (duty_cnt > 0xffff) {
 210                         dev_err(meson->chip.dev, "unable to get duty cycle\n");
 211                         return -EINVAL;
 212                 }
 213
 214                 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
 215                         duty, pre_div, duty_cnt);
 216
 217                 channel->pre_div = pre_div;
 218                 channel->hi = duty_cnt;
 219                 channel->lo = cnt - duty_cnt;
 220         }
 221
 222         return 0;
 223 }
 224
 225 static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
 226 {
 227         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 228         struct meson_pwm_channel_data *channel_data;
 229         unsigned long flags;
 230         u32 value;
 231
 232         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 233
 234         spin_lock_irqsave(&meson->lock, flags);
 235
 236         value = readl(meson->base + REG_MISC_AB);
 237         value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
 238         value |= channel->pre_div << channel_data->clk_div_shift;
 239         value |= channel_data->clk_en_mask;
 240         writel(value, meson->base + REG_MISC_AB);
 241
 242         value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
 243                 FIELD_PREP(PWM_LOW_MASK, channel->lo);
 244         writel(value, meson->base + channel_data->reg_offset);
 245
 246         value = readl(meson->base + REG_MISC_AB);
 247         value |= channel_data->pwm_en_mask;
 248         writel(value, meson->base + REG_MISC_AB);
 249
 250         spin_unlock_irqrestore(&meson->lock, flags);
 251 }
 252
 253 static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
 254 {
 255         unsigned long flags;
 256         u32 value;
 257
 258         spin_lock_irqsave(&meson->lock, flags);
 259
 260         value = readl(meson->base + REG_MISC_AB);
 261         value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
 262         writel(value, meson->base + REG_MISC_AB);
 263
 264         spin_unlock_irqrestore(&meson->lock, flags);
 265 }
 266
 267 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 268                            const struct pwm_state *state)
 269 {
 270         struct meson_pwm *meson = to_meson_pwm(chip);
 271         struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
 272         int err = 0;
 273
 274         if (!state->enabled) {
 275                 if (state->polarity == PWM_POLARITY_INVERSED) {
 276                         /*
 277                          * This IP block revision doesn't have an "always high"
 278                          * setting which we can use for "inverted disabled".
 279                          * Instead we achieve this using the same settings
 280                          * that we use a pre_div of 0 (to get the shortest
 281                          * possible duration for one "count") and
 282                          * "period == duty_cycle". This results in a signal
 283                          * which is LOW for one "count", while being HIGH for
 284                          * the rest of the (so the signal is HIGH for slightly
 285                          * less than 100% of the period, but this is the best
 286                          * we can achieve).
 287                          */
 288                         channel->pre_div = 0;
 289                         channel->hi = ~0;
 290                         channel->lo = 0;
 291
 292                         meson_pwm_enable(meson, pwm);
 293                 } else {
 294                         meson_pwm_disable(meson, pwm);
 295                 }
 296         } else {
 297                 err = meson_pwm_calc(meson, pwm, state);
 298                 if (err < 0)
 299                         return err;
 300
 301                 meson_pwm_enable(meson, pwm);
 302         }
 303
 304         return 0;
 305 }
 306
 307 static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
 308                                         struct pwm_device *pwm, u32 cnt)
 309 {
 310         struct meson_pwm *meson = to_meson_pwm(chip);
 311         struct meson_pwm_channel *channel;
 312         unsigned long fin_freq;
 313         u32 fin_ns;
 314
 315         /* to_meson_pwm() can only be used after .get_state() is called */
 316         channel = &meson->channels[pwm->hwpwm];
 317
 318         fin_freq = clk_get_rate(channel->clk);
 319         if (fin_freq == 0)
 320                 return 0;
 321
 322         fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
 323
 324         return cnt * fin_ns * (channel->pre_div + 1);
 325 }
 326
 327 static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 328                                struct pwm_state *state)
 329 {
 330         struct meson_pwm *meson = to_meson_pwm(chip);
 331         struct meson_pwm_channel_data *channel_data;
 332         struct meson_pwm_channel *channel;
 333         u32 value, tmp;
 334
 335         if (!state)
 336                 return 0;
 337
 338         channel = &meson->channels[pwm->hwpwm];
 339         channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
 340
 341         value = readl(meson->base + REG_MISC_AB);
 342
 343         tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
 344         state->enabled = (value & tmp) == tmp;
 345
 346         tmp = value >> channel_data->clk_div_shift;
 347         channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
 348
 349         value = readl(meson->base + channel_data->reg_offset);
 350
 351         channel->lo = FIELD_GET(PWM_LOW_MASK, value);
 352         channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
 353
 354         if (channel->lo == 0) {
 355                 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
 356                 state->duty_cycle = state->period;
 357         } else if (channel->lo >= channel->hi) {
 358                 state->period = meson_pwm_cnt_to_ns(chip, pwm,
 359                                                     channel->lo + channel->hi);
 360                 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
 361                                                         channel->hi);
 362         } else {
 363                 state->period = 0;
 364                 state->duty_cycle = 0;
 365         }
 366
 367         state->polarity = PWM_POLARITY_NORMAL;
 368
 369         return 0;
 370 }
 371
 372 static const struct pwm_ops meson_pwm_ops = {
 373         .request = meson_pwm_request,
 374         .free = meson_pwm_free,
 375         .apply = meson_pwm_apply,
 376         .get_state = meson_pwm_get_state,
 377         .owner = THIS_MODULE,
 378 };
 379
 380 static const char * const pwm_meson8b_parent_names[] = {
 381         "xtal", "vid_pll", "fclk_div4", "fclk_div3"
 382 };
 383
 384 static const struct meson_pwm_data pwm_meson8b_data = {
 385         .parent_names = pwm_meson8b_parent_names,
 386         .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
 387 };
 388
 389 static const char * const pwm_gxbb_parent_names[] = {
 390         "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
 391 };
 392
 393 static const struct meson_pwm_data pwm_gxbb_data = {
 394         .parent_names = pwm_gxbb_parent_names,
 395         .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
 396 };
 397
 398 /*
 399  * Only the 2 first inputs of the GXBB AO PWMs are valid
 400  * The last 2 are grounded
 401  */
 402 static const char * const pwm_gxbb_ao_parent_names[] = {
 403         "xtal", "clk81"
 404 };
 405
 406 static const struct meson_pwm_data pwm_gxbb_ao_data = {
 407         .parent_names = pwm_gxbb_ao_parent_names,
 408         .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
 409 };
 410
 411 static const char * const pwm_axg_ee_parent_names[] = {
 412         "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
 413 };
 414
 415 static const struct meson_pwm_data pwm_axg_ee_data = {
 416         .parent_names = pwm_axg_ee_parent_names,
 417         .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
 418 };
 419
 420 static const char * const pwm_axg_ao_parent_names[] = {
 421         "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5"
 422 };
 423
 424 static const struct meson_pwm_data pwm_axg_ao_data = {
 425         .parent_names = pwm_axg_ao_parent_names,
 426         .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
 427 };
 428
 429 static const char * const pwm_g12a_ao_ab_parent_names[] = {
 430         "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5"
 431 };
 432
 433 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
 434         .parent_names = pwm_g12a_ao_ab_parent_names,
 435         .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
 436 };
 437
 438 static const char * const pwm_g12a_ao_cd_parent_names[] = {
 439         "xtal", "g12a_ao_clk81",
 440 };
 441
 442 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
 443         .parent_names = pwm_g12a_ao_cd_parent_names,
 444         .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
 445 };
 446
 447 static const char * const pwm_g12a_ee_parent_names[] = {
 448         "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
 449 };
 450
 451 static const struct meson_pwm_data pwm_g12a_ee_data = {
 452         .parent_names = pwm_g12a_ee_parent_names,
 453         .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
 454 };
 455
 456 static const struct of_device_id meson_pwm_matches[] = {
 457         {
 458                 .compatible = "amlogic,meson8b-pwm",
 459                 .data = &pwm_meson8b_data
 460         },
 461         {
 462                 .compatible = "amlogic,meson-gxbb-pwm",
 463                 .data = &pwm_gxbb_data
 464         },
 465         {
 466                 .compatible = "amlogic,meson-gxbb-ao-pwm",
 467                 .data = &pwm_gxbb_ao_data
 468         },
 469         {
 470                 .compatible = "amlogic,meson-axg-ee-pwm",
 471                 .data = &pwm_axg_ee_data
 472         },
 473         {
 474                 .compatible = "amlogic,meson-axg-ao-pwm",
 475                 .data = &pwm_axg_ao_data
 476         },
 477         {
 478                 .compatible = "amlogic,meson-g12a-ee-pwm",
 479                 .data = &pwm_g12a_ee_data
 480         },
 481         {
 482                 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
 483                 .data = &pwm_g12a_ao_ab_data
 484         },
 485         {
 486                 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
 487                 .data = &pwm_g12a_ao_cd_data
 488         },
 489         {},
 490 };
 491 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
 492
 493 static int meson_pwm_init_channels(struct meson_pwm *meson)
 494 {
 495         struct device *dev = meson->chip.dev;
 496         struct clk_init_data init;
 497         unsigned int i;
 498         char name[255];
 499         int err;
 500
 501         for (i = 0; i < meson->chip.npwm; i++) {
 502                 struct meson_pwm_channel *channel = &meson->channels[i];
 503
 504                 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
 505
 506                 init.name = name;
 507                 init.ops = &clk_mux_ops;
 508                 init.flags = 0;
 509                 init.parent_names = meson->data->parent_names;
 510                 init.num_parents = meson->data->num_parents;
 511
 512                 channel->mux.reg = meson->base + REG_MISC_AB;
 513                 channel->mux.shift =
 514                                 meson_pwm_per_channel_data[i].clk_sel_shift;
 515                 channel->mux.mask = MISC_CLK_SEL_MASK;
 516                 channel->mux.flags = 0;
 517                 channel->mux.lock = &meson->lock;
 518                 channel->mux.table = NULL;
 519                 channel->mux.hw.init = &init;
 520
 521                 channel->clk = devm_clk_register(dev, &channel->mux.hw);
 522                 if (IS_ERR(channel->clk)) {
 523                         err = PTR_ERR(channel->clk);
 524                         dev_err(dev, "failed to register %s: %d\n", name, err);
 525                         return err;
 526                 }
 527
 528                 snprintf(name, sizeof(name), "clkin%u", i);
 529
 530                 channel->clk_parent = devm_clk_get_optional(dev, name);
 531                 if (IS_ERR(channel->clk_parent))
 532                         return PTR_ERR(channel->clk_parent);
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int meson_pwm_probe(struct platform_device *pdev)
 539 {
 540         struct meson_pwm *meson;
 541         int err;
 542
 543         meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
 544         if (!meson)
 545                 return -ENOMEM;
 546
 547         meson->base = devm_platform_ioremap_resource(pdev, 0);
 548         if (IS_ERR(meson->base))
 549                 return PTR_ERR(meson->base);
 550
 551         spin_lock_init(&meson->lock);
 552         meson->chip.dev = &pdev->dev;
 553         meson->chip.ops = &meson_pwm_ops;
 554         meson->chip.npwm = MESON_NUM_PWMS;
 555
 556         meson->data = of_device_get_match_data(&pdev->dev);
 557
 558         err = meson_pwm_init_channels(meson);
 559         if (err < 0)
 560                 return err;
 561
 562         err = devm_pwmchip_add(&pdev->dev, &meson->chip);
 563         if (err < 0) {
 564                 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
 565                 return err;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static struct platform_driver meson_pwm_driver = {
 572         .driver = {
 573                 .name = "meson-pwm",
 574                 .of_match_table = meson_pwm_matches,
 575         },
 576         .probe = meson_pwm_probe,
 577 };
 578 module_platform_driver(meson_pwm_driver);
 579
 580 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
 581 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 582 MODULE_LICENSE("Dual BSD/GPL");