1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek Pulse Width Modulator driver
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
10 #include <linux/err.h>
12 #include <linux/ioport.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/clk.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pwm.h>
20 #include <linux/slab.h>
21 #include <linux/types.h>
23 /* PWM registers and bits definitions */
28 #define PWMWAVENUM 0x28
29 #define PWMDWIDTH 0x2c
30 #define PWM45DWIDTH_FIXUP 0x30
32 #define PWM45THRES_FIXUP 0x34
33 #define PWM_CK_26M_SEL 0x210
35 #define PWM_CLK_DIV_MAX 7
37 struct pwm_mediatek_of_data {
38 unsigned int num_pwms;
41 const unsigned int *reg_offset;
45 * struct pwm_mediatek_chip - struct representing PWM chip
46 * @chip: linux PWM chip representation
47 * @regs: base address of PWM chip
48 * @clk_top: the top clock generator
49 * @clk_main: the clock used by PWM core
50 * @clk_pwms: the clock used by each PWM channel
51 * @clk_freq: the fix clock frequency of legacy MIPS SoC
52 * @soc: pointer to chip's platform data
54 struct pwm_mediatek_chip {
59 struct clk **clk_pwms;
60 const struct pwm_mediatek_of_data *soc;
63 static const unsigned int mtk_pwm_reg_offset_v1[] = {
64 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
67 static const unsigned int mtk_pwm_reg_offset_v2[] = {
68 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
71 static inline struct pwm_mediatek_chip *
72 to_pwm_mediatek_chip(struct pwm_chip *chip)
74 return container_of(chip, struct pwm_mediatek_chip, chip);
77 static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
78 struct pwm_device *pwm)
80 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
83 ret = clk_prepare_enable(pc->clk_top);
87 ret = clk_prepare_enable(pc->clk_main);
91 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
93 goto disable_clk_main;
98 clk_disable_unprepare(pc->clk_main);
100 clk_disable_unprepare(pc->clk_top);
105 static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
106 struct pwm_device *pwm)
108 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
110 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
111 clk_disable_unprepare(pc->clk_main);
112 clk_disable_unprepare(pc->clk_top);
115 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
116 unsigned int num, unsigned int offset,
119 writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
122 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
123 int duty_ns, int period_ns)
125 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
126 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
127 reg_thres = PWMTHRES;
131 ret = pwm_mediatek_clk_enable(chip, pwm);
136 /* Make sure we use the bus clock and not the 26MHz clock */
137 if (pc->soc->has_ck_26m_sel)
138 writel(0, pc->regs + PWM_CK_26M_SEL);
140 /* Using resolution in picosecond gets accuracy higher */
141 resolution = (u64)NSEC_PER_SEC * 1000;
142 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
144 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
145 while (cnt_period > 8191) {
148 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
152 if (clkdiv > PWM_CLK_DIV_MAX) {
153 pwm_mediatek_clk_disable(chip, pwm);
154 dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
158 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
160 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
161 * from the other PWMs on MT7623.
163 reg_width = PWM45DWIDTH_FIXUP;
164 reg_thres = PWM45THRES_FIXUP;
167 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
168 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
170 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
172 pwm_mediatek_clk_disable(chip, pwm);
177 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
179 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
183 ret = pwm_mediatek_clk_enable(chip, pwm);
187 value = readl(pc->regs);
188 value |= BIT(pwm->hwpwm);
189 writel(value, pc->regs);
194 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
196 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
199 value = readl(pc->regs);
200 value &= ~BIT(pwm->hwpwm);
201 writel(value, pc->regs);
203 pwm_mediatek_clk_disable(chip, pwm);
206 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
207 const struct pwm_state *state)
211 if (state->polarity != PWM_POLARITY_NORMAL)
214 if (!state->enabled) {
215 if (pwm->state.enabled)
216 pwm_mediatek_disable(chip, pwm);
221 err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
225 if (!pwm->state.enabled)
226 err = pwm_mediatek_enable(chip, pwm);
231 static const struct pwm_ops pwm_mediatek_ops = {
232 .apply = pwm_mediatek_apply,
233 .owner = THIS_MODULE,
236 static int pwm_mediatek_probe(struct platform_device *pdev)
238 struct pwm_mediatek_chip *pc;
242 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
246 pc->soc = of_device_get_match_data(&pdev->dev);
248 pc->regs = devm_platform_ioremap_resource(pdev, 0);
249 if (IS_ERR(pc->regs))
250 return PTR_ERR(pc->regs);
252 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
253 sizeof(*pc->clk_pwms), GFP_KERNEL);
257 pc->clk_top = devm_clk_get(&pdev->dev, "top");
258 if (IS_ERR(pc->clk_top))
259 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
260 "Failed to get top clock\n");
262 pc->clk_main = devm_clk_get(&pdev->dev, "main");
263 if (IS_ERR(pc->clk_main))
264 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
265 "Failed to get main clock\n");
267 for (i = 0; i < pc->soc->num_pwms; i++) {
270 snprintf(name, sizeof(name), "pwm%d", i + 1);
272 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
273 if (IS_ERR(pc->clk_pwms[i]))
274 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
275 "Failed to get %s clock\n", name);
278 pc->chip.dev = &pdev->dev;
279 pc->chip.ops = &pwm_mediatek_ops;
280 pc->chip.npwm = pc->soc->num_pwms;
282 ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
284 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
289 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
291 .pwm45_fixup = false,
292 .has_ck_26m_sel = false,
293 .reg_offset = mtk_pwm_reg_offset_v1,
296 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
298 .pwm45_fixup = false,
299 .has_ck_26m_sel = false,
300 .reg_offset = mtk_pwm_reg_offset_v1,
303 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
305 .pwm45_fixup = false,
306 .has_ck_26m_sel = true,
307 .reg_offset = mtk_pwm_reg_offset_v1,
310 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
313 .has_ck_26m_sel = false,
314 .reg_offset = mtk_pwm_reg_offset_v1,
317 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
320 .has_ck_26m_sel = false,
321 .reg_offset = mtk_pwm_reg_offset_v1,
324 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
326 .pwm45_fixup = false,
327 .has_ck_26m_sel = false,
328 .reg_offset = mtk_pwm_reg_offset_v1,
331 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
333 .pwm45_fixup = false,
334 .has_ck_26m_sel = true,
335 .reg_offset = mtk_pwm_reg_offset_v2,
338 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
340 .pwm45_fixup = false,
341 .has_ck_26m_sel = true,
342 .reg_offset = mtk_pwm_reg_offset_v1,
345 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
347 .pwm45_fixup = false,
348 .has_ck_26m_sel = true,
349 .reg_offset = mtk_pwm_reg_offset_v1,
352 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
354 .pwm45_fixup = false,
355 .has_ck_26m_sel = true,
356 .reg_offset = mtk_pwm_reg_offset_v1,
359 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
361 .pwm45_fixup = false,
362 .has_ck_26m_sel = true,
363 .reg_offset = mtk_pwm_reg_offset_v1,
366 static const struct of_device_id pwm_mediatek_of_match[] = {
367 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
368 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
369 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
370 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
371 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
372 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
373 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
374 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
375 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
376 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
377 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
380 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
382 static struct platform_driver pwm_mediatek_driver = {
384 .name = "pwm-mediatek",
385 .of_match_table = pwm_mediatek_of_match,
387 .probe = pwm_mediatek_probe,
389 module_platform_driver(pwm_mediatek_driver);
391 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
392 MODULE_LICENSE("GPL v2");