USB: serial: cp210x: add cp210x-stlink driver
[platform/kernel/linux-rpi.git] / drivers / pwm / pwm-lpss.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel Low Power Subsystem PWM controller driver
4  *
5  * Copyright (C) 2014, Intel Corporation
6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7  * Author: Chew Kean Ho <kean.ho.chew@intel.com>
8  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
9  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
10  * Author: Alan Cox <alan@linux.intel.com>
11  */
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/time.h>
20
21 #include "pwm-lpss.h"
22
23 #define PWM                             0x00000000
24 #define PWM_ENABLE                      BIT(31)
25 #define PWM_SW_UPDATE                   BIT(30)
26 #define PWM_BASE_UNIT_SHIFT             8
27 #define PWM_ON_TIME_DIV_MASK            0x000000ff
28
29 /* Size of each PWM register space if multiple */
30 #define PWM_SIZE                        0x400
31
32 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
33 {
34         return container_of(chip, struct pwm_lpss_chip, chip);
35 }
36
37 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
38 {
39         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
40
41         return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
42 }
43
44 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
45 {
46         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
47
48         writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
49 }
50
51 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
52 {
53         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
54         const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
55         const unsigned int ms = 500 * USEC_PER_MSEC;
56         u32 val;
57         int err;
58
59         /*
60          * PWM Configuration register has SW_UPDATE bit that is set when a new
61          * configuration is written to the register. The bit is automatically
62          * cleared at the start of the next output cycle by the IP block.
63          *
64          * If one writes a new configuration to the register while it still has
65          * the bit enabled, PWM may freeze. That is, while one can still write
66          * to the register, it won't have an effect. Thus, we try to sleep long
67          * enough that the bit gets cleared and make sure the bit is not
68          * enabled while we update the configuration.
69          */
70         err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
71         if (err)
72                 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
73
74         return err;
75 }
76
77 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
78 {
79         if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {
80                 dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n");
81                 return -EBUSY;
82         }
83
84         return 0;
85 }
86
87 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
88                              int duty_ns, int period_ns)
89 {
90         unsigned long long on_time_div;
91         unsigned long c = lpwm->info->clk_rate, base_unit_range;
92         unsigned long long base_unit, freq = NSEC_PER_SEC;
93         u32 ctrl;
94
95         do_div(freq, period_ns);
96
97         /*
98          * The equation is:
99          * base_unit = round(base_unit_range * freq / c)
100          */
101         base_unit_range = BIT(lpwm->info->base_unit_bits);
102         freq *= base_unit_range;
103
104         base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
105         /* base_unit must not be 0 and we also want to avoid overflowing it */
106         base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
107
108         on_time_div = 255ULL * duty_ns;
109         do_div(on_time_div, period_ns);
110         on_time_div = 255ULL - on_time_div;
111
112         ctrl = pwm_lpss_read(pwm);
113         ctrl &= ~PWM_ON_TIME_DIV_MASK;
114         ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
115         ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
116         ctrl |= on_time_div;
117
118         pwm_lpss_write(pwm, ctrl);
119         pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
120 }
121
122 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
123 {
124         if (cond)
125                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
126 }
127
128 static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
129                                    struct pwm_device *pwm,
130                                    const struct pwm_state *state)
131 {
132         int ret;
133
134         ret = pwm_lpss_is_updating(pwm);
135         if (ret)
136                 return ret;
137
138         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
139         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
140         ret = pwm_lpss_wait_for_update(pwm);
141         if (ret)
142                 return ret;
143
144         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
145         return 0;
146 }
147
148 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
149                           const struct pwm_state *state)
150 {
151         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
152         int ret = 0;
153
154         if (state->enabled) {
155                 if (!pwm_is_enabled(pwm)) {
156                         pm_runtime_get_sync(chip->dev);
157                         ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
158                         if (ret)
159                                 pm_runtime_put(chip->dev);
160                 } else {
161                         ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
162                 }
163         } else if (pwm_is_enabled(pwm)) {
164                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
165                 pm_runtime_put(chip->dev);
166         }
167
168         return ret;
169 }
170
171 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
172                                struct pwm_state *state)
173 {
174         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
175         unsigned long base_unit_range;
176         unsigned long long base_unit, freq, on_time_div;
177         u32 ctrl;
178
179         pm_runtime_get_sync(chip->dev);
180
181         base_unit_range = BIT(lpwm->info->base_unit_bits);
182
183         ctrl = pwm_lpss_read(pwm);
184         on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
185         base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
186
187         freq = base_unit * lpwm->info->clk_rate;
188         do_div(freq, base_unit_range);
189         if (freq == 0)
190                 state->period = NSEC_PER_SEC;
191         else
192                 state->period = NSEC_PER_SEC / (unsigned long)freq;
193
194         on_time_div *= state->period;
195         do_div(on_time_div, 255);
196         state->duty_cycle = on_time_div;
197
198         state->polarity = PWM_POLARITY_NORMAL;
199         state->enabled = !!(ctrl & PWM_ENABLE);
200
201         pm_runtime_put(chip->dev);
202 }
203
204 static const struct pwm_ops pwm_lpss_ops = {
205         .apply = pwm_lpss_apply,
206         .get_state = pwm_lpss_get_state,
207         .owner = THIS_MODULE,
208 };
209
210 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
211                                      const struct pwm_lpss_boardinfo *info)
212 {
213         struct pwm_lpss_chip *lpwm;
214         unsigned long c;
215         int i, ret;
216         u32 ctrl;
217
218         if (WARN_ON(info->npwm > MAX_PWMS))
219                 return ERR_PTR(-ENODEV);
220
221         lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
222         if (!lpwm)
223                 return ERR_PTR(-ENOMEM);
224
225         lpwm->regs = devm_ioremap_resource(dev, r);
226         if (IS_ERR(lpwm->regs))
227                 return ERR_CAST(lpwm->regs);
228
229         lpwm->info = info;
230
231         c = lpwm->info->clk_rate;
232         if (!c)
233                 return ERR_PTR(-EINVAL);
234
235         lpwm->chip.dev = dev;
236         lpwm->chip.ops = &pwm_lpss_ops;
237         lpwm->chip.npwm = info->npwm;
238
239         ret = devm_pwmchip_add(dev, &lpwm->chip);
240         if (ret) {
241                 dev_err(dev, "failed to add PWM chip: %d\n", ret);
242                 return ERR_PTR(ret);
243         }
244
245         for (i = 0; i < lpwm->info->npwm; i++) {
246                 ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
247                 if (ctrl & PWM_ENABLE)
248                         pm_runtime_get(dev);
249         }
250
251         return lpwm;
252 }
253 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
254
255 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
256 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
257 MODULE_LICENSE("GPL v2");