drivers/pwm/pwm-lpc32xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/err.h>
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pwm.h>
  15 #include <linux/slab.h>
  16
  17 struct lpc32xx_pwm_chip {
  18         struct pwm_chip chip;
  19         struct clk *clk;
  20         void __iomem *base;
  21 };
  22
  23 #define PWM_ENABLE      BIT(31)
  24 #define PWM_PIN_LEVEL   BIT(30)
  25
  26 #define to_lpc32xx_pwm_chip(_chip) \
  27         container_of(_chip, struct lpc32xx_pwm_chip, chip)
  28
  29 static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  30                               int duty_ns, int period_ns)
  31 {
  32         struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  33         unsigned long long c;
  34         int period_cycles, duty_cycles;
  35         u32 val;
  36         c = clk_get_rate(lpc32xx->clk);
  37
  38         /* The highest acceptable divisor is 256, which is represented by 0 */
  39         period_cycles = div64_u64(c * period_ns,
  40                                (unsigned long long)NSEC_PER_SEC * 256);
  41         if (!period_cycles || period_cycles > 256)
  42                 return -ERANGE;
  43         if (period_cycles == 256)
  44                 period_cycles = 0;
  45
  46         /* Compute 256 x #duty/period value and care for corner cases */
  47         duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
  48                                 period_ns);
  49         if (!duty_cycles)
  50                 duty_cycles = 1;
  51         if (duty_cycles > 255)
  52                 duty_cycles = 255;
  53
  54         val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  55         val &= ~0xFFFF;
  56         val |= (period_cycles << 8) | duty_cycles;
  57         writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  58
  59         return 0;
  60 }
  61
  62 static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  63 {
  64         struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  65         u32 val;
  66         int ret;
  67
  68         ret = clk_prepare_enable(lpc32xx->clk);
  69         if (ret)
  70                 return ret;
  71
  72         val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  73         val |= PWM_ENABLE;
  74         writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  75
  76         return 0;
  77 }
  78
  79 static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  80 {
  81         struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  82         u32 val;
  83
  84         val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  85         val &= ~PWM_ENABLE;
  86         writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  87
  88         clk_disable_unprepare(lpc32xx->clk);
  89 }
  90
  91 static const struct pwm_ops lpc32xx_pwm_ops = {
  92         .config = lpc32xx_pwm_config,
  93         .enable = lpc32xx_pwm_enable,
  94         .disable = lpc32xx_pwm_disable,
  95         .owner = THIS_MODULE,
  96 };
  97
  98 static int lpc32xx_pwm_probe(struct platform_device *pdev)
  99 {
 100         struct lpc32xx_pwm_chip *lpc32xx;
 101         int ret;
 102         u32 val;
 103
 104         lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
 105         if (!lpc32xx)
 106                 return -ENOMEM;
 107
 108         lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
 109         if (IS_ERR(lpc32xx->base))
 110                 return PTR_ERR(lpc32xx->base);
 111
 112         lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
 113         if (IS_ERR(lpc32xx->clk))
 114                 return PTR_ERR(lpc32xx->clk);
 115
 116         lpc32xx->chip.dev = &pdev->dev;
 117         lpc32xx->chip.ops = &lpc32xx_pwm_ops;
 118         lpc32xx->chip.npwm = 1;
 119
 120         /* If PWM is disabled, configure the output to the default value */
 121         val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
 122         val &= ~PWM_PIN_LEVEL;
 123         writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
 124
 125         ret = devm_pwmchip_add(&pdev->dev, &lpc32xx->chip);
 126         if (ret < 0) {
 127                 dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
 128                 return ret;
 129         }
 130
 131         return 0;
 132 }
 133
 134 static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
 135         { .compatible = "nxp,lpc3220-pwm", },
 136         { /* sentinel */ }
 137 };
 138 MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
 139
 140 static struct platform_driver lpc32xx_pwm_driver = {
 141         .driver = {
 142                 .name = "lpc32xx-pwm",
 143                 .of_match_table = lpc32xx_pwm_dt_ids,
 144         },
 145         .probe = lpc32xx_pwm_probe,
 146 };
 147 module_platform_driver(lpc32xx_pwm_driver);
 148
 149 MODULE_ALIAS("platform:lpc32xx-pwm");
 150 MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
 151 MODULE_DESCRIPTION("LPC32XX PWM Driver");
 152 MODULE_LICENSE("GPL v2");